JPH05159080A - Logical integrated circuit - Google Patents

Abstract

PURPOSE:To provide a technique which can design a clock distribution system comparatively easily making a clock skew to be minimum. CONSTITUTION:This circuit is designed by dividing a semiconductor chip 10 into the plural blocks 10a to 10d of which area are mostly equal one another, respectively/individually providing the clock distribution system including clock input terminals 1a to 1d, buffer circuits 3a to 3c and phase adjusting circuits for respective blocks and providing the clock distribution system in the shape of a tree for the respective blocks so that the wiring between respective nodes are equal in length and capacitance. Consequently, as the semiconductor 10 is divided into the plural blocks 10a to 10d, the wiring length from the clock input terminals 1a to 1d to flip-flops, etc., at ends become short so that the wiring designation of the equal length and capacity becomes easy, and a clock delay time from input terminals to the end circuits become short so that the absolute value of clock can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic integrated circuit technique and a technique particularly effective when applied to a clock signal supply system, for example, to a technique effectively applied to a clock signal distribution circuit in a logic LSI.

[0002]

2. Description of the Related Art Conventionally, in a logic LSI, the entire LSI may be operated in synchronization with one clock signal or a plurality of clock signals having different phases. In this case, the basic clock signal supplied from the outside
By distributing to each part of the flip-flop etc.,
Although operations such as decoding, memory read / write, and various operations are performed, if the wiring length from the clock distribution source to the supply destination is different, there is a deviation in the arrival timing of each clock (clock skew). .. If there is clock skew, there is a possibility that the flip-flop may take in an incorrect signal, or that the logic gate may generate an undesired whisker-like pulse at the output to malfunction the circuit. Therefore, in the clock synchronous LSI, the magnitude of the clock skew is
It becomes a factor that determines the performance (operating speed) of the LSI.

Therefore, in order to minimize this clock skew, a plurality of buffer circuits 3a, 3b, 3c, ... From the clock input terminal 1 of the LSI to the terminal flip-flop 2 are conventionally provided as shown in FIG. The clock supply lines 4 are provided and connected in a tree shape. That is, the clock is gradually distributed as 2 times, 4 times, 8 times, etc., and the clock capacity is adjusted so that the load capacity (the wiring capacity, the input capacity of the gate of the next stage, etc.) of the buffer circuit of each stage is matched. The method of designing the distribution system was adopted (CICC'91
Mikio Yamagashi et al. "A Two-Ch
ipCMOS64b Mainframe Proce
sosor Chipset "P-P).

[0004]

[Problems to be Solved by the Invention] However, logical LS
The clock skew in I is not only the load capacitance of each buffer circuit, but also the performance variations of the transistors that make up the buffer circuit, power supply voltage variations, temperature variations, wiring capacitance variations, gate capacitance variations, wiring resistance variations, etc.
It is caused by various causes. On the other hand, since LSIs are becoming larger and more highly integrated in recent years, the distance from the clock input terminal to the flip-flops at the end becomes longer and more, and the wiring resistance becomes smaller as the pattern becomes finer. Get bigger. Therefore, the clock delay time from the clock input terminal to the terminal flip-flop or the like becomes long, and it becomes difficult to minimize the clock skew. Therefore, when trying to design a clock distribution system with the minimum clock skew by the above-mentioned conventional design method, there is a problem that the work is very troublesome and that there is a limit to the minimization of the clock skew. It was

An object of the present invention is to provide a design method capable of realizing a clock distribution system which minimizes clock skew relatively easily. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, the inside of a semiconductor chip is divided into a plurality of blocks having substantially the same area, and a clock distribution system including a clock input terminal and a buffer circuit connected to this terminal is independently configured for each block, and each block is Each stage is provided with a plurality of stages of buffer circuits, and the clock distribution system is configured in a tree shape that branches toward the end circuit of the clock supply destination, and the wiring between each stage of the buffer circuits has the same length and the same capacity. ,
The buffer circuits in each stage are designed to have the same fan-out number.

[0007]

Since the semiconductor chip is divided into a plurality of blocks, the wiring length from the clock input terminal to the flip-flop at the end is shortened, and the wiring design of equal length and equal capacity is facilitated and The clock delay time until reaching the end circuit is shortened, and the absolute value of the clock skew can be reduced.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a clock distribution system in a logic LSI to which the present invention is applied. In FIG. 1, 10 is a semiconductor chip on which elements and wirings forming an integrated circuit are formed, and 1a, 1b, 1c and 1d are pads formed on the semiconductor chip 10 as clock input terminals. In this embodiment, the semiconductor chip 10 is divided into blocks 10a, 10b, 10c and 10d of equal area,
The clock input terminals 1a, 1b, 1 for each block
c and 1d are provided.

A plurality of buffer circuits 3a, 3b, 3c ... Are cascaded in each block to form clock supply lines 4a, 4b, 4c .. Clock is 2 times, 4 times,
It is configured so that it is branched and distributed gradually as in 8 times. In addition, the wiring length between the buffer circuits and between the final buffer circuit and the flip-flop 2 as the terminal circuit is adjusted so that the load capacitances (the wiring capacitance and the input capacitance of the gate of the next stage, etc.) of the buffer circuits of the respective stages match. The number of fanouts of the buffer circuit in each stage is determined. Further, in this embodiment, even on the substrate on which the semiconductor chip 10 is mounted, the wirings 21a to 21d from the clock generation source 20 to the clock input terminals 1a, 1b, 1c and 1d have the same length and the same capacity. Is designed to be.

FIG. 2 shows a configuration example of a microcomputer chip as a suitable logic LSI to which the above-mentioned clock distribution system design method is applied. In the microcomputer of this embodiment, the chip is divided into four blocks, and the block 10a has an arithmetic logic unit ALU.
And floating point controller FCT and operation register CRG
Further, the block 10b further includes an instruction queue IQ, an instruction register IR and an instruction decoder IDC, and the block 10c further includes a multiplier controller MCT, a register file RGF, a multiplier array MRY, an address register ARG and an address conversion buffer circuit ACB. Block 10
Barrel shifter BST and data cache memory D
CMs are arranged respectively. And each block 1
Clock input terminals 1a, 1b, 1c and 1d are provided for the respective 0a, 10b, 10c and 10d, and a buffer circuit 3 for clock distribution and a supply line 4 are formed by the method shown in FIG. A clock signal is supplied to flip-flops and logic gates in the circuit block. Incidentally, 6a to 6d are input / output buffer circuits.

FIG. 3 shows a second embodiment of the clock distribution system according to the present invention. Also in this embodiment, the semiconductor chip is divided into four, and the clock input terminal 1, the buffer circuit 3, and the wiring 4 are formed for each block. FIG. 3 shows only the configuration of the clock distribution system in one of the blocks 10a. The configuration of the clock distribution system is similar to that of the embodiment shown in FIG. Therefore, in this embodiment, in addition to the clock input terminal 1, a terminal 11 to which a reference clock CKr having a lower frequency but the same phase as the clock signal CK input to the clock input terminal 1 is input is provided. In addition, a delay adjustment circuit 31 capable of adjusting the delay amount of the clock is connected between the first-stage buffer circuit 3a and the next-stage buffer circuit 3b of the clock distribution system. A buffer circuit 13 is connected to the reference clock input terminal 11, and the reference clock CKr is supplied to the phase comparison circuit 32 via the buffer circuit 13.

Further, the other input terminal of the phase comparison circuit 32 has a buffer circuit 3 at the final stage of the clock distribution system.
The clock CK ′ output from e is supplied, the phase difference from the reference clock CKr is detected, and a signal corresponding to the difference is supplied to the control circuit 15. The control circuit 33 is configured to control the delay adjustment circuit 31 so that the phase difference between the clock CK 'output from the final stage buffer circuit 3e and the reference clock CKr becomes zero. In this embodiment, each block 10
a, 10b, 10c, 10d clock input terminals 1a,
Even if the phase of the clock CK input to 1b, 1c, 1d is deviated, even if the delay of the clock signal from the clock input terminal to the terminal flip-flop is different for each clock, even the phase of the reference clock CKr is stable. If so, the phase of the clock CK 'supplied to the terminal circuit 2 such as a flip-flop can be matched in the entire LSI.

FIG. 4 shows a third embodiment of the clock distribution system according to the present invention. In this embodiment, one input terminal 1 for the clock CK is provided in the semiconductor chip 10, and the reference clock CKr input to the reference clock input terminal 11 is temporarily provided from the buffer circuit 13a to the buffer circuit 13b provided at the center of the chip. To the clock phase adjusting circuits 30a to 30d provided in each of the blocks 10a, 10b, 10c, and 10d by wiring of equal length. The clock phase adjusting circuits 30a to 30d are the same as in the above-described embodiment, the delay adjusting circuit 31, the phase comparing circuit 32, and the control circuit 33.
It can be configured by and.

Further, in this embodiment, the clock CK input to the only clock input terminal 1 is commonly supplied to each of the clock phase adjusting circuits 30a to 30d. In each block, a plurality of buffer circuits 3a, 3b, 3c ... Are connected in cascade to form clock supply lines 4a, 4b, 4c .. Circuits 30a-30
The clock CK ′ output from d is the buffer circuit 3
It is adapted to be distributed to the flip-flops 2 and the like at the end via b, 3c .... In addition, the wiring lengths of the buffer circuits and between the buffer circuits and the final buffer circuit and the flip-flop 2 as the end circuit and the wiring lengths of the respective stages are adjusted so that the load capacitances (the wiring capacitances and the input capacitances of the gates of the next stage, etc.) of the respective stages are matched. It is designed to determine the fanout number of the buffer circuit. In this embodiment, each block 1
Even if the phases of the clocks input to the clock phase adjusting circuits 30a to 30d of 0a, 10b, 10c, and 10d are deviated, the reference clock CKr has the same phase and is supplied to the terminal circuit such as a flip-flop. The phases of the clocks CK 'can be matched in the entire LSI.

FIG. 5 shows a structural example of the delay adjusting circuit 31. That is, the delay adjusting circuit 31 has a plurality of delay means D1, D2, D3, ... Is provided with a selector SEL, and the selector SEL is controlled by a control signal from the control circuit 33 to delay the clock signal CK from the buffer circuit 3a by delay means D1, D2, D3 ,.
A desired delay amount is given by passing any one of n.

In the above embodiment, four semiconductor chips are used.
The case of division is described, but in a so-called CCB-mounted semiconductor chip or the like in which solder bumps are formed on the entire surface of the chip, a clock can be directly input into the chip, and therefore, as in the above embodiment. Since the clock supply wiring from the clock input terminal to each block can be formed in equal length wiring without dividing into four,
The chip may be divided into 9 or 16 parts.

As described above, in the above embodiment, the inside of the semiconductor chip is divided into a plurality of blocks having substantially the same area, and each block includes a clock input terminal and a clock circuit including a buffer circuit connected to this terminal. The distribution system is configured independently, and a buffer circuit of multiple stages is provided for each block to configure the clock distribution system in a tree shape that gradually branches toward the end circuit of the clock supply destination, and between each stage buffer circuit. The wiring is designed to have the same length and the same capacity, and the number of fanouts of the buffer circuits in each stage is the same, so the wiring length from the clock input terminal to the terminal flip-flop is shortened. Wiring design of equal length and same capacity is easy, and the clock delay time from the input terminal to the end circuit is shortened. There is an effect that it is possible to reduce the absolute value of Kkusukyu.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, the case where the input clock is one phase has been described as an example, but the present invention is not limited to this, and is applicable to the case where a plurality of clocks having different phases are input. You can In that case, the clock distribution system may be designed for each clock by the design method of the above embodiment. However, in the embodiments of FIGS. 3 and 4, the reference clock CKr can be commonly used for each clock. In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is a field of application which is the background of the invention has been described. However, the present invention is not limited to this, and is applied to a semiconductor logic integrated circuit in general. can do.

[0019]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to design a clock distribution system that minimizes clock skew in a logic LSI relatively easily.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a clock distribution system in a logic LSI to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration example of a microcomputer chip as a suitable logic LSI to which the design method of the clock distribution system is applied.

FIG. 3 is a circuit configuration diagram showing a second embodiment of a clock distribution system in a logic LSI to which the present invention is applied.

FIG. 4 is a circuit configuration diagram showing a third embodiment of the clock distribution system in the logic LSI to which the present invention is applied.

FIG. 5 is a circuit configuration diagram showing a configuration example of a delay adjustment circuit in the logic integrated circuits of FIGS. 3 and 4;

FIG. 6 is a circuit configuration diagram showing an example of a conventional clock distribution circuit.

[Explanation of symbols]

 1a, 1b, 1c, 1d Clock input terminal (pad) 2 Terminal circuit (flip-flop) 3a, 3b, 3c Buffer circuit 4a, 4b, 4c Clock supply line 10 Semiconductor chip 10a, 10b, 10c, 10d block 30 Phase adjusting circuit 31 Delay adjustment circuit

Claims (3)

[Claims] 1. A semiconductor chip is divided into a plurality of blocks having substantially the same area, and a clock distribution system including a clock input terminal and a buffer circuit connected to this terminal is independently provided for each block. In addition, the clock distribution system for each block is gradually branched toward the end circuit of the clock supply destination, and the load of the buffer circuit of each stage is formed to be the same. Logic integrated circuit. 2. A semiconductor chip is divided into a plurality of blocks each having substantially the same area, and a clock distribution system including a clock input terminal, a buffer circuit connected to this terminal, and a phase adjusting circuit is independent for each block. The clock signal for reference supplied from the outside and the clock signal supplied to the terminal circuit via the clock distribution system are fed back to the phase adjustment circuit to adjust the phase of the clock signal. And a logic integrated circuit. 3. A semiconductor chip is divided into a plurality of blocks each having an area substantially equal to each other, and a clock distribution system including a clock buffer circuit and a phase adjustment circuit is independently configured for each block and externally provided. The reference clock signal supplied and the clock signal input from the common clock terminal are supplied to the phase adjustment circuit, and the phase of the clock signal is adjusted. Logic integrated circuit.