JP2000035831A - Low skew clock tree circuit using variable threshold voltage transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock tree circuit capable of controlling clock skew of a clock tree circuit, reduced in power consumption and low in clock skew. SOLUTION: This clock tree circuit uses a transistor having a threshold voltage variable well structure for a clock element. Here, it has phase comparator circuits 31 to 33 which perform comparison observation of skew values among respective elements 21 to 24 and output differential voltage and charge pump circuits 41 to 43 which make the differential voltage of the circuits 31 to 33 inputs and supply them as well potential to each well terminal of the elements 21 to 24, controls the switching speed of a clock tree circuit by adjusting the threshold voltage of each element 21 to 24 and reduces clock skew.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock tree circuit for distributing clocks, and more particularly to a clock skew between elements of a clock tree circuit using variable threshold voltage transistors.

[0002]

2. Description of the Related Art As the degree of integration of LSIs increases, the circuit scale increases and the operating speed increases. Conventionally, the well potential of each clock element of a clock tree circuit for distributing clocks is common as shown in FIG. 7, and the switching speed of each clock element in a chip of the clock tree circuit varies depending on manufacturing conditions and the like. In this case, the clock skew of the clock tree circuit is disadvantageously increased.

[0003]

When the switching speed of each clock element cannot be individually controlled and the switching speed between the clock elements varies within a chip depending on manufacturing conditions and the like, the well of each clock element is changed. The potential is common, and the threshold voltage of each clock element, that is,
Since it is impossible to individually control the switching speed, there is a disadvantage that the clock skew increases.

Japanese Patent Application Laid-Open No. 9-92723 discloses a semiconductor device which solves the above-mentioned disadvantages. The disclosed semiconductor device has a skew observation circuit between internal clocks, and a load increasing / decreasing circuit for increasing a load of a clock whose phase is relatively advanced between clocks, and a clock source value of an observation value of the variation observation circuit. And a sequence maintaining circuit for fixing the detection state in order from the closest one and fixing the load of the internal clock by the load increasing / decreasing circuit.

However, the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 9-92723 has a problem in terms of power consumption as compared with a conventional clock tree circuit in that a larger number of circuits are added.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock tree circuit with low power consumption and low clock skew by controlling the clock skew of the clock tree circuit.

[0007]

According to the present invention, a low skew clock tree circuit using a variable threshold voltage transistor is provided.
A clock tree circuit using a transistor having a well structure with a variable threshold voltage as a clock element, comprising: comparison observation means for comparing and observing a skew value between clock elements; and controlling a well potential of each clock element from the comparison observation result. It has a control means, in which the switching speed of the clock tree circuit is controlled and the clock skew is reduced by controlling the well potential and adjusting the threshold voltage. Further, the comparison and observation means for comparing and observing the skew value between the clock elements may be a phase comparison circuit that compares the phases between the clock elements and outputs a difference voltage.

The control means for controlling the well potential of each clock element based on the comparison observation result is a charge pump which receives the difference voltage of the phase comparison circuit as an input and supplies it as a well potential to the N-well terminal of the P-type MOS transistor of the clock element. It may be a circuit and a charge pump circuit that receives the differential voltage of the phase comparison circuit and supplies the P-well terminal of the N-type MOS transistor of the clock element as a well potential.

A low skew clock tree circuit using a variable threshold voltage transistor according to the present invention compares and observes a clock skew value between clock elements with a clock tree circuit composed of a transistor having a well structure with a variable threshold voltage. A clock skew comparison / observation circuit, and a well potential control circuit for individually controlling a well potential of each clock element based on a measurement result of the clock skew comparison / observation circuit; The switching speed of each clock element is controlled by adjusting the threshold voltage by individually controlling the well potential of each clock element by a well potential control circuit based on the measurement results, and controlling the clock skew with other clock elements. To reduce.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing the principle of the present invention. A clock tree circuit 1 composed of a transistor having a well structure with a variable threshold voltage is compared with a clock skew value between respective clock elements, and a voltage is calculated. The clock skew comparison / observation circuit 2 for conversion and a well potential control circuit 3 for individually controlling the well potential of each clock element based on the measurement result of the clock skew comparison / observation circuit 2.

FIG. 2 is a logic circuit diagram showing the configuration of the clock tree circuit 1 composed of transistors having a well structure with variable threshold voltage shown in FIG. In FIG. 2, a clock supply source 25 distributes a clock to clock elements 21, 22, 23, and 24. The clock element 21 distributes a clock to four clock elements as shown in FIG. Here, clocks are distributed to four clock elements, but the number is not limited.

FIG. 3 is a circuit diagram at the transistor level of each clock element of FIG. The well potential of the clock element used in the clock tree of the present invention is separated into an N-well terminal CTR * A of a P-type MOS transistor and a P-well terminal CTR * B of an N-type MOS transistor. It can be controlled individually. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing a circuit configuration of the first embodiment of the present invention.
Is a block diagram showing a circuit configuration of a second embodiment of the present invention,
FIG. 6 is a block diagram showing the circuit configuration of the third embodiment of the present invention.

FIG. 4 shows a phase comparison circuit for comparing the phases between the remaining clock elements 21, 22, and 23 based on the clock element 24 among the clock elements to be compared, and outputting a difference voltage. 31, 32, and 33, and charge pump circuits 41, 42, and 43 that receive the difference voltage of the phase comparison circuit as an input and supply the N-well terminal of the P-type MOS transistor of the clock element as a well potential.

FIG. 5 shows a phase in which the phases between the remaining clock elements 21, 22, and 23 are compared based on the clock element 24 among the clock elements to be compared, and a difference voltage is output. An N-type MOS of a clock element which receives the difference voltage of the comparison circuits 31, 32, 33 and the phase comparison circuit as an input.
It comprises charge pump circuits 41, 42 and 43 for supplying a P-well terminal of the transistor as a well potential.

Further, FIG. 6 compares the phases between the remaining clock elements 21, 22, and 23 based on the clock element 24 among the clock elements to be compared.
The phase comparators 31 to 36 for outputting a differential voltage, and the charge supplied with the differential voltage of the phase comparators 31, 33, and 35 to be supplied as well potential to the N-well terminals of the P-type MOS transistors of the clock elements 21, 22, and 23. Pump circuit 4
1, 43, 45 and the differential voltages of the phase comparison circuits 32, 34, 36 as inputs, and the N-type M of the clock elements 21, 22, 23
The charge pump circuit 42, 44, 46 supplies a P-well terminal of the OS transistor as a well potential.

Returning to FIG. 1, the clock tree circuit 1 having the configuration described above observes the clock skew value between the clock elements with the clock skew comparison observation circuit 2 corresponding to the phase comparison circuit, and from the measurement result. The switching speed of each clock element is controlled by individually controlling the well potential of each clock element by a well potential control circuit 3 corresponding to a charge pump circuit and adjusting the threshold voltage.
Clock skew with another clock element is reduced.

[0018]

According to the present invention, a clock tree circuit composed of a transistor having a well structure with a variable threshold voltage compares and observes a clock skew value between clock elements, and from the measurement result, the well of each clock element is measured. By individually controlling the potential and adjusting the threshold voltage, the switching speed of each clock element can be controlled, and the clock skew with other clock elements can be reduced.

Further, according to the present invention, a clock tree circuit composed of a transistor having a well structure with a variable threshold voltage directly measures and controls the clock skew. There is an effect that a skewed clock tree circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing one embodiment of the present invention.

FIG. 2 is a logic circuit diagram illustrating a configuration of a clock tree circuit 1 including a transistor having a well structure with a variable threshold voltage in FIG.

FIG. 3 is a circuit diagram of a transistor level of each clock element of FIG. 2;

FIG. 4 is a block diagram showing a circuit configuration of the first embodiment of the present invention.

FIG. 5 is a block diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 6 is a block diagram showing a circuit configuration according to a third embodiment of the present invention.

FIG. 7 is a functional block diagram showing a conventional example.

[Explanation of symbols]

Reference Signs List 1 Clock tree circuit using VT-CMOS 2 Clock skew comparison observation circuit 3 Well potential control circuit 21, 22, 23, 24 Clock element 25 Clock supply source clock element 31, 32, 33, 34, 35, 36 Phase comparison circuit 41, 42, 43, 44, 45, 46 charge pump circuit

Claims (6)

[Claims] 1. A clock tree circuit that uses a transistor having a well structure with a variable threshold voltage as a clock element and distributes clocks according to a clock tree, wherein the comparison and observation means compares and observes a skew value between the clock elements. A control means for controlling a well potential of each clock element from the observation result; controlling the well potential by the control means to adjust a threshold voltage, thereby controlling a switching speed of the clock tree circuit and reducing clock skew; A low skew clock tree circuit using a variable threshold voltage transistor. 2. The variable threshold voltage transistor according to claim 1, wherein said comparison and observation means for comparing and observing a skew value between each clock element is a phase comparison circuit for comparing phases between clock elements and outputting a difference voltage. Low skew clock tree circuit using. 3. A comparison / observation means for comparing and observing a skew value between the clock elements, wherein a phase between the clock elements based on an arbitrary clock element among the clock elements to be compared is determined. 2. The method according to claim 1, wherein a difference voltage is output.
Or a low skew clock tree circuit using the variable threshold voltage transistor according to 2. 4. A control means for controlling a well potential of each clock element based on the comparison observation result, wherein the difference voltage of the phase comparison circuit is input and the P element of the clock element is controlled.
4. A low skew clock tree circuit using a variable threshold voltage transistor according to claim 1, which is a charge pump circuit for supplying a well potential to an N-well terminal of a type MOS transistor. 5. A control means for controlling a well potential of each clock element based on the comparison observation result, comprising:
4. A charge pump circuit for supplying a well potential to a P-well terminal of a type MOS transistor.
A low skew clock tree circuit using the variable threshold voltage transistor according to any one of the above. 6. A control means for controlling a well potential of each clock element based on the comparison observation result, comprising:
A charge pump circuit for supplying a well potential to an N-well terminal of a type MOS transistor;
4. A charge pump circuit for supplying a well potential to a P-well terminal of a type MOS transistor.
A low skew clock tree circuit using the variable threshold voltage transistor according to any one of the above.