JP2000035831A - Low skew clock tree circuit using variable threshold voltage transistor - Google Patents

Low skew clock tree circuit using variable threshold voltage transistor

Info

Publication number
JP2000035831A
JP2000035831A JP10205309A JP20530998A JP2000035831A JP 2000035831 A JP2000035831 A JP 2000035831A JP 10205309 A JP10205309 A JP 10205309A JP 20530998 A JP20530998 A JP 20530998A JP 2000035831 A JP2000035831 A JP 2000035831A
Authority
JP
Japan
Prior art keywords
clock
circuit
threshold voltage
skew
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10205309A
Other languages
Japanese (ja)
Inventor
Masaharu Mizuno
雅春 水野
Original Assignee
Nec Corp
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nec Corp, 日本電気株式会社 filed Critical Nec Corp
Priority to JP10205309A priority Critical patent/JP2000035831A/en
Publication of JP2000035831A publication Critical patent/JP2000035831A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a clock tree circuit capable of controlling clock skew of a clock tree circuit, reduced in power consumption and low in clock skew. SOLUTION: This clock tree circuit uses a transistor having a threshold voltage variable well structure for a clock element. Here, it has phase comparator circuits 31 to 33 which perform comparison observation of skew values among respective elements 21 to 24 and output differential voltage and charge pump circuits 41 to 43 which make the differential voltage of the circuits 31 to 33 inputs and supply them as well potential to each well terminal of the elements 21 to 24, controls the switching speed of a clock tree circuit by adjusting the threshold voltage of each element 21 to 24 and reduces clock skew.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock tree circuit for distributing clocks, and more particularly to a clock skew between elements of a clock tree circuit using variable threshold voltage transistors.

[0002]

2. Description of the Related Art As the degree of integration of LSIs increases, the circuit scale increases and the operating speed increases. Conventionally, the well potential of each clock element of a clock tree circuit for distributing clocks is common as shown in FIG. 7, and the switching speed of each clock element in a chip of the clock tree circuit varies depending on manufacturing conditions and the like. In this case, the clock skew of the clock tree circuit is disadvantageously increased.

[0003]

When the switching speed of each clock element cannot be individually controlled and the switching speed between the clock elements varies within a chip depending on manufacturing conditions and the like, the well of each clock element is changed. The potential is common, and the threshold voltage of each clock element, that is,
Since it is impossible to individually control the switching speed, there is a disadvantage that the clock skew increases.

Japanese Patent Application Laid-Open No. 9-92723 discloses a semiconductor device which solves the above-mentioned disadvantages. The disclosed semiconductor device has a skew observation circuit between internal clocks, and a load increasing / decreasing circuit for increasing a load of a clock whose phase is relatively advanced between clocks, and a clock source value of an observation value of the variation observation circuit. And a sequence maintaining circuit for fixing the detection state in order from the closest one and fixing the load of the internal clock by the load increasing / decreasing circuit.

However, the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 9-92723 has a problem in terms of power consumption as compared with a conventional clock tree circuit in that a larger number of circuits are added.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock tree circuit with low power consumption and low clock skew by controlling the clock skew of the clock tree circuit.

[0007]

According to the present invention, a low skew clock tree circuit using a variable threshold voltage transistor is provided.
A clock tree circuit using a transistor having a well structure with a variable threshold voltage as a clock element, comprising: comparison observation means for comparing and observing a skew value between clock elements; and controlling a well potential of each clock element from the comparison observation result. It has a control means, in which the switching speed of the clock tree circuit is controlled and the clock skew is reduced by controlling the well potential and adjusting the threshold voltage. Further, the comparison and observation means for comparing and observing the skew value between the clock elements may be a phase comparison circuit that compares the phases between the clock elements and outputs a difference voltage.

The control means for controlling the well potential of each clock element based on the comparison observation result is a charge pump which receives the difference voltage of the phase comparison circuit as an input and supplies it as a well potential to the N-well terminal of the P-type MOS transistor of the clock element. It may be a circuit and a charge pump circuit that receives the differential voltage of the phase comparison circuit and supplies the P-well terminal of the N-type MOS transistor of the clock element as a well potential.

A low skew clock tree circuit using a variable threshold voltage transistor according to the present invention compares and observes a clock skew value between clock elements with a clock tree circuit composed of a transistor having a well structure with a variable threshold voltage. A clock skew comparison / observation circuit, and a well potential control circuit for individually controlling a well potential of each clock element based on a measurement result of the clock skew comparison / observation circuit; The switching speed of each clock element is controlled by adjusting the threshold voltage by individually controlling the well potential of each clock element by a well potential control circuit based on the measurement results, and controlling the clock skew with other clock elements. To reduce.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing the principle of the present invention. A clock tree circuit 1 composed of a transistor having a well structure with a variable threshold voltage is compared with a clock skew value between respective clock elements, and a voltage is calculated. The clock skew comparison / observation circuit 2 for conversion and a well potential control circuit 3 for individually controlling the well potential of each clock element based on the measurement result of the clock skew comparison / observation circuit 2.

FIG. 2 is a logic circuit diagram showing the configuration of the clock tree circuit 1 composed of transistors having a well structure with variable threshold voltage shown in FIG. In FIG. 2, a clock supply source 25 distributes a clock to clock elements 21, 22, 23, and 24. The clock element 21 distributes a clock to four clock elements as shown in FIG. Here, clocks are distributed to four clock elements, but the number is not limited.

FIG. 3 is a circuit diagram at the transistor level of each clock element of FIG. The well potential of the clock element used in the clock tree of the present invention is separated into an N-well terminal CTR * A of a P-type MOS transistor and a P-well terminal CTR * B of an N-type MOS transistor. It can be controlled individually. Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a block diagram showing a circuit configuration of the first embodiment of the present invention.
Is a block diagram showing a circuit configuration of a second embodiment of the present invention,
FIG. 6 is a block diagram showing the circuit configuration of the third embodiment of the present invention.

FIG. 4 shows a phase comparison circuit for comparing the phases between the remaining clock elements 21, 22, and 23 based on the clock element 24 among the clock elements to be compared, and outputting a difference voltage. 31, 32, and 33, and charge pump circuits 41, 42, and 43 that receive the difference voltage of the phase comparison circuit as an input and supply the N-well terminal of the P-type MOS transistor of the clock element as a well potential.

FIG. 5 shows a phase in which the phases between the remaining clock elements 21, 22, and 23 are compared based on the clock element 24 among the clock elements to be compared, and a difference voltage is output. An N-type MOS of a clock element which receives the difference voltage of the comparison circuits 31, 32, 33 and the phase comparison circuit as an input.
It comprises charge pump circuits 41, 42 and 43 for supplying a P-well terminal of the transistor as a well potential.

Further, FIG. 6 compares the phases between the remaining clock elements 21, 22, and 23 based on the clock element 24 among the clock elements to be compared.
The phase comparators 31 to 36 for outputting a differential voltage, and the charge supplied with the differential voltage of the phase comparators 31, 33, and 35 to be supplied as well potential to the N-well terminals of the P-type MOS transistors of the clock elements 21, 22, and 23. Pump circuit 4
1, 43, 45 and the differential voltages of the phase comparison circuits 32, 34, 36 as inputs, and the N-type M of the clock elements 21, 22, 23
The charge pump circuit 42, 44, 46 supplies a P-well terminal of the OS transistor as a well potential.

Returning to FIG. 1, the clock tree circuit 1 having the configuration described above observes the clock skew value between the clock elements with the clock skew comparison observation circuit 2 corresponding to the phase comparison circuit, and from the measurement result. The switching speed of each clock element is controlled by individually controlling the well potential of each clock element by a well potential control circuit 3 corresponding to a charge pump circuit and adjusting the threshold voltage.
Clock skew with another clock element is reduced.

[0018]

According to the present invention, a clock tree circuit composed of a transistor having a well structure with a variable threshold voltage compares and observes a clock skew value between clock elements, and from the measurement result, the well of each clock element is measured. By individually controlling the potential and adjusting the threshold voltage, the switching speed of each clock element can be controlled, and the clock skew with other clock elements can be reduced.

Further, according to the present invention, a clock tree circuit composed of a transistor having a well structure with a variable threshold voltage directly measures and controls the clock skew. There is an effect that a skewed clock tree circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing one embodiment of the present invention.

FIG. 2 is a logic circuit diagram illustrating a configuration of a clock tree circuit 1 including a transistor having a well structure with a variable threshold voltage in FIG.

FIG. 3 is a circuit diagram of a transistor level of each clock element of FIG. 2;

FIG. 4 is a block diagram showing a circuit configuration of the first embodiment of the present invention.

FIG. 5 is a block diagram showing a circuit configuration of a second embodiment of the present invention.

FIG. 6 is a block diagram showing a circuit configuration according to a third embodiment of the present invention.

FIG. 7 is a functional block diagram showing a conventional example.

[Explanation of symbols]

Reference Signs List 1 Clock tree circuit using VT-CMOS 2 Clock skew comparison observation circuit 3 Well potential control circuit 21, 22, 23, 24 Clock element 25 Clock supply source clock element 31, 32, 33, 34, 35, 36 Phase comparison circuit 41, 42, 43, 44, 45, 46 charge pump circuit

Claims (6)

[Claims]
1. A clock tree circuit that uses a transistor having a well structure with a variable threshold voltage as a clock element and distributes clocks according to a clock tree, wherein the comparison and observation means compares and observes a skew value between the clock elements. A control means for controlling a well potential of each clock element from the observation result; controlling the well potential by the control means to adjust a threshold voltage, thereby controlling a switching speed of the clock tree circuit and reducing clock skew; A low skew clock tree circuit using a variable threshold voltage transistor.
2. The variable threshold voltage transistor according to claim 1, wherein said comparison and observation means for comparing and observing a skew value between each clock element is a phase comparison circuit for comparing phases between clock elements and outputting a difference voltage. Low skew clock tree circuit using.
3. A comparison / observation means for comparing and observing a skew value between the clock elements, wherein a phase between the clock elements based on an arbitrary clock element among the clock elements to be compared is determined. 2. The method according to claim 1, wherein a difference voltage is output.
Or a low skew clock tree circuit using the variable threshold voltage transistor according to 2.
4. A control means for controlling a well potential of each clock element based on the comparison observation result, wherein the difference voltage of the phase comparison circuit is input and the P element of the clock element is controlled.
4. A low skew clock tree circuit using a variable threshold voltage transistor according to claim 1, which is a charge pump circuit for supplying a well potential to an N-well terminal of a type MOS transistor.
5. A control means for controlling a well potential of each clock element based on the comparison observation result, comprising:
4. A charge pump circuit for supplying a well potential to a P-well terminal of a type MOS transistor.
A low skew clock tree circuit using the variable threshold voltage transistor according to any one of the above.
6. A control means for controlling a well potential of each clock element based on the comparison observation result, comprising:
A charge pump circuit for supplying a well potential to an N-well terminal of a type MOS transistor;
4. A charge pump circuit for supplying a well potential to a P-well terminal of a type MOS transistor.
A low skew clock tree circuit using the variable threshold voltage transistor according to any one of the above.
JP10205309A 1998-07-21 1998-07-21 Low skew clock tree circuit using variable threshold voltage transistor Pending JP2000035831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10205309A JP2000035831A (en) 1998-07-21 1998-07-21 Low skew clock tree circuit using variable threshold voltage transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10205309A JP2000035831A (en) 1998-07-21 1998-07-21 Low skew clock tree circuit using variable threshold voltage transistor

Publications (1)

Publication Number Publication Date
JP2000035831A true JP2000035831A (en) 2000-02-02

Family

ID=16504827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10205309A Pending JP2000035831A (en) 1998-07-21 1998-07-21 Low skew clock tree circuit using variable threshold voltage transistor

Country Status (1)

Country Link
JP (1) JP2000035831A (en)

Cited By (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002312058A (en) * 2001-04-11 2002-10-25 Mitsubishi Electric Corp Semiconductor integrated circuit
WO2003036313A1 (en) * 2001-10-25 2003-05-01 Advantest Corporation Clock/skew measurement apparatus and clock/skew measurement method
US6873939B1 (en) 2001-02-02 2005-03-29 Rambus Inc. Method and apparatus for evaluating and calibrating a signaling system
US6877054B2 (en) 2001-07-16 2005-04-05 Rambus Inc. Method and apparatus for position dependent data scheduling
US6897699B1 (en) * 2002-07-19 2005-05-24 Rambus Inc. Clock distribution network with process, supply-voltage, and temperature compensation
US6909387B2 (en) 2002-04-25 2005-06-21 Rambus Inc. Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy
US6911853B2 (en) 2002-03-22 2005-06-28 Rambus Inc. Locked loop with dual rail regulation
US6920402B1 (en) 2001-03-07 2005-07-19 Rambus Inc. Technique for determining performance characteristics of electronic devices and systems
US6922091B2 (en) 2002-09-03 2005-07-26 Rambus Inc. Locked loop circuit with clock hold function
US6928128B1 (en) 1999-05-03 2005-08-09 Rambus Inc. Clock alignment circuit having a self regulating voltage supply
US6952123B2 (en) 2002-03-22 2005-10-04 Rambus Inc. System with dual rail regulated locked loop
US6961862B2 (en) 2004-03-17 2005-11-01 Rambus, Inc. Drift tracking feedback for communication channels
US6960948B2 (en) 2002-03-22 2005-11-01 Rambus Inc. System with phase jumping locked loop circuit
US6976114B1 (en) 2001-01-25 2005-12-13 Rambus Inc. Method and apparatus for simultaneous bidirectional signaling in a bus topology
US6982922B2 (en) 1999-10-19 2006-01-03 Rambus Inc. Single-clock, strobeless signaling system
US6998892B1 (en) 2002-02-13 2006-02-14 Rambus Inc. Method and apparatus for accommodating delay variations among multiple signals
US6998889B2 (en) 2003-08-11 2006-02-14 Rambus Inc. Circuit, apparatus and method for obtaining a lock state value
US7039118B1 (en) 1999-08-11 2006-05-02 Rambus Inc. High speed communication system with a feedback synchronization loop
US7089442B2 (en) 2003-02-07 2006-08-08 Rambus Inc. Fault-tolerant clock generator
US7095789B2 (en) 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US7099424B1 (en) 2001-08-28 2006-08-29 Rambus Inc. Clock data recovery with selectable phase control
US7119549B2 (en) 2003-02-25 2006-10-10 Rambus Inc. Output calibrator with dynamic precision
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US7129739B2 (en) 2002-02-19 2006-10-31 Rambus Inc. Method and apparatus for selectably providing single-ended and differential signaling with controllable impedence and transition time
US7137048B2 (en) 2001-02-02 2006-11-14 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US7135903B2 (en) 2002-09-03 2006-11-14 Rambus Inc. Phase jumping locked loop circuit
US7138877B2 (en) 2004-04-21 2006-11-21 Rambus Inc. PLL and method for providing a single/multiple adjustable frequency range
US7149856B2 (en) 1997-10-10 2006-12-12 Rambus Inc. Method and apparatus for adjusting the performance of a synchronous memory system
US7148699B1 (en) 2002-06-24 2006-12-12 Rambus Inc. Technique for calibrating electronic devices
US7176721B2 (en) 2003-12-17 2007-02-13 Rambus Inc. Signal receiver with data precessing function
US7190754B1 (en) 2001-12-24 2007-03-13 Rambus Inc. Transceiver with selectable data rate
US7231306B1 (en) 2002-04-30 2007-06-12 Rambus Inc. Method and apparatus for calibrating static timing offsets across multiple outputs
US7268605B2 (en) 2004-06-14 2007-09-11 Rambus, Inc. Technique for operating a delay circuit
US7275171B2 (en) 2003-05-22 2007-09-25 Rambus Inc. Method and apparatus for programmable sampling clock edge selection
US7298807B2 (en) 2003-02-11 2007-11-20 Rambus Inc. Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incoming serial data
US7376042B2 (en) * 2006-07-25 2008-05-20 Qimonda Ag Boosted clock circuit for semiconductor memory
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US7400671B2 (en) 2004-01-28 2008-07-15 Rambus Inc. Periodic calibration for communication channels by drift tracking
US7403044B2 (en) * 2005-04-26 2008-07-22 Micron Technology, Inc. Method of producing balanced data output
US7412016B2 (en) 2003-04-09 2008-08-12 Rambus Inc. Data-level clock recovery
US7437584B2 (en) 2006-02-27 2008-10-14 Atmel Corporation Apparatus and method for reducing power consumption in electronic devices
US7489739B2 (en) 2004-09-17 2009-02-10 Rambus, Inc. Method and apparatus for data recovery
US7516029B2 (en) 2004-06-09 2009-04-07 Rambus, Inc. Communication channel calibration using feedback
US7571406B2 (en) 2005-08-04 2009-08-04 Freescale Semiconductor, Inc. Clock tree adjustable buffer
US7668271B2 (en) 2003-09-30 2010-02-23 Rambus Inc. Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data
US7724590B2 (en) 2004-09-15 2010-05-25 Rambus Inc. Memory controller with multiple delayed timing signals
US7765074B2 (en) 2003-02-11 2010-07-27 Rambus Inc. Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit
US7978754B2 (en) 2004-05-28 2011-07-12 Rambus Inc. Communication channel calibration with nonvolatile parameter store for recovery
US8063509B2 (en) * 2007-03-20 2011-11-22 Fujitsu Limited Power supply voltage adjusting apparatus, recording medium, and power supply voltage adjusting method
US8069378B2 (en) 2001-02-02 2011-11-29 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US8073009B2 (en) 2004-01-28 2011-12-06 Rambus Inc. Adaptive allocation of I/O bandwidth using a configurable interconnect topology
US8214616B2 (en) 2001-04-24 2012-07-03 Rambus Inc. Memory controller device having timing offset capability
US8264906B2 (en) 2007-05-29 2012-09-11 Rambus Inc. Adjusting clock error across a circuit interface
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US8422568B2 (en) 2004-01-28 2013-04-16 Rambus Inc. Communication channel calibration for drift conditions
US9071407B2 (en) 2012-05-02 2015-06-30 Ramnus Inc. Receiver clock test circuitry and related methods and apparatuses
US9577816B2 (en) 2012-03-13 2017-02-21 Rambus Inc. Clock and data recovery having shared clock generator
US9824740B2 (en) 2002-06-20 2017-11-21 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
US10706910B2 (en) 2019-02-25 2020-07-07 Rambus Inc. Memory controller

Cited By (157)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7149856B2 (en) 1997-10-10 2006-12-12 Rambus Inc. Method and apparatus for adjusting the performance of a synchronous memory system
US7337294B2 (en) 1997-10-10 2008-02-26 Rambus Inc. Method and apparatus for adjusting the performance of a synchronous memory system
US6928128B1 (en) 1999-05-03 2005-08-09 Rambus Inc. Clock alignment circuit having a self regulating voltage supply
US7593470B2 (en) 1999-08-11 2009-09-22 Rambus Inc. High-speed communication system with a feedback synchronization loop
US7039118B1 (en) 1999-08-11 2006-05-02 Rambus Inc. High speed communication system with a feedback synchronization loop
US7092449B2 (en) 1999-08-11 2006-08-15 Rambus Inc. High-speed communication system with a feedback synchronization loop
US6990042B2 (en) 1999-10-19 2006-01-24 Rambus Inc. Single-clock, strobeless signaling system
US7663966B2 (en) 1999-10-19 2010-02-16 Rambus, Inc. Single-clock, strobeless signaling system
US6982922B2 (en) 1999-10-19 2006-01-03 Rambus Inc. Single-clock, strobeless signaling system
US6976114B1 (en) 2001-01-25 2005-12-13 Rambus Inc. Method and apparatus for simultaneous bidirectional signaling in a bus topology
US7921236B2 (en) 2001-01-25 2011-04-05 Rambus Inc. Method and apparatus for simultaneous bidirectional signaling in a bus topology
US8260979B2 (en) 2001-01-25 2012-09-04 Rambus Inc. Method and apparatus for simultaneous bidirectional signaling in a bus topology
US7137048B2 (en) 2001-02-02 2006-11-14 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US6873939B1 (en) 2001-02-02 2005-03-29 Rambus Inc. Method and apparatus for evaluating and calibrating a signaling system
US8069378B2 (en) 2001-02-02 2011-11-29 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US7360127B2 (en) 2001-02-02 2008-04-15 Rambus Inc. Method and apparatus for evaluating and optimizing a signaling system
US6920402B1 (en) 2001-03-07 2005-07-19 Rambus Inc. Technique for determining performance characteristics of electronic devices and systems
US7542857B2 (en) 2001-03-07 2009-06-02 Rambus Inc. Technique for determining performance characteristics of electronic devices and systems
US8489345B2 (en) 2001-03-07 2013-07-16 Rambus Inc. Technique for determining performance characteristics of electronic devices and systems
US7006932B1 (en) 2001-03-07 2006-02-28 Rambus Inc. Technique for determining performance characteristics of electronic devices and systems
US9562934B2 (en) 2001-03-07 2017-02-07 Rambus Inc. Technique for determining performance characteristics of electronic devices and systems
US9977076B2 (en) 2001-03-07 2018-05-22 Rambus Inc. Technique for determining performance characteristics of electronic devices and systems
US8055458B2 (en) 2001-03-07 2011-11-08 Rambus Inc. Technique for determining performance characteristics of electronic devices and systems
JP2002312058A (en) * 2001-04-11 2002-10-25 Mitsubishi Electric Corp Semiconductor integrated circuit
US8462566B2 (en) 2001-04-24 2013-06-11 Rambus Inc. Memory module with termination component
US8717837B2 (en) 2001-04-24 2014-05-06 Rambus Inc. Memory module
US8214616B2 (en) 2001-04-24 2012-07-03 Rambus Inc. Memory controller device having timing offset capability
US10236051B2 (en) 2001-04-24 2019-03-19 Rambus Inc. Memory controller
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US8760944B2 (en) 2001-04-24 2014-06-24 Rambus Inc. Memory component that samples command/address signals in response to both edges of a clock signal
US9053778B2 (en) 2001-04-24 2015-06-09 Rambus Inc. Memory controller that enforces strobe-to-strobe timing offset
US8625371B2 (en) 2001-04-24 2014-01-07 Rambus Inc. Memory component with terminated and unterminated signaling inputs
US9741424B2 (en) 2001-04-24 2017-08-22 Rambus Inc. Memory controller
US9311976B2 (en) 2001-04-24 2016-04-12 Rambus Inc. Memory module
US8359445B2 (en) 2001-04-24 2013-01-22 Rambus Inc. Method and apparatus for signaling between devices of a memory system
US9472262B2 (en) 2001-04-24 2016-10-18 Rambus Inc. Memory controller
US6877054B2 (en) 2001-07-16 2005-04-05 Rambus Inc. Method and apparatus for position dependent data scheduling
US7136949B2 (en) 2001-07-16 2006-11-14 Rambus Inc. Method and apparatus for position dependent data scheduling
US7099424B1 (en) 2001-08-28 2006-08-29 Rambus Inc. Clock data recovery with selectable phase control
WO2003036313A1 (en) * 2001-10-25 2003-05-01 Advantest Corporation Clock/skew measurement apparatus and clock/skew measurement method
US6737852B2 (en) 2001-10-25 2004-05-18 Advantest Corporation Clock skew measuring apparatus and method
US7190754B1 (en) 2001-12-24 2007-03-13 Rambus Inc. Transceiver with selectable data rate
US6998892B1 (en) 2002-02-13 2006-02-14 Rambus Inc. Method and apparatus for accommodating delay variations among multiple signals
US7268602B2 (en) 2002-02-13 2007-09-11 Rambus Inc. Method and apparatus for accommodating delay variations among multiple signals
US7154302B2 (en) 2002-02-19 2006-12-26 Rambus Inc. Method and apparatus for selectably providing single-ended and differential signaling with controllable impedance and transition time
US7129739B2 (en) 2002-02-19 2006-10-31 Rambus Inc. Method and apparatus for selectably providing single-ended and differential signaling with controllable impedence and transition time
US6960948B2 (en) 2002-03-22 2005-11-01 Rambus Inc. System with phase jumping locked loop circuit
US7902890B2 (en) 2002-03-22 2011-03-08 Rambus Inc. Locked loop circuit with clock hold function
US8680903B2 (en) 2002-03-22 2014-03-25 Rambus Inc. Locked loop circuit with clock hold function
US6952123B2 (en) 2002-03-22 2005-10-04 Rambus Inc. System with dual rail regulated locked loop
US7535271B2 (en) 2002-03-22 2009-05-19 Rambus Inc. Locked loop circuit with clock hold function
US8120399B2 (en) 2002-03-22 2012-02-21 Rambus Inc. Locked loop circuit with clock hold function
US6911853B2 (en) 2002-03-22 2005-06-28 Rambus Inc. Locked loop with dual rail regulation
US6909387B2 (en) 2002-04-25 2005-06-21 Rambus Inc. Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy
US7231306B1 (en) 2002-04-30 2007-06-12 Rambus Inc. Method and apparatus for calibrating static timing offsets across multiple outputs
US9824740B2 (en) 2002-06-20 2017-11-21 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
US10593390B2 (en) 2002-06-20 2020-03-17 Rambus Inc. Dynamic memory supporting simultaneous refresh and data-access transactions
US7148699B1 (en) 2002-06-24 2006-12-12 Rambus Inc. Technique for calibrating electronic devices
US7095265B2 (en) 2002-07-19 2006-08-22 Rambus Inc. PVT-compensated clock distribution
US6897699B1 (en) * 2002-07-19 2005-05-24 Rambus Inc. Clock distribution network with process, supply-voltage, and temperature compensation
US7135903B2 (en) 2002-09-03 2006-11-14 Rambus Inc. Phase jumping locked loop circuit
US6922091B2 (en) 2002-09-03 2005-07-26 Rambus Inc. Locked loop circuit with clock hold function
US7089442B2 (en) 2003-02-07 2006-08-08 Rambus Inc. Fault-tolerant clock generator
US7467320B2 (en) 2003-02-07 2008-12-16 Rambus Inc. Fault-tolerant clock generator
US7298807B2 (en) 2003-02-11 2007-11-20 Rambus Inc. Circuit, apparatus and method for adjusting a duty-cycle of a clock signal in response to incoming serial data
US7765074B2 (en) 2003-02-11 2010-07-27 Rambus Inc. Circuit, apparatus and method for capturing a representation of a waveform from a clock-data recovery (CDR) unit
US7119549B2 (en) 2003-02-25 2006-10-10 Rambus Inc. Output calibrator with dynamic precision
US9917708B2 (en) 2003-04-09 2018-03-13 Rambus Inc. Partial response receiver
US10225111B2 (en) 2003-04-09 2019-03-05 Rambus Inc. Partial response receiver
US7397848B2 (en) 2003-04-09 2008-07-08 Rambus Inc. Partial response receiver
US9025678B2 (en) 2003-04-09 2015-05-05 Rambus Inc. Partial response receiver
US9407473B2 (en) 2003-04-09 2016-08-02 Rambus Inc. Partial response receiver
US7412016B2 (en) 2003-04-09 2008-08-12 Rambus Inc. Data-level clock recovery
US8428196B2 (en) 2003-04-09 2013-04-23 Rambus Inc. Equalizing receiver
US7715501B2 (en) 2003-04-09 2010-05-11 Rambus, Inc. Partial response receiver
US7275171B2 (en) 2003-05-22 2007-09-25 Rambus Inc. Method and apparatus for programmable sampling clock edge selection
US6998889B2 (en) 2003-08-11 2006-02-14 Rambus Inc. Circuit, apparatus and method for obtaining a lock state value
US7668271B2 (en) 2003-09-30 2010-02-23 Rambus Inc. Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data
US8130891B2 (en) 2003-09-30 2012-03-06 Rambus Inc. Clock-data recovery (“CDR”) circuit, apparatus and method for variable frequency data
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US9287909B2 (en) 2003-12-17 2016-03-15 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US8564328B2 (en) 2003-12-17 2013-10-22 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US10411923B2 (en) 2003-12-17 2019-09-10 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US7715471B2 (en) 2003-12-17 2010-05-11 Rambus, Inc. Signaling system with selectively-inhibited adaptive equalization
US9705710B2 (en) 2003-12-17 2017-07-11 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US7233164B2 (en) 2003-12-17 2007-06-19 Rambus Inc. Offset cancellation in a multi-level signaling system
US7199615B2 (en) 2003-12-17 2007-04-03 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation
US7423454B2 (en) 2003-12-17 2008-09-09 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US7176721B2 (en) 2003-12-17 2007-02-13 Rambus Inc. Signal receiver with data precessing function
US8994398B2 (en) 2003-12-17 2015-03-31 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US9000803B2 (en) 2003-12-17 2015-04-07 Rambus Inc. High speed signaling system with adaptive transmit pre-emphasis
US9628257B2 (en) 2004-01-28 2017-04-18 Rambus Inc. Communication channel calibration for drift conditions
US8149874B2 (en) 2004-01-28 2012-04-03 Rambus Inc. Adaptive-allocation of I/O bandwidth using a configurable interconnect topology
US8144792B2 (en) 2004-01-28 2012-03-27 Rambus Inc. Communication channel calibration for drift conditions
US8422568B2 (en) 2004-01-28 2013-04-16 Rambus Inc. Communication channel calibration for drift conditions
US10673582B2 (en) 2004-01-28 2020-06-02 Rambus Inc. Communication channel calibration for drift conditions
US7095789B2 (en) 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US10523344B2 (en) 2004-01-28 2019-12-31 Rambus Inc. Periodic calibration for communication channels by drift tracking
US7400671B2 (en) 2004-01-28 2008-07-15 Rambus Inc. Periodic calibration for communication channels by drift tracking
US7400670B2 (en) 2004-01-28 2008-07-15 Rambus, Inc. Periodic calibration for communication channels by drift tracking
US9042504B2 (en) 2004-01-28 2015-05-26 Rambus Inc. Communication channel calibration for drift conditions
US10305674B2 (en) 2004-01-28 2019-05-28 Rambus Inc. Communication channel calibration for drift conditions
US7415073B2 (en) 2004-01-28 2008-08-19 Rambus, Inc. Communication channel calibration for drift conditions
US10320496B2 (en) 2004-01-28 2019-06-11 Rambus Inc. Periodic calibration for communication channels by drift tracking
US8644419B2 (en) 2004-01-28 2014-02-04 Rambus Inc. Periodic calibration for communication channels by drift tracking
US9667359B2 (en) 2004-01-28 2017-05-30 Rambus Inc. Periodic calibration for communication channels by drift tracking
US8693556B2 (en) 2004-01-28 2014-04-08 Rambus Inc. Communication channel calibration for drift conditions
US8073009B2 (en) 2004-01-28 2011-12-06 Rambus Inc. Adaptive allocation of I/O bandwidth using a configurable interconnect topology
US8929424B2 (en) 2004-01-28 2015-01-06 Rambus Inc. Periodic calibration for communication channels by drift tracking
US9160466B2 (en) 2004-01-28 2015-10-13 Rambus Inc. Periodic calibration for communication channels by drift tracking
US9667406B2 (en) 2004-01-28 2017-05-30 Rambus Inc. Communication channel calibration for drift conditions
US7640448B2 (en) 2004-03-17 2009-12-29 Rambus, Inc. Drift tracking feedback for communication channels
US10503201B2 (en) 2004-03-17 2019-12-10 Rambus Inc. Drift tracking feedback for communication channels
US9710011B2 (en) 2004-03-17 2017-07-18 Rambus Inc. Drift tracking feedback for communication channels
US8504863B2 (en) 2004-03-17 2013-08-06 Rambus Inc. Drift tracking feedback for communication channels
US6961862B2 (en) 2004-03-17 2005-11-01 Rambus, Inc. Drift tracking feedback for communication channels
US7526664B2 (en) 2004-03-17 2009-04-28 Rambus, Inc. Drift tracking feedback for communication channels
US7159136B2 (en) 2004-03-17 2007-01-02 Rambus, Inc. Drift tracking feedback for communication channels
US7138877B2 (en) 2004-04-21 2006-11-21 Rambus Inc. PLL and method for providing a single/multiple adjustable frequency range
US8488686B2 (en) 2004-05-28 2013-07-16 Rambus Inc. Communication channel calibration with nonvolatile parameter store for recovery
US7978754B2 (en) 2004-05-28 2011-07-12 Rambus Inc. Communication channel calibration with nonvolatile parameter store for recovery
US10439740B2 (en) 2004-06-09 2019-10-08 Rambus Inc. Communication channel calibration using feedback
US9735898B2 (en) 2004-06-09 2017-08-15 Rambus Inc. Communication channel calibration using feedback
US8121803B2 (en) 2004-06-09 2012-02-21 Rambus, Inc. Communication channel calibration using feedback
US7516029B2 (en) 2004-06-09 2009-04-07 Rambus, Inc. Communication channel calibration using feedback
US9172521B2 (en) 2004-06-09 2015-10-27 Rambus Inc. Communication channel calibration using feedback
US7268605B2 (en) 2004-06-14 2007-09-11 Rambus, Inc. Technique for operating a delay circuit
US9830971B2 (en) 2004-09-15 2017-11-28 Rambus Inc. Memory controller with clock-to-strobe skew compensation
US8493802B1 (en) 2004-09-15 2013-07-23 Rambus Inc. Memory controller having a write-timing calibration mode
US9229470B2 (en) 2004-09-15 2016-01-05 Rambus Inc. Memory controller with clock-to-strobe skew compensation
US10325645B2 (en) 2004-09-15 2019-06-18 Rambus Inc. Memory controller with clock-to-strobe skew compensation
US7724590B2 (en) 2004-09-15 2010-05-25 Rambus Inc. Memory controller with multiple delayed timing signals
US8743636B2 (en) 2004-09-15 2014-06-03 Rambus Inc. Memory module having a write-timing calibration mode
US8045407B2 (en) 2004-09-15 2011-10-25 Rambus Inc. Memory-write timing calibration including generation of multiple delayed timing signals
US8218382B2 (en) 2004-09-15 2012-07-10 Rambus Inc. Memory component having a write-timing calibration mode
US9437279B2 (en) 2004-09-15 2016-09-06 Rambus Inc. Memory controller with clock-to-strobe skew compensation
US8363493B2 (en) 2004-09-15 2013-01-29 Rambus Inc. Memory controller having a write-timing calibration mode
US7489739B2 (en) 2004-09-17 2009-02-10 Rambus, Inc. Method and apparatus for data recovery
US8233567B2 (en) 2004-09-17 2012-07-31 Rambus Inc. Method and apparatus for data recovery
US7403044B2 (en) * 2005-04-26 2008-07-22 Micron Technology, Inc. Method of producing balanced data output
US7917875B1 (en) 2005-08-04 2011-03-29 Freescale Semiconductor, Inc. Clock tree adjustable buffer
US7571406B2 (en) 2005-08-04 2009-08-04 Freescale Semiconductor, Inc. Clock tree adjustable buffer
US7437584B2 (en) 2006-02-27 2008-10-14 Atmel Corporation Apparatus and method for reducing power consumption in electronic devices
US7376042B2 (en) * 2006-07-25 2008-05-20 Qimonda Ag Boosted clock circuit for semiconductor memory
US8063509B2 (en) * 2007-03-20 2011-11-22 Fujitsu Limited Power supply voltage adjusting apparatus, recording medium, and power supply voltage adjusting method
US8264906B2 (en) 2007-05-29 2012-09-11 Rambus Inc. Adjusting clock error across a circuit interface
US8582391B2 (en) 2007-05-29 2013-11-12 Rambus Inc. Adjusting clock error across a circuit interface
US9577816B2 (en) 2012-03-13 2017-02-21 Rambus Inc. Clock and data recovery having shared clock generator
US10263761B2 (en) 2012-03-13 2019-04-16 Rambus Inc. Clock and data recovery having shared clock generator
US9768947B2 (en) 2012-03-13 2017-09-19 Rambus Inc. Clock and data recovery having shared clock generator
US10050771B2 (en) 2012-03-13 2018-08-14 Rambus Inc. Clock and data recovery having shared clock generator
US9906335B2 (en) 2012-05-02 2018-02-27 Rambus Inc. Receiver clock test circuitry and related methods and apparatuses
US9294262B2 (en) 2012-05-02 2016-03-22 Rambus Inc. Receiver clock test circuitry and related methods and apparatuses
US9071407B2 (en) 2012-05-02 2015-06-30 Ramnus Inc. Receiver clock test circuitry and related methods and apparatuses
US10320534B2 (en) 2012-05-02 2019-06-11 Rambus Inc. Receiver clock test circuitry and related methods and apparatuses
US9537617B2 (en) 2012-05-02 2017-01-03 Rambus Inc. Receiver clock test circuitry and related methods and apparatuses
US10706910B2 (en) 2019-02-25 2020-07-07 Rambus Inc. Memory controller

Similar Documents

Publication Publication Date Title
US20160161971A1 (en) Small-circuit-scale reference voltage generating circuit
US6954101B2 (en) Potential detector and semiconductor integrated circuit
US6351179B1 (en) Semiconductor integrated circuit having active mode and standby mode converters
US7414453B2 (en) Level conversion circuit
US6429723B1 (en) Integrated circuit with charge pump and method
US7161408B2 (en) Semiconductor integrated circuit device and microcomputer
US4214174A (en) Voltage multiplier employing clock gated transistor chain
KR100888806B1 (en) Semiconductor integrated circuit device
JP6169892B2 (en) Semiconductor integrated circuit and operation method thereof
DE19946154C2 (en) Voltage-controlled low-voltage oscillator with a small fluctuation range
US6466077B1 (en) Semiconductor integrated circuit device including a speed monitor circuit and a substrate bias controller responsive to the speed-monitor circuit
US6700363B2 (en) Reference voltage generator
US6020778A (en) Transmission gate including body effect compensation circuit
DE69633539T2 (en) Clock distribution circuit
US7190211B2 (en) Semiconductor device equipped with a voltage step-up circuit
US6603346B2 (en) Semiconductor booster circuit having cascaded MOS transistors
JP3278765B2 (en) Negative voltage generation circuit
US5936455A (en) MOS integrated circuit with low power consumption
US7592832B2 (en) Adjustable transistor body bias circuitry
US6525587B2 (en) Semiconductor integrated circuit device including a clock synchronous type logical processing circuit
JP4133371B2 (en) Level conversion circuit
US6278294B1 (en) Output buffer circuit
US9030176B2 (en) Semiconductor integrated circuit
US7560975B2 (en) Semiconductor device
US6556071B2 (en) Semiconductor integrated circuit