JP2000035831A - Low skew clock tree circuit using variable threshold voltage transistor - Google Patents

Low skew clock tree circuit using variable threshold voltage transistor

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Publication number
JP2000035831A
JP2000035831A JP20530998A JP20530998A JP2000035831A JP 2000035831 A JP2000035831 A JP 2000035831A JP 20530998 A JP20530998 A JP 20530998A JP 20530998 A JP20530998 A JP 20530998A JP 2000035831 A JP2000035831 A JP 2000035831A
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clock
circuit
element
skew
threshold voltage
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JP20530998A
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Japanese (ja)
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Masaharu Mizuno
雅春 水野
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Nec Corp
日本電気株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a clock tree circuit capable of controlling clock skew of a clock tree circuit, reduced in power consumption and low in clock skew. SOLUTION: This clock tree circuit uses a transistor having a threshold voltage variable well structure for a clock element. Here, it has phase comparator circuits 31 to 33 which perform comparison observation of skew values among respective elements 21 to 24 and output differential voltage and charge pump circuits 41 to 43 which make the differential voltage of the circuits 31 to 33 inputs and supply them as well potential to each well terminal of the elements 21 to 24, controls the switching speed of a clock tree circuit by adjusting the threshold voltage of each element 21 to 24 and reduces clock skew.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】クロックを分配するクロックツリー回路に関し、特に可変閾値電圧トランジスタを用いたクロックツリー回路の素子間のクロックスキューに関する。 Relates clock tree circuit for distributing a clock BACKGROUND OF THE INVENTION, in particular to clock skew between the elements of the clock tree circuit using a variable threshold voltage transistor.

【0002】 [0002]

【従来の技術】LSIの高集積化と共に回路規模の増大と、動作速度の高速化が行われている。 And increase in the circuit scale with higher integration of the Related Art LSI, the operating speed is being performed. 従来、クロックを分配するクロックツリー回路の各クロック素子のウエル電位は、図7に示すように共通であり、製造条件等に依存してクロックツリー回路のチップ内各クロック素子のスイッチングスピードがばらついた場合、クロックツリー回路のクロックスキューが大きくなる欠点を持っていた。 Conventionally, the well potentials of the clock component of the clock tree circuit for distributing the clock is common, as shown in FIG. 7, the switching speed of the chip in each clock elements of the clock tree circuit, depending on the manufacturing conditions are varied case, had a clock skew is greater disadvantage of the clock tree circuit.

【0003】 [0003]

【発明が解決しようとする課題】各クロック素子のスイッチングスピードが個別に制御ができず、各クロック素子間のスイッチングスピードが製造条件等に依存してチップ内でばらついた場合、各クロック素子のウエル電位が共通であり、各クロック素子の閾値電圧、すなわち、 Switching speed of the Invention Problems to be Solved by the clock element can not be individually controlled, when the switching speed between the clock element varies in dependent on the manufacturing conditions such as a chip, the well of each clock element potential is common, the threshold voltage of each clock element, i.e.,
スイッチングスピードを個別に制御することが不可能であるので、クロックスキューが大きくなる欠点を持っている。 Since the switching speed is impossible to control individually, it has the disadvantage that the clock skew becomes large.

【0004】上記の欠点を解決する半導体装置として特開平9−92723号公報が開示されている。 [0004] JP-A 9-92723 Patent Publication discloses a semiconductor device for solving the above-mentioned drawbacks. 開示された半導体装置は、内部クロック間のスキュー観測回路と、クロック間で相対的に位相の進んだクロックの負荷を増加させる負荷増減回路を有し、ばらつき観測回路の観測値のクロック源の値に近いものから順次検出状態を固定し、負荷増減回路による内部クロックの負荷を固定する順序維持回路を有するものである。 The disclosed semiconductor device includes a skew monitoring circuit between the internal clock has a load increase or decrease circuit for increasing the load of the clock advanced relatively phase between the clock, the clock source of the value of the observed value of the variation monitoring circuit sequentially detected state is fixed from close to, those having the sequence maintaining circuit for fixing a load on the internal clock by the load increase or decrease circuit.

【0005】しかし、特開平9−92723号公報に開示されている半導体装置は、従来のクロックツリー回路に比較し、付加される回路群が多く、消費電力の点で問題を有する。 However, the semiconductor device disclosed in JP-A-9-92723 is compared with the conventional clock tree circuit, it added the circuit many group has a problem in terms of power consumption.

【0006】本発明の目的は、 クロックツリー回路のクロックスキューを制御して、消費電力の少なく、クロックスキューの低いクロックツリー回路を提供することである。 An object of the present invention controls the clock skew of the clock tree circuit, less power consumption, is to provide a low clock tree circuit of skew.

【0007】 [0007]

【課題を解決するための手段】本発明の可変閾値電圧トランジスタを用いた低スキュークロックツリー回路は、 Low skew clock tree circuit using a variable threshold voltage transistor SUMMARY OF THE INVENTION The present invention,
クロック素子に閾値電圧可変なウエル構造を持つトランジスタを用いるクロックツリー回路であって、各クロック素子間のスキュー値を比較観測する比較観測手段と、比較観測結果から各クロック素子のウエル電位を制御する制御手段を有し、ウエル電位を制御し閾値電圧を調整することで、クロックツリー回路のスイッチングスピードを制御し、クロックスキューを低減することを特徴とする。 A clock tree circuit using a transistor having a threshold voltage variable well structure with a clock device for controlling the comparing observation means for comparing the observed skew value, the well potential of each clock element from the comparison observations between the clock element a controlling unit, by adjusting the threshold voltage by controlling the well potential, and controls the switching speed of the clock tree circuit, and wherein the reducing the clock skew. また、各クロック素子間のスキュー値を比較観測する比較観測手段は、クロック素子間の位相を比較し、差電圧を出力する位相比較回路であって良い。 The comparison observation means for comparing the observed skew values ​​between the clock element compares the phase between the clock element may be a phase comparison circuit for outputting a difference voltage.

【0008】また、比較観測結果から各クロック素子のウエル電位を制御する制御手段は、位相比較回路の差電圧を入力としクロック素子のP型MOSトランジスタのNウエル端子にウエル電位として供給するチャージポンプ回路と、位相比較回路の差電圧を入力としクロック素子のN型MOSトランジスタのPウエル端子にウエル電位として供給するチャージポンプ回路であって良い。 Further, control means for controlling the well potential of each clock element from the comparison observations, the charge pump supplies the N-well terminal of the P-type MOS transistor of the clock device as input differential voltage of the phase comparator as well potential and the circuit may be a charge pump circuit for supplying to the P-well terminal of the N-type MOS transistor of the clock device as input differential voltage of the phase comparator as well potential.

【0009】本発明の可変閾値電圧トランジスタを用いた低スキュークロックツリー回路は、閾値電圧可変なウエル構造を持つトランジスタで構成されたクロックツリー回路と、各クロック素子間のクロックスキュー値を比較観測するクロックスキュー比較観測回路と、前記クロックスキュー比較観測回路の測定結果から各クロック素子のウエル電位を個別に制御するウエル電位制御回路とで構成された半導体集積回路で、各クロック素子間のクロックスキュー値を比較観測し、その測定結果から各クロック素子のウエル電位をウエル電位制御回路で個別に制御し閾値電圧を調整することで、各クロック素子のスイッチングスピードを制御し、他クロック素子とのクロックスキューを低減させる。 [0009] low-skew clock tree circuit using a variable threshold voltage transistor of the present invention includes a clock tree circuit constituted by transistors having a threshold voltage variable well structure, comparing observed clock skew between the clock element a skew comparison monitoring circuit, a semiconductor integrated circuit constituted by the well potential control circuit for individually controlling the measurement results well potential of the clock element of the skew comparator monitoring circuit, the clock skew between the clock element the comparison was observed, by adjusting the individually controlled by the threshold voltage in the well potential control circuit well potential of each clock element from the measurement result, to control the switching speed of each clock elements, skew of the other clock element It is reduced.

【0010】 [0010]

【発明の実施の形態】次に、本発明の実施の形態について図面を参照して説明する。 BEST MODE FOR CARRYING OUT THE INVENTION Next, a description with reference to the drawings, embodiments of the present invention.

【0011】図1は本発明の原理を示す機能ブロック図で、閾値電圧可変なウエル構造を持つトランジスタで構成されたクロックツリー回路1と、各クロック素子間のクロックスキュー値を比較し、電圧に変換するクロックスキュー比較観測回路2と、クロックスキュー比較観測回路2の測定結果から各クロック素子のウエル電位を個別に制御するウエル電位制御回路3とで構成される。 [0011] Figure 1 is a functional block diagram illustrating the principles of the present invention, a clock tree circuit 1 composed of a transistor having a threshold voltage variable well structure, it compares the clock skew between the clock element into a voltage composed of the skew comparator monitoring circuit 2 for converting a well potential control circuit 3 for controlling individually the well potential of each clock element from the measurement result of skew comparison monitoring circuit 2.

【0012】図2は図1の閾値電圧可変なウエル構造を持つトランジスタで構成されたクロックツリー回路1の構成を表す論理回路図である。 [0012] FIG. 2 is a logic circuit diagram showing a configuration of a clock tree circuit 1 composed of a transistor having a threshold voltage variable well structure of FIG. 図2において、クロック供給元25はクロック素子21、22、23、24にクロックを分配している。 2, the clock source 25 is distributed to clock the clock device 21, 22, 23, 24. クロック素子21は、図に示すように、更に4個のクロック素子にクロックを分配している。 Clock element 21, as shown, is further distribute clocks to four clock element. ここでは4個のクロック素子にクロックを分配しているが、その数に制限されるものではない。 Here, although to distribute clocks to four clock element, but is not limited to that number.

【0013】図3は図2の各クロック素子のトランジスタレベルの回路図である。 [0013] FIG. 3 is a circuit diagram of a transistor level of the clock element of FIG. 本発明のクロックツリーに使われるクロック素子のウエル電位は、 P型MOSトランジスタのNウエル端子CTR*Aと、 N型MOSトランジスタのPウエル端子CTR*Bとに分離されており、そのウエル電位は個別に制御できるものである。 Well potential of the clock devices used in the clock tree of the present invention is separated and N-well terminal CTR * A P-type MOS transistor, to the P-well terminal CTR * B of N-type MOS transistor, the well potential is in which can be individually controlled. 次に、本発明の実施例を図を参照して説明する。 Next, a description will be given of an embodiment of the present invention with reference to FIG. 図4は本発明の第1の実施例の回路構成を示すブロック図、図5 Figure 4 is a block diagram showing a circuit configuration of a first embodiment of the present invention, FIG. 5
は本発明の第2の実施例の回路構成を示すブロック図、 Block diagram showing a circuit configuration of a second embodiment of the present invention,
図6は本発明の第3の実施例の回路構成を示すブロック図である。 6 is a block diagram showing a circuit configuration of a third embodiment of the present invention.

【0014】図4は比較対象となるクロック素子の内のクロック素子24をベースにして残りの各クロック素子21、22、23との素子間の位相を比較し、差電圧を出力する位相比較回路31、32、33と、位相比較回路の差電圧を入力としクロック素子のP型MOSトランジスタのNウエル端子にウエル電位として供給するチャージポンプ回路41、42、43とにより構成されている。 [0014] Figure 4 compares the phase between elements with the rest of the clock device 21, 22, 23 in the base clock element 24 of the clock element to be compared, the phase comparator circuit for outputting a difference voltage and 31, 32, 33 is constituted by a charge pump circuit 41, 42 and 43 supplied to the N-well terminal of the P-type MOS transistor of the clock device as input differential voltage of the phase comparator as well potential.

【0015】また、図5は比較対象となるクロック素子の内のクロック素子24をベースにして残りの各クロック素子21、22、23との素子間の位相を比較し、差電圧を出力する位相比較回路31、32、33と、位相比較回路の差電圧を入力としクロック素子のN型MOS [0015] Figure 5 compares the phase between elements with the rest of the clock device 21, 22, 23 in the base clock element 24 of the clock element to be compared, and outputs a difference voltage phase a comparator circuit 31, 32, 33, N-type MOS clock element as input differential voltage of the phase comparator
トランジスタのPウエル端子にウエル電位として供給するチャージポンプ回路41、42、43とにより構成されている。 It is constituted by a charge pump circuit 41, 42 and 43 supplied to the P-well terminal of the transistor as well potential.

【0016】更にまた、図6は比較対象となるクロック素子の内クロック素子24をベースにして残りの各クロック素子21、22、23との素子間の位相を比較し、 [0016] Furthermore, Figure 6 compares the phase between elements with each clock elements 21, 22, 23 remaining in the base clock internal clock element 24 of the element to be compared,
差電圧を出力する位相比較回路31〜36と、位相比較回路31、33、35の差電圧を入力としクロック素子21、22、23のP型MOSトランジスタのNウエル端子にウエル電位として供給するチャージポンプ回路4 A phase comparison circuit 31 to 36 for outputting a difference voltage, the charge supplied to the N-well terminal of the P-type MOS transistor of the clock device 21, 22, 23 as input differential voltage of the phase comparator 31, 33 and 35 as well potential pump circuit 4
1、43、45と、位相比較回路32、34、36の差電圧を入力としクロック素子21、22、23のN型M And 1,43,45, N-type M of clock elements 21, 22, 23 as input difference voltage of the phase comparator circuit 32, 34, 36
OSトランジスタのPウエル端子にウエル電位として供給するチャージポンプ回路42、44、46により構成されている。 It is constituted by a charge pump circuit 42, 44 and 46 supplied as well potential to the P-well terminal of the OS transistor.

【0017】上記で説明した構成を持つクロックツリー回路1は、図1に戻り、各クロック素子間のクロックスキュー値を位相比較回路に相当するクロックスキュー比較観測回路2で観測し、その測定結果から各クロック素子のウエル電位をチャージポンプ回路に相当するウエル電位制御回路3で個別に制御し閾値電圧の調整を行うことで各クロック素子のスイッチングスピードを制御し、 The clock tree circuit 1 having the configuration described above, the process returns to FIG. 1, the clock skew between the clock element observed by skew comparison monitoring circuit 2 corresponding to the phase comparator circuit, from the measurement result It controls the switching speed of each clock element by adjusting the individually controlled threshold voltage in the well potential control circuit 3 which corresponds to the well potentials of the clock element to the charge pump circuit,
他のクロック素子とのクロックスキューを低減させる。 Reducing the clock skew of the other clock element.

【0018】 [0018]

【発明の効果】本発明によれば、閾値電圧可変なウエル構造を持つトランジスタで構成したクロックツリー回路は、各クロック素子間のクロックスキュー値を比較観測し、その測定結果から各クロック素子のウエル電位を個別に制御し閾値電圧を調整することで、各クロック素子のスイッチングスピードを制御し、他クロック素子とのクロックスキューを低減させることができる効果がある。 According to the present invention, the clock tree circuit configured with transistors having a threshold voltage variable well structure compares observed clock skew between the clock element, the wells of each clock element from the measurement result by adjusting the individually controlled threshold voltage potential, by controlling the switching speed of each clock elements, there is an effect that it is possible to reduce the clock skew between the other clock device.

【0019】また、本発明によれば、閾値電圧可変なウエル構造を持つトランジスタで構成したクロックツリー回路は、直接クロックスキューを測定し、制御するため、製造条件の変動等にも依存しない、低スキューなクロックツリー回路を実現することができる効果がある。 Further, according to the present invention, the clock tree circuit configured with transistors having a threshold voltage variable well structure directly measures the clock skew, for controlling, not dependent on variations in manufacturing conditions, low there is an effect capable of providing a skew clock tree circuit.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の一実施例を示す機能ブロック図である。 1 is a functional block diagram showing an embodiment of the present invention.

【図2】図1の閾値電圧可変なウエル構造を持つトランジスタで構成されたクロックツリー回路1の構成を表す論理回路図である。 2 is a logic circuit diagram showing a configuration of a clock tree circuit 1 composed of a transistor having a threshold voltage variable well structure of FIG.

【図3】図2の各クロック素子のトランジスタレベルの回路図である。 3 is a circuit diagram of a transistor level of the clock element of FIG.

【図4】本発明の第1の実施例の回路構成を示すブロック図である。 Is a block diagram showing a circuit configuration of a first embodiment of the present invention; FIG.

【図5】本発明の第2の実施例の回路構成を示すブロック図である。 5 is a block diagram showing a circuit configuration of a second embodiment of the present invention.

【図6】本発明の第3の実施例の回路構成を示すブロック図である。 6 is a block diagram showing a circuit configuration of a third embodiment of the present invention.

【図7】従来の一実施例を示す機能ブロック図である。 7 is a functional block diagram showing an embodiment of a prior art.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 VT−CMOSを用いたクロックツリー回路 2 クロックスキュー比較観測回路 3 ウエル電位制御回路 21、22、23、24 クロック素子 25 クロック供給元クロック素子 31、32、33、34、35、36 位相比較回路 41、42、43、44、45、46 チャージポンプ回路 Clock tree circuit 2 skew comparator monitoring circuit 3 well-potential control circuit 21, 22, 23, 24 clock element 25 clock supply source clock elements 31,32,33,34,35,36 phase comparison circuit using the 1 VT-CMOS 41 to 46 charge pump circuit

Claims (6)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 クロック素子に閾値電圧可変なウエル構造を持つトランジスタを用い、クロックツリーによってクロックを分配するクロックツリー回路において、 各クロック素子間のスキュー値を比較観測する比較観測手段と、 前記比較観測結果から各クロック素子のウエル電位を制御する制御手段を有し、 前記制御手段によりウエル電位を制御し閾値電圧を調整することで、クロックツリー回路のスイッチングスピードを制御し、クロックスキューを低減することを特徴とする可変閾値電圧トランジスタを用いた低スキュークロックツリー回路。 [Claim 1] with a transistor having a threshold voltage variable well structure with a clock device, the clock tree circuit for distributing a clock by the clock tree, and comparing the observed means for comparing the observed skew values ​​between the clock element, the comparison a control means for controlling the well potential of each clock element from observation, by adjusting the threshold voltage by controlling the well potential by the control means to control the switching speed of the clock tree circuit, to reduce the clock skew low skew clock tree circuit using a variable threshold voltage transistor, characterized in that.
  2. 【請求項2】 前記各クロック素子間のスキュー値を比較観測する比較観測手段が、 クロック素子間の位相を比較し、差電圧を出力する位相比較回路である請求項1記載の可変閾値電圧トランジスタを用いた低スキュークロックツリー回路。 2. A comparison observation means for said comparing observed skew values ​​between the clock element, compares the phase between the clock element, the variable threshold voltage transistor according to claim 1, wherein a phase comparison circuit for outputting a difference voltage low-skew clock tree circuit that was used.
  3. 【請求項3】 前記各クロック素子間のスキュー値を比較観測する比較観測手段が、 比較対象となるクロック素子の内の任意のクロック素子をベースにして残りの各クロック素子との素子間の位相を比較し、差電圧を出力することを特徴とする請求項1 3. A phase between the comparative observation means for comparing the observed skew values ​​between the clock element, the element with the rest of the clock device by an arbitrary clock element to the base of the clock element to be compared compare, and outputs the difference voltage according to claim 1
    または2記載の可変閾値電圧トランジスタを用いた低スキュークロックツリー回路。 Or low skew clock tree circuit using a variable threshold voltage transistor 2, wherein.
  4. 【請求項4】 前記比較観測結果から各クロック素子のウエル電位を制御する制御手段が、 前記位相比較回路の差電圧を入力としクロック素子のP 4. A control means for controlling the well potential of each clock element from the comparison observation result, P clock device and a difference voltage between the input of the phase comparator circuit
    型MOSトランジスタのNウエル端子にウエル電位として供給するチャージポンプ回路である請求項1乃至3の何れかに記載の可変閾値電圧トランジスタを用いた低スキュークロックツリー回路。 Type MOS transistors low skew clock tree circuit using a variable threshold voltage transistor according to any one of claims 1 to 3 in the N-well terminal is a charge pump circuit for supplying a well potential of.
  5. 【請求項5】 前記比較観測結果から各クロック素子のウエル電位を制御する制御手段が、 前記位相比較回路の差電圧を入力としクロック素子のN 5. A control means for controlling the well potential of each clock element from the comparison observation result, N of the difference voltage between the input clock elements of said phase comparator circuit
    型MOSトランジスタのPウエル端子にウエル電位として供給するチャージポンプ回路である請求項1、乃至3 Claims P-well terminal type MOS transistor is a charge pump circuit for supplying a well potential 1, or 3
    の何れかに記載の可変閾値電圧トランジスタを用いた低スキュークロックツリー回路。 Low skew clock tree circuit using a variable threshold voltage transistor according to any one of.
  6. 【請求項6】 前記比較観測結果から各クロック素子のウエル電位を制御する制御手段が、 前記位相比較回路の差電圧を入力としクロック素子のP 6. A control unit for controlling the well potential of each clock element from the comparison observation result, P clock device and a difference voltage between the input of the phase comparator circuit
    型MOSトランジスタのNウエル端子にウエル電位として供給するチャージポンプ回路と、 前記位相比較回路の差電圧を入力としクロック素子のN Type MOS charge pump circuit for supplying the N-well terminal as well potential of the transistor, N clock device and a difference voltage between the input of the phase comparator circuit
    型MOSトランジスタのPウエル端子にウエル電位として供給するチャージポンプ回路を有する請求項1乃至3 Claims 1 to 3 having a charge pump circuit for supplying to the P-well terminal type MOS transistor as well potential
    の何れかに記載の可変閾値電圧トランジスタを用いた低スキュークロックツリー回路。 Low skew clock tree circuit using a variable threshold voltage transistor according to any one of.
JP20530998A 1998-07-21 1998-07-21 Low skew clock tree circuit using variable threshold voltage transistor Pending JP2000035831A (en)

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