JPH1197949A - Variable current source, and source voltage compensation type integral delay circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily obtain the current which is proportional to variation in source voltage. SOLUTION: A current mirror circuit 1 is constituted by connecting the gates of a 1st transistor(TR) 2 connected to a source voltage Vdd through a 1st resistance 4 and a 2nd TR 3 connected to the source voltage Vdd through a 2nd resistance 5 having the same resistance value with the 1st resistance 4, and a 3rd TR 10 which controls a current flowing to the 1st TR 2 according to the output of a differential amplifier 9 inputting a voltage stepped down by a 3rd resistance 7 of a resistance voltage dividing circuit 6 dividing the source voltage Vdd and a voltage stepped down by the 1st resistance 4 is provided at the part of the leg of the current mirror circuit 1. Consequently, the 3rd TR 10 is able to operate like a constant-current source and a current which is proportional to variation in the source voltage Vdd can securely be taken out by the current mirror.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable current source and a power supply voltage compensation type integration delay circuit using the same.
The present invention relates to a technique for obtaining a current proportional to a power supply voltage.

[0002]

2. Description of the Related Art In recent years, a semiconductor integrated circuit (LSI) such as a microprocessor or a semiconductor memory has been required to operate at a high frequency in order to increase processing speed. Accordingly, synchronization between each LSI chip or each LSI
The frequency of a clock for synchronizing circuits in a chip has been increasing.

[0005] As the operating frequency is extremely high, it is sometimes required to generate a clock having a fixed delay amount with respect to the input clock. For example,
For very high-speed DRAM interfaces, when the microprocessor receives information from the DRAM via the bus, the timing to read from the DRAM is set to be a fixed time shorter than the timing of the input clock so that the microprocessor can receive the information at the right timing. There is a demand to delay.

Conventionally, for example, an integration delay circuit has been used to delay an input clock. As shown in FIG. 3, the integration delay circuit 30 includes a constant current source 31,
It is composed of a capacitor 32 and an inverter 33. According to the integration delay circuit 30, the current from the constant current source 31 is gradually accumulated as an integrated voltage in the capacitor 32 by the integration operation, and the input to the inverter 33 is gradually increased. Thereafter, by outputting a clock when the integrated voltage exceeds the logical threshold value of the inverter 33, it is possible to delay the clock by the time from the start of integration until the threshold value is reached.

[0005]

In this case, it is required that the amount of delay of the clock is always constant regardless of disturbance or the like. However, the CMO constituting the inverter 33
Since the logical threshold value of the S gate is generally set to about 1/2 of the power supply voltage, the logical threshold value of the inverter 33 changes in proportion to the power supply voltage, and accordingly, the amount of delay also changes. For example, as the power supply voltage Vdd increases, the delay time increases.

As shown in FIG. 4, when a P-type MOS transistor 41 is used instead of the constant current source 31 shown in FIG. 3, the current flowing through the transistor 41 becomes equal to the power supply voltage Vdd.
A change larger than the change occurs. for that reason,
For example, when the power supply voltage Vdd increases, the delay time becomes short.

Although the use of the resistor 51 as shown in FIG. 5 eliminates the influence of the power supply voltage Vdd, this circuit configuration has no function for switching and cannot be used practically. In order to make it practically usable, it is necessary to further provide a switching transistor.
This transistor is affected by the power supply voltage Vdd.

Therefore, when an integration delay circuit that does not depend on the power supply voltage Vdd is to be made, a mechanism for self-correction for fluctuations in the power supply voltage Vdd is provided.
It is necessary to change the charging current for the capacitor 32 in proportion to the power supply voltage Vdd. If the charging current to the capacitor 32 is changed in proportion to the power supply voltage Vdd, even if the logic threshold value of the inverter 33 changes due to the fluctuation of the power supply voltage Vdd, the integration speed changes accordingly.
A certain amount of delay can be maintained.

As shown in FIG. 6, a circuit for obtaining a current proportional to the power supply voltage Vdd has two MOs.
It is easily imagined that a resistor 61 is provided at the leg of a current mirror circuit in which the gates of the S transistors 62 and 63 are connected to each other. That is, since the current flowing through the resistor 61 is considered to be proportional to the power supply voltage Vdd, it can be imagined that a current proportional to the power supply voltage Vdd can be obtained by extracting the current with the current mirror.

However, actually, in this circuit, the voltage at the point P is not a mirror potential determined by the current flowing through the resistor 61, and the potential obtained by dividing the power supply voltage Vdd by the resistor 61 and the P-type MOS transistor 62. Will be. Therefore, the current mirror does not operate well and the power supply voltage V
There is a problem that a current proportional to dd cannot be obtained.

The present invention has been made in order to solve such a problem, and a first object of the present invention is to provide a circuit capable of easily obtaining a current proportional to a fluctuation of a power supply voltage. I do. It is a second object of the present invention to provide an integration delay circuit capable of always maintaining a constant delay amount with respect to an input clock irrespective of fluctuations in a power supply voltage.

[0012]

The variable current source according to the present invention comprises:
A first power supply line connected to the first power supply line via the first resistor;
And a current mirror circuit formed by connecting the gates of a second transistor connected to the first power supply line via a second resistor having the same resistance value as the first resistor. A third resistor connected to the first power line, and a fourth resistor connected in series to the third resistor, between the first power line and the second power line. A resistor voltage dividing circuit for dividing the supplied power supply voltage, and a voltage stepped down by the first resistor is applied to one input terminal and stepped down by the third resistor of the resistor voltage dividing circuit. A differential amplifier configured to apply a voltage to the other input terminal; and a third transistor that controls a current flowing through the first transistor according to an output of the differential amplifier. Features.

Here, the first transistor and the second transistor may be constituted by P-type MOS transistors, and the third transistor may be constituted by N-type MOS transistors.

Further, a power supply voltage compensation type integration delay circuit according to the present invention is provided with the variable current source according to the first aspect. For example, the variable current source according to claim 1, a switch that is turned on / off in response to an input clock, and a capacitor that accumulates an integrated voltage according to a current supplied from the variable current source when the switch is turned on. And an inverter circuit connected in parallel to the capacitor.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing one embodiment of the variable current source according to the present invention. Hereinafter, the variable current source according to the present embodiment will be described with reference to FIG.

In FIG. 1, reference numeral 1 denotes a current mirror circuit, and the gates of a first transistor 2 formed by a P-type MOS circuit and a second transistor 3 formed by a P-type MOS circuit are also connected. Are connected. Further, the gate and the drain of the first transistor 2 are also connected.

The first transistor 2 is connected to a power supply voltage Vdd line via a first resistor 4, and the second transistor 3 has a second resistance having the same resistance value as the first resistor 4. It is connected to the line of the power supply voltage Vdd via the resistor 5. The same resistance value is used for the power supply voltage Vdd.
This is to make the voltage drop to the same.

Reference numeral 6 denotes a resistance voltage dividing circuit, which is a power supply voltage Vdd.
, And a fourth resistor 8 connected in series with the third resistor 7. This resistance voltage dividing circuit 6 divides the power supply voltage Vdd supplied between the power supply voltage line and the ground power supply line.
Note that the resistance values of the third resistor 7 and the fourth resistor 8 do not necessarily have to be the same, but are preferably the same.
These resistance values are the first and second resistances 4, 5
Use a resistance value larger than the resistance value.

Reference numeral 9 denotes a differential amplifier, to which a stepped-down voltage of the power supply voltage Vdd is applied to one input terminal by the first resistor 4, and the power supply voltage is supplied by the third resistor 7 of the resistor voltage dividing circuit 6. The reduced voltage of Vdd is applied to the other input terminal. This differential amplifier 9 operates so that the voltages at points A and B become equal. Reference numeral 10 denotes a third transistor formed of an N-type MOS circuit,
Controls the current flowing through the first transistor 2 according to the output of the first transistor 2.

As shown in FIG. 1, in this embodiment, the first and second resistors 4 and 5 for detecting a current are connected to the side of the current mirror circuit 1 where the gates of the current mirror circuit 1 are connected to each other (the leg of the current mirror). The third transistor 10 is connected to the other side of the third transistor 10 as a circuit for controlling the current flowing through the first transistor 2.
Are connected. Then, a current flowing through the first transistor 2 is taken out by a current mirror.

With this configuration, the third transistor 10 can function as a constant current source, unlike the case of the example of FIG. 6 in which a resistor is provided at the leg of the current mirror. That is, when the gate voltage input to the third transistor 10 from the differential amplifier 9 is small and the third transistor 10 is in the saturation region,
The drain current of the third transistor 10 becomes a saturation current, and the third transistor 10 acts as a constant current source.

Therefore, the voltage at the point C is not affected by the third transistor 10 and becomes a mirror potential determined by the current mirror circuit 1. At this time, the output current of the current mirror circuit 1 changes according to the gate voltage of the third transistor 10 (the output voltage of the differential amplifier 9). The output voltage of the differential amplifier 9 is the power supply voltage V
As a result, a current proportional to the power supply voltage Vdd can be obtained from the current mirror circuit 1.

Next, FIG. 2 shows a configuration example of a power supply voltage compensation type integration delay circuit to which the variable current source of the present embodiment configured as described above is applied. As shown in FIG. 2, the power supply voltage compensation type integration delay circuit 20 of the present embodiment includes a variable current source 21
, A capacitor 22, an inverter 23, and a switch 24 including a CMOS transistor or the like.

The internal configuration of the variable current source 21 is as shown in FIG. 1, and the output current of the second transistor 3 constituting the current mirror circuit 1 is supplied to the switch 24. A clock signal generated by a clock generation circuit (not shown) is applied to the gate terminal of the switch 24, and the switch 24 is turned ON only during the clock pulse.

When the switch 24 is turned on by the supply of the clock signal, the current supplied from the variable current source 21 through the switch 24 is integrated by the capacitor 22 by the integration operation.
Is gradually accumulated as an integrated voltage in the inverter 2
The input to 3 gradually increases. Thereafter, by outputting the clock when the integrated voltage exceeds the logical threshold of the inverter 23, the clock can be delayed by the time from the start of the integration until the threshold is reached.

At this time, the logical threshold value of the inverter 23 is
Although it changes in proportion to the power supply voltage Vdd, the supply current is changed by the variable current source 21 in proportion to the power supply voltage Vdd. Correspondingly, the integration speed (rise curve of the integration voltage) can be changed, and a constant delay amount can be maintained.

In the above embodiment, the current mirror circuit 1 is constituted by P-type MOS transistors 2 and 3, but may be constituted by N-type MOS transistors. Although the power supply voltage compensation type integration delay circuit has been described as one application example of the variable current source according to the present embodiment, this is merely an example, and the input current changes in proportion to the fluctuation of the power supply voltage. Can be applied to any circuit requiring

[0028]

As described above, the present invention forms a current mirror circuit by connecting the gates of the first transistor and the second transistor to each other, and forms a current mirror circuit on the side (leg portion) where the gates are connected. A first resistor and a second resistor on opposite sides
The first power line is connected via the resistor of
The legs of the current mirror circuit are connected to the output of a differential amplifier that receives the voltage stepped down by the third resistor and the voltage stepped down by the first resistor of the resistor voltage dividing circuit that divides the power supply voltage. And a third transistor for controlling the current flowing through the first transistor, the third transistor can act as a constant current source, and a current proportional to the fluctuation of the power supply voltage is supplied to the current mirror. Can be reliably taken out.

Further, in the present invention, the power supply voltage compensation type integration delay circuit is configured using the variable current source configured as described above, so that the logical threshold value of the inverter forming the integration delay circuit is proportional to the power supply voltage. Even if it changes, a constant amount of delay can be maintained by changing the supply current from the variable current source in proportion to the power supply voltage.

[Brief description of the drawings]

FIG. 1 is a diagram showing one embodiment of a variable current source according to the present invention.

FIG. 2 is a diagram showing an embodiment of a power supply voltage compensation type integration delay circuit to which a variable current source according to the present invention is applied.

FIG. 3 is a diagram illustrating a configuration example of a conventional integration delay circuit.

FIG. 4 is a diagram showing another configuration example of the conventional integration delay circuit.

FIG. 5 is a diagram showing still another configuration example of the conventional integration delay circuit.

FIG. 6 is a diagram showing an example of a possible configuration for obtaining a current proportional to a power supply voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Current mirror circuit 2 1st transistor 3 2nd transistor 4 1st resistor 5 2nd resistor 6 Resistor voltage dividing circuit 7 3rd resistor 8 4th resistor 9 Differential amplifier 10 3rd transistor 20 Power supply Voltage compensation type integration delay circuit 21 Variable current source 22 Capacitor 23 Inverter 24 Switch

Claims (4)

[Claims] 1. A first transistor connected to a first power supply line via a first resistor, and the first power supply via a second resistor having the same resistance value as the first resistor. A current mirror circuit configured by connecting the gates of a second transistor connected to the line to each other; a third resistor connected to the first power supply line; and a series connected to the third resistor A resistor voltage dividing circuit for dividing a power supply voltage supplied between the first power supply line and the second power supply line; and a voltage stepped down by the first resistance, A differential amplifier applied to an input terminal and configured to apply a voltage stepped down by the third resistor of the resistance voltage dividing circuit to the other input terminal; The current flowing through the first transistor A variable current source comprising: a third transistor to be controlled. 2. The method according to claim 1, wherein the first transistor and the second transistor are P-type MOS transistors.
2. The variable current source according to claim 1, wherein said third transistor comprises an N-type MOS transistor. 3. A power supply voltage compensation type integration delay circuit comprising the variable current source according to claim 1. 4. A variable current source according to claim 1, a switch that is turned on / off in response to an input clock, and an integrated voltage according to a current supplied from the variable current source when the switch is turned on. A power supply voltage compensation type integration delay circuit comprising: a storage capacitor; and an inverter circuit connected in parallel to the capacitor.