JP2000163970A - Back-bias circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a back-bias circuit which can improve the manufacture yield of a semiconductor device, obtains target transistor characteristics, and enables manufacture of a semiconductor chip having performance exactly as designed. SOLUTION: A detection circuit 12 for a back-bias voltage VBB comprises a current mirror circuit composed of P-channel transistors T1 to T3, which supply the current of a current source 20 to a 1st reference potential node Vref1 and a 2nd reference potential node Vref2, two N-channel reference transistors T4 and T5 which are connected between the 1st reference potential node Vref1 and the node of a ground electrode, a resistance 22 which is connected between the 2nd reference potential node Vref2 and the node of the back-bias voltage VBB, and a differential amplifier 23 which inputs the 1st and 2nd reference potential node Vref1 and Vref2, and the back-bias voltage VBB is optimized by detecting the threshold voltage of the transistors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a back bias circuit for applying a back bias voltage for correcting a threshold voltage of a transistor to a semiconductor device including a plurality of transistors.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device including a plurality of transistors, a back bias is applied to a substrate on which the semiconductor device is formed in order to correct a threshold voltage of the transistor on the substrate. A back bias circuit for applying a voltage is widely used.

In a semiconductor device provided with such a back bias circuit, an impurity is diffused or implanted into the surface of the semiconductor substrate before forming a gate electrode on the semiconductor substrate, thereby forming the semiconductor device. The threshold voltage of the transistor is determined.

A generator for a back bias circuit is provided on the semiconductor substrate, and a detection circuit for controlling the operation of the back bias circuit is provided so that the back bias voltage becomes a predetermined voltage.

[0005]

However, in a semiconductor device having a conventional back bias circuit as described above, the threshold voltage of the transistor is determined before the gate electrode is formed on the substrate. The threshold voltage of the transistor fluctuates due to variations in the dimensions of the gate electrode and variations in the thermal history. At this time, when the back bias voltage is fixed to the predetermined voltage, there is a problem that the fluctuation of the threshold voltage cannot be corrected.

Therefore, since the above-described change in the threshold voltage cannot be corrected, the back bias voltage cannot be changed in accordance with the change, so that the manufacturing yield of the semiconductor device is deteriorated and the transistor characteristics are reduced. And it is difficult to manufacture a semiconductor chip having the performance as designed.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. In a semiconductor device, a back bias voltage can be changed in accordance with a change in a threshold voltage of a transistor, thereby improving the semiconductor device manufacturing yield. And a back bias circuit capable of producing a semiconductor chip having a designed performance with a desired transistor characteristic.

[0008]

In order to solve the above problems, a back bias circuit according to the present invention has a function of changing a back bias voltage in accordance with a change in a threshold voltage.
By detecting the difference between the voltage proportional to the threshold voltage of the transistor and the voltage proportional to the back bias voltage, and controlling the back bias generation circuit, variations in gate electrode dimensions, variations in impurity implantation, and thermal history Even if the threshold voltage fluctuates due to variations in the threshold voltage, the threshold voltage of the transistor is corrected by detecting the fluctuation and controlling and changing the back bias voltage.

Further, since the potential of the back bias voltage is set to be high when the operating temperature is high, a leakage current of the transistor to which the back bias is applied at a high temperature is suppressed.

Further, since the back bias voltage is constant irrespective of the power supply voltage, the back bias voltage is kept constant even when the power supply voltage becomes low, thereby suppressing an increase in leakage current.

In particular, the present invention is characterized in that the data retention characteristics of a dynamic random access memory (DRAM) are prevented from deteriorating. As described above, in the semiconductor device, the back bias voltage can be changed in accordance with the change in the threshold voltage of the transistor, and the manufacturing yield of the semiconductor device can be improved. A semiconductor chip having the following performance can be manufactured.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a back bias circuit according to a first aspect of the present invention, a back bias voltage for correcting a threshold voltage of a transistor for a semiconductor device including a plurality of transistors is provided. A back bias circuit configured to apply a back bias voltage, configured by a charge pump circuit, and outputting the back bias voltage; detecting a back bias voltage from the back bias generation circuit; And a detection circuit for controlling ON / OFF of the operation of the bias generation circuit.

The back bias circuit according to claim 2 is
The detection circuit according to claim 1 is configured such that the back bias voltage output from the back bias generation circuit is constant independently of the power supply voltage.

The back bias circuit according to claim 3 is
3. A detection circuit according to claim 1, wherein one end of the detection circuit is connected to a ground node formed of a ground electrode having a ground potential, and the other end of the current source is connected to the current source. A current mirror circuit for causing a proportional current to flow through the first reference potential node and the second reference potential node;
A first resistance element connected between the first reference potential node and a ground node, and a second resistance element connected between the second reference potential node and a node to which a back bias voltage is input. A resistance element; and first and second input terminals to which voltages of the first and second reference potential nodes are respectively inputted, and based on a voltage difference between them, the operation of the back bias generation circuit is turned on. -It is composed of a differential amplifier that outputs a control signal for off control.

The back bias circuit according to claim 4 is
The current source according to claim 3 is configured such that its output current is constant without depending on the power supply voltage. According to a fifth aspect of the present invention, there is provided a back bias circuit comprising the current source according to the third or fourth aspect, comprising a first P-channel transistor having a source connected to a power supply and a gate and a drain connected to a first node. A second P-channel transistor having a drain connected to the second node, a gate connected to the first node, a source connected to the power supply via a third resistance element, and a source connected to the first P-channel transistor. A first N-channel transistor connected to a node, a gate connected to the second node, and a drain connected to a ground electrode having a ground potential;
A second N-channel transistor having a source and a gate connected to the second node and a drain connected to the ground electrode; a gate connected to the second node, a source connected to the ground electrode, and a drain connected to the output; And a third N-channel transistor serving as a node.

The back bias circuit according to claim 6 is
The absolute value of the back bias voltage output from the back bias generating circuit according to any one of claims 1 to 5 is dependent on temperature and is proportional to the operating temperature.

The back bias circuit according to claim 7 is
The current source according to any one of claims 3 to 5 is configured such that its output current is temperature-dependent and proportional to the operating temperature.

The back bias circuit according to claim 8 is
3. A detection circuit according to claim 1, wherein one end of the current source is connected to a ground node formed of a ground electrode having a ground potential, and the other end of the current source is connected to the current source. A current mirror circuit for flowing current through a first reference potential node and a second reference potential node; one or more reference transistors connected between the first reference potential node and a ground node; Resistance element connected between the second reference potential node and a node to which the back bias voltage is input, and first and second input terminals to which the voltages of the first and second reference potential nodes are input, respectively. And a differential amplifier that outputs a control signal for on / off control of the operation of the back bias generation circuit based on the voltage difference therebetween.

The back bias circuit according to claim 9 is
9. A back bias circuit for outputting a predetermined back bias voltage under a predetermined manufacturing condition, wherein the absolute value of the back bias voltage output from the back bias generation circuit according to claim 1. However, due to the variation in the manufacturing conditions, the threshold voltage of the configured transistor is inversely proportional to the threshold voltage.

A back bias circuit according to a tenth aspect is a back bias circuit configured in a dynamic random access memory, and the back bias generation circuit according to any one of the first to ninth aspects. The back bias voltage output from the
It is configured to be supplied to a substrate of a transistor constituting a memory cell in a random access memory.

A back bias circuit according to an eleventh aspect is a back bias circuit configured in a dynamic random access memory, wherein a back bias voltage output from the back bias generation circuit according to the eighth aspect is provided. Is supplied to a substrate of a transistor forming a memory cell in the dynamic random access memory, and configures a reference transistor to have the same structure as a transistor forming the memory cell.

A back bias circuit according to a twelfth aspect is a back bias circuit configured in a dynamic random access memory and outputting a predetermined back bias voltage under a predetermined manufacturing condition. Item 9: The absolute value of the back bias voltage output from the back bias generating circuit according to Item 8 is configured to be inversely proportional to the threshold voltage of the configured transistor due to variations in manufacturing conditions. Is supplied to a substrate of a transistor forming a memory cell in the dynamic random access memory, and configures a reference transistor to have the same structure as a transistor forming the memory cell.

According to the above structure, the function of changing the back bias voltage in accordance with the change in the threshold voltage is provided, and a voltage proportional to the threshold voltage of the transistor and a voltage proportional to the back bias voltage are determined. By detecting the difference and controlling the back bias generation circuit, even if the threshold voltage fluctuates due to variations in gate electrode dimensions, variations in impurity implantation, and variations in thermal history, etc. The bias voltage is controlled and changed to correct the threshold voltage of the transistor.

Further, since the potential of the back bias voltage is set to be high when the operating temperature is high, the leakage current of the transistor to which the back bias is applied at a high temperature is suppressed.

Since the back bias voltage is constant irrespective of the power supply voltage, the back bias voltage is kept constant even when the power supply voltage becomes low, thereby suppressing an increase in leakage current.

In particular, it is possible to prevent the data holding characteristic of the dynamic random access memory (DRAM) from deteriorating. Hereinafter, a back bias circuit according to an embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a back bias circuit according to an embodiment of the present invention. As shown in FIG. 1, the back bias circuit 10 includes a back bias generation circuit 11 and a detection circuit 12. An output node of the back bias generation circuit 11 is connected to a semiconductor substrate of the semiconductor device and outputs a back bias voltage VBB. Further, a control signal GE for controlling the operation / stop is input to the back bias generation circuit 11. The detection circuit 12 receives the back bias voltage VBB and outputs a control signal GE.

FIG. 2 is a circuit diagram showing a configuration example of the detection circuit 12 in the back bias circuit 10 according to the embodiment of the present invention. 2, the detection circuit 12 includes P-channel transistors T1 to T3 connected in a current mirror type.
, A current source 20, a reference potential generating load 21, a trimmable resistor 22, a differential amplifier 23, and inverters 24 and 25.

The P-channel transistor T1 is composed of a P-channel MOSFET whose gate and drain are connected to the current source 20, and whose substrate and source are connected to the power supply voltage VDD.

The P-channel transistor T2 has a gate connected to the gate of the P-channel transistor T1, a substrate and a source connected to the power supply voltage VDD so as to form a current mirror circuit with the P-channel transistor T1,
The drain is a node (first reference potential node) Vref1
And a P-channel MOSFET connected to.

The P-channel transistor T3 has a gate connected to the gate of the P-channel transistor T1, a substrate and a source connected to the power supply voltage VDD so as to form a current mirror circuit with the P-channel transistor T1,
The drain is a node (second reference potential node) Vref2
And a P-channel MOSFET connected to.

The reference potential generating load 21 is connected to the node Vre
An N-channel transistor (N-channel MOSFE) diode-connected between f1 and a ground electrode which is a ground potential.
T) It is composed of T4 and T5. These N-channel transistors T4 and T5 are manufactured with the same structure and the same process as the transistor to which the back bias voltage VBB is applied. However, the ground potential voltage is applied to the substrates of the N-channel transistors T4 and T5. Here, two N-channel MOSFETs are shown as diode-connected N-channel transistors. However, only one N-channel MOSFET may be used, or three or more N-channel MOSFETs may be connected in series.

The resistor 22 is composed of, for example, a polysilicon resistor or a silicide resistor. The resistor 22 is connected to the node V
It is connected between ref2 and the node of the back bias voltage VBB. The resistance value of the resistor 22 is set to a desired resistance value R. The resistor 22 is formed by connecting a plurality of units each including a plurality of resistance elements and a fuse element connected in parallel, and cutting the fuse element by a known technique such as laser trimming to obtain a desired resistance value. It may be configured to be set to R.

The differential amplifier 23 has the node Vref1 and the node Vref2 as inputs to the-terminal and the + terminal, and outputs the output to the inverter 24 for waveform shaping.
The buffer inverter 25 has a configuration in which the input is connected to the output of the inverter 24 and the output is connected to the node of the control signal GE. Here, as an example, two-stage connection is made using the inverters 24 and 25. However, it is also possible to connect a large number of inverters, or to omit the inverter and output the differential amplifier 23 to the node of the control signal GE. It may be configured to be directly connected.

FIG. 3 is a circuit diagram showing the configuration of the current source 20 in FIG. The current source 20 basically includes a set of P-channel transistors (P-channel MOSFETs) 31 and 35 connected in a current mirror type, and N-channel transistors (N-channel MOSFETs) 36, 37 and 39.
And a resistor 38.

The current source 20 includes a P-channel transistor 31 having a substrate and a source connected to a power supply voltage VDD and a gate and a drain connected to a node 32, and a substrate and a source connected to a node 33 and a gate connected to the node 32. A P-channel transistor 35 having a drain connected to a node 34; an N-channel transistor 36 having a source and a gate connected to the node 34 and a drain grounded to a ground electrode; and a source connected to the node 32 and a gate connected to the node 34. -Channel transistor 37 connected to a power supply voltage VDD and node 3
3 and a gate connected to the node 34.
And an N-channel transistor 39 whose drain is grounded to the ground electrode and whose source receives output current Ia.

FIG. 4 shows the back bias generation circuit 1 shown in FIG.
FIG. 2 is a circuit diagram showing one configuration example of the present invention. This circuit has a configuration in which the operation / stop of the back bias generation operation can be controlled by the control signal GE. This back bias generation circuit 11
Is an N-channel transistor (N-channel MOSFET) 4 which is a capacity transistor connected to form a capacitor with a ring oscillator 40, an inverter 41, and
2 and an N-channel transistor (N-channel MOSFE
T) 43, 44.

The ring oscillator 40 is a circuit that generates a pulse of a fixed period when the control signal GE is at H level (high level), and stops the pulse when the control signal GE is at L level (low level). is there. The inverter 41 is
It receives the output of ring oscillator 40 and plays the role of a buffer for shaping the output waveform. N-channel transistor 42 has a gate connected to the output of inverter 41, a source and a drain short-circuited, and connected to the gate and source of N-channel transistor 43 and the source of N-channel transistor 44. The drain of N-channel transistor 43 is grounded to a ground electrode, and the drain of N-channel transistor 44 is back bias voltage VB
B is output. These N-channel transistors 42, 4
Reference numerals 3 and 44 constitute a charge pump circuit.

FIG. 5 is a circuit diagram showing an example of the configuration of the differential amplifier 23 in FIG. This differential amplifier 23 basically includes a P-channel transistor (P-channel MOSFE).
T) 50, 51; N-channel transistors (N-channel MOSFETs) 52, 53; and N-channel transistors (N-channel MOSFETs) 54 for current control.

The differential amplifier 23 includes P-channel transistors 50 and 51 arranged in a current mirror type.
And N-channel transistors 52 and 53 connected to their drains, forming a general differential amplifier grounded to a ground electrode via an N-channel transistor 54.

Next, before describing the operation of the detection circuit 12 shown in FIG. 2, the operation of the current source 20 shown in FIG. 3 will be briefly described first. In FIG. 3, if the dimensions of the N-channel transistors (N-channel MOSFETs) 36 and 37 are equal to the threshold voltage Vtn, the N-channel transistors 36 and 37 constitute a current mirror circuit with each other. The current Io flowing through 37 also flows through P-channel transistors (P-channel MOSFETs) 31 and 35. If the threshold voltage of the P-channel transistor 31 and 35 equally Vtp, currents flowing through the transistors 31,35,36,37 _{is, Io = β 31 · (V} 32 -VDD-Vtp) 2 Io = β 35 (V ₃₂ −VDD + Io · R ₃₈ −Vtp) ² Io = β ₃₆ (V ₃₄ −Vtn) ² Io = β ₃₇ (V ₃₄ −Vtn) ² Here V ₃₂ is the voltage of the node 32, V ₃₄ is the voltage at the node 34, R ₃₈ is the resistance of the resistor 38.

[0042] Here, by modifying the above equation from β ₃₆ = β _37, obtain ^{_{Io = 1 / (R 38 2}} · β 31) · (1- (β 31 / β 35) 0.5) 2. Since the N-channel transistor 36 and the N-channel transistor (N-channel MOSFET) 39 form a current mirror circuit, this circuit
And outputs a current Ia which is a constant multiple of.

On the other hand, according to this configuration, it can be seen that the current output from the current source 20 is proportional to 1 / β. That is, the current source 20 shown in FIG. 3 has a characteristic that the current increases when the operating temperature of the circuit is high, and decreases when the operating temperature is low. The current Ia output from the current source 20 also has a feature that does not depend on the power supply voltage VDD.

Next, the operation of the detection circuit 12 shown in FIG. 2 will be described. P-channel transistor (P-channel M
The current Ia flows through the OSFET) T1. In the P-channel transistors (P-channel MOSFETs) T2 and T3 connected in a current mirror type, currents Ib and Ic determined by a ratio between their respective gate lengths and gate widths flow.

The voltage value of node Vref1 is VBB back bias transistor (N-channel MOSFET) T
4. Assuming that the threshold voltage of T5 is Vt1, 2 · Vt1
Voltage. The voltage value of the node Vref2 is
Is R22 · Ic + VBB, where R22 is the resistance value of R22. The resistance value R22 is selected such that R22 · Ic + VBB = 2 · Vt1 when the back bias voltage is at a desired potential.

The voltage at node Vref2 is
When the voltage is higher than the voltage of f1, the control signal GE is set to the high level by the differential amplifier 23, the back bias generation circuit 11 is activated, and the back bias voltage VBB is set to the negative potential. Then, the back bias voltage VBB becomes a negative potential, and the voltage of the node Vref2 becomes the node Vref.
If the voltage is lower than 1, the control signal GE is set to low level, and the back bias generation circuit 11 is stopped. Thus, the back bias voltage VBB is set to a desired potential.

If the threshold voltage of the transistor group to which the back bias voltage VBB is applied becomes low due to the influence of the variation of the impurity implantation, the variation of the dimensions, the variation of the thermal history, and the like, the voltage of the node Vref1 is reduced. Lower. In this case, the voltage of the node Vref2 and the node Vre
Back bias voltage VBB that is equal to the voltage of f1
The threshold voltage of the transistor group to which the back bias voltage VBB is applied is set to a deeper negative voltage as compared with the case where the transistor is manufactured as intended. Therefore, the threshold voltage of the transistor group to which the back bias voltage VBB is applied can be increased by the back bias effect,
It can be corrected to the target transistor performance.

If the threshold voltage of the transistor group to which the back bias is applied rises due to the influence of the variation of the impurity implantation, the variation of the dimensions, the variation of the thermal history, etc., the voltage of the node Vref1 becomes high. Become. In this case, the back bias voltage VBB at which the voltage at the node Vref2 is equal to the voltage at the node Vref1 is a shallower negative voltage than when the threshold voltage of the transistor group to which the back bias is applied is manufactured as intended. Is set to Therefore, the threshold voltage of the transistor group to which the back bias is applied due to the back bias effect can be reduced, and the desired transistor performance can be corrected.

As described above, the reference potential generating load 21 may be a series connection of one diode-connected transistor, or may be a series connection of three or more transistors. In the former case, the fluctuation of the level of the back bias voltage VBB with respect to the fluctuation of the threshold voltage can be set small, and in the latter case, the fluctuation of the level of the back bias voltage VBB with respect to the fluctuation of the threshold voltage is set large. can do.

On the other hand, when the configuration shown in FIG. 3 is used as the current source 20, when the operating temperature of the chip increases, the current Ia increases as described above. However, Ic also increases due to the Miller effect. As a result, as a result, the node Vre
The potential of f2 increases, and the back bias voltage is set to a deep negative potential. Conversely, if the temperature is low, the node Vre
The potential of f2 decreases, and the back bias voltage is set to a shallow negative potential.

When this circuit is used for a dynamic random access memory (DRAM) and is used for applying a back bias voltage to a transistor constituting the memory cell, the circuit operates at a high temperature which poses a problem in the DRAM. With regard to the data retention capability period, the back bias voltage is deepened at a high temperature and the threshold voltage is increased, so that the leakage current can be suppressed and the data retention capability period can be extended.

According to this circuit configuration, the power supply voltage V
As described above, the current Ia is constant irrespective of the DD, but Ic is also constant due to the Miller effect. As a result, a constant back bias voltage VBB is set independent of the power supply voltage VDD. be able to.

The back bias generation circuit 11 shown in FIG.
Is a general charge pump circuit, and the description of its operation is omitted here.

[0054]

As described above, according to the present invention, the function of changing the back bias voltage according to the change in the threshold voltage is provided. By detecting the difference between the threshold voltage and the voltage proportional to the threshold voltage and controlling the back bias generation circuit, even if the threshold voltage fluctuates due to variations in gate electrode dimensions, variations in impurity implantation, and variations in thermal history,
Detecting this and controlling and changing the back bias voltage,
The threshold voltage of the transistor can be corrected.

Further, since the potential of the back bias voltage is set to be high when the operating temperature is high, the leakage current of the transistor to which the back bias is applied at a high temperature can be suppressed.

Further, since the back bias voltage is constant irrespective of the power supply voltage, the back bias voltage is kept constant even when the power supply voltage becomes low, so that an increase in leak current can be suppressed.

In particular, it is possible to prevent the data holding characteristic of the dynamic random access memory (DRAM) from deteriorating. As described above, in the semiconductor device, the back bias voltage can be changed in accordance with the change in the threshold voltage of the transistor, and the manufacturing yield of the semiconductor device can be improved. A semiconductor chip having the following performance can be manufactured.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a back bias circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a detection circuit in the back bias circuit of the embodiment.

FIG. 3 is a circuit diagram showing a configuration of a current source in the back bias circuit of the embodiment.

FIG. 4 is a circuit diagram showing a configuration of a back bias generation circuit in the back bias circuit according to the embodiment;

FIG. 5 is a circuit diagram showing a configuration of a differential amplifier in the back bias circuit of the embodiment.

[Explanation of symbols]

Reference Signs List 10 back bias circuit 11 back bias generation circuit 12 detection circuit 20 current source 21 load for reference potential generation 22 resistor 23 differential amplifier 24 inverter 25 inverter 31, 35 P-channel MOSFET 32, 33, 34 node 36, 37, 39 N-channel MOSFET 38 Resistance 40 Ring oscillator 41 Inverter 42 Capacitance transistor 43, 44 N-channel MOSFET 50, 51 P-channel MOSFET 52, 53, 54 N-channel MOSFET GE Control signal T1, T2, T3 P-channel MOSFET T4, T5 VBB Back bias N Channel MOS
FET VBB Back bias voltage

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03F 1/30 H01L 27/04 G 5J090 H03K 19/094 D H03K 19/094 F term (reference) 5B024 AA03 BA27 CA07 5F038 AR09 AV02 AV15 BB01 BB08 BG09 CD03 DF05 EZ20 5F083 GA06 HA04 HA05 LA08 PR57 5H420 NA27 NB02 NC02 NC26 5J056 AA00 BB10 BB38 BB59 CC00 CC01 CC02 DD13 DD28 EE07 FF06 5J10 AA11A10 A11A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 A11 AA11 A11 A11 A11 AA11 A11 HA17 HA25 HA49 HN07 KA02 KA09 KA12 KA17 MA11 MN02 NN06 TA01

Claims (12)

[Claims] 1. A back bias circuit for applying a back bias voltage for correcting a threshold voltage of a transistor to a semiconductor device including a plurality of transistors, the back bias circuit including a charge pump circuit. A back bias generation circuit that outputs a back bias voltage; and a detection circuit that detects a back bias voltage from the back bias generation circuit and controls on / off of the operation of the back bias generation circuit in accordance with the voltage. A back bias circuit, comprising: 2. The back bias circuit according to claim 1, wherein the detection circuit is configured such that the back bias voltage output from the back bias generation circuit is constant independently of the power supply voltage. 3. A detecting circuit comprising: a current source connected to a ground node having a ground electrode having one end at a ground potential; and a current source connected to the other end of the current source and having a current equal or proportional to the current source. A current mirror circuit flowing through the first reference potential node and the second reference potential node; a first resistance element connected between the first reference potential node and a ground node; and a second reference potential node A second resistance element connected between the first input terminal and a node to which a back bias voltage is input; and a first and second input terminal to which voltages of the first and second reference potential nodes are input, respectively. And a differential amplifier for outputting a control signal for controlling ON / OFF of the operation of the back bias generating circuit based on the voltage difference between the two. Backba Ias circuit. 4. The back bias circuit according to claim 3, wherein the current source is configured such that its output current is constant independently of the power supply voltage. 5. A current source comprising: a first P-channel transistor having a source connected to a power supply and a gate and a drain connected to a first node; and a drain connected to a second node and a gate connected to the first node. A second P-channel transistor connected to a node and having a source connected to the power supply through a third resistance element, a source connected to the first node, a gate connected to the second node, and a drain connected to the second node; A first N-channel transistor connected to a ground electrode which is a ground potential; a second N-channel transistor having a source and a gate connected to the second node and a drain connected to the ground electrode; A third N-channel transistor connected to a second node, a source connected to the ground electrode, and a drain serving as an output node. The back bias circuit according to claim 3 or claim 4. 6. The system according to claim 1, wherein the absolute value of the back bias voltage output from the back bias generating circuit is dependent on the temperature and is proportional to the operating temperature.
The back bias circuit according to any one of claims 1 to 5. 7. The back bias circuit according to claim 3, wherein the current source is configured so that an output current thereof is dependent on temperature and is proportional to an operating temperature. 8. A detection circuit comprising: a current source connected to a ground node having a ground electrode having one end at a ground potential; and a current equal to the current source connected to the other end of the current source.
A current mirror circuit flowing between the first reference potential node and the second reference potential node; one or more reference transistors connected between the first reference potential node and a ground node; A resistance element connected between a potential node and a node to which a back bias voltage is input, and first and second input terminals to which voltages of the first and second reference potential nodes are respectively input 3. A differential amplifier according to claim 1, wherein said differential amplifier outputs a control signal for on / off control of the operation of said back bias generation circuit based on the voltage difference between them. Back bias circuit. 9. A back bias circuit for outputting a back bias voltage of a predetermined voltage under predetermined manufacturing conditions,
2. The method according to claim 1, wherein the absolute value of the back bias voltage output from the back bias generation circuit is inversely proportional to the threshold voltage of the transistor formed due to variations in manufacturing conditions. 9. The back bias circuit according to any one of 8. 10. A dynamic random access system.
A back bias circuit configured in a memory, wherein a back bias voltage output from a back bias generating circuit is supplied to a substrate of a transistor forming a memory cell in the dynamic random access memory. The back bias circuit according to any one of claims 1 to 9, wherein the back bias circuit is configured. 11. A dynamic random access system.
A back bias circuit configured in the memory, wherein a back bias voltage output from the back bias generating circuit is supplied to a substrate of a transistor forming a memory cell in the dynamic random access memory, and 9. The back bias circuit according to claim 8, wherein the transistor is configured to have the same structure as a transistor forming the memory cell. 12. A dynamic random access system.
A back bias circuit configured in a memory and outputting a back bias voltage of a predetermined voltage under a predetermined manufacturing condition, wherein an absolute value of the back bias voltage output from the back bias generating circuit varies depending on a variation in the manufacturing condition. And the back bias voltage is supplied to a substrate of a transistor constituting a memory cell in the dynamic random access memory, and 9. The back bias circuit according to claim 8, wherein the transistor is configured to have the same structure as a transistor forming the memory cell.