JP2000216251A - Method of designing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress speed performance deterioration caused by a wiring capacity, etc., by adopting a relay buffer insertion method, and in addition, to realize a low-clock skew that does not rely upon voltage or temperature characteristics. SOLUTION: In a block 1 adjoining the route from a clock-supplying source to a clock-supplying destination, the disturbance to a signal line passing through a wiring inhibiting region 5 can be avoided by generating an arrangement inhibiting region 5 and the wiring inhibiting region 5 in the block 1 along the clock-wiring path-side edge. In addition, since relay buffers 4 are arranged in the regions 7 and 5, delay adjustment can be performed without correcting the arranged positions of cells. Moreover, a circuit which does not rely upon voltage or temperature characteristics is generated, by making a wiring delay and a cell delay equal to each other, by making the wiring of clock signals to each destination with the same length and the same capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout of a semiconductor integrated circuit operating in synchronization with a clock, and more particularly to a method of designing a semiconductor integrated circuit capable of reducing clock skew. In particular, the present invention relates to a technique effective for skew measures when a clock signal is supplied from a clock supply source to a plurality of logic circuits arranged on a substrate.

[0002]

2. Description of the Related Art Conventionally, the layout of a semiconductor integrated circuit is as follows.
In both of the layout method of the building block method and the flat layout, the arrangement and wiring have been performed in two stages between blocks composed of a plurality of logic cells.

[0003] In addition, with regard to skew adjustment within a block, a skew can be sufficiently suppressed by generating a clock tree even with a commercially available VAD tool, but skew adjustment between blocks is performed by a wiring method inside the block. Buffer two blocks in the same way,
A method has been proposed in which the intermediate point is connected as a node to suppress skew.

Further, as shown in FIG. 2, delay adjusting cells 2 of the same size and different cell delay values are prepared in a block 1, and the delay adjusting cells are changed according to the wiring delay between the blocks. A technique for suppressing the skew by using the same has been proposed.

As a method for inserting a relay buffer at a certain interval with respect to speed performance degradation due to long-distance wiring between blocks, there is a proposal as disclosed in Japanese Patent Laid-Open No. Hei 6-334442. . This relay buffer insertion method is a method of arranging columns of relay buffer cells 4 vertically and horizontally in a chip 3 as shown in FIG. 1 and laying them out at regular intervals in a clock signal via a relay buffer. Met.

[0006]

In the skew adjustment method between blocks as described above, when wiring is to be performed by an automatic wiring tool, in the former method, a plurality of the same nets are placed in the same channel by the channel router. This is impossible because of existing wiring.

In the method of adjusting the skew in the delay adjustment cell, it is difficult to adjust the skew because the cell delay and the wiring delay vary separately with respect to the power supply voltage and the temperature. Furthermore, in the method of arranging the relay buffers in a grid pattern to cope with the speed performance degradation due to long-distance wiring,
Since the wiring length is different in each clock wiring path, the skew adjustment described above is difficult.

[0008]

In order to solve the above problem, in the present invention, when laying out a block, the upper layer is limited to a vertical layer or a horizontal layer in advance in consideration of a clock signal path in an upper hierarchy. By forming a wiring prohibited area, equal-length and equal-capacity wiring is performed.

In addition, by forming an arrangement prohibited area in the same area as the wiring prohibited area and arranging the relay buffer cells, it is possible to cope with the speed performance degradation due to long distance wiring.

Further, the skew can be adjusted by combining the above-mentioned wiring area when adjusting the skew between the blocks.

[0011]

According to a first aspect of the present invention, there is provided a method of designing a semiconductor integrated circuit, in which a clock signal is supplied to a plurality of circuits in synchronization with a clock signal supply source and a destination. This is a design method for long and equal-capacity wiring. In consideration of the clock signal path in the upper layer when performing the block layout, the vicinity of a specific side inside the block is limited to a vertical layer or a horizontal layer. Create a prohibited routing area and perform placement and routing, and use the prohibited routing layer in the routing prohibited area created when adjusting the skew between blocks without changing the existing intra-block routing. Wiring of equal length and equal capacity can be performed.

According to a second aspect of the present invention, there is provided a method for designing a semiconductor integrated circuit device, comprising:
A design method for arranging relay buffer cells in order to cope with speed performance degradation due to long-distance wiring, wherein a layout prohibited area is created in the same area as in claim 1 when performing block layout. By arranging the relay buffer cells when the wiring resistance and capacitance between the blocks exceed the specified values, it is possible to reduce the speed performance degradation due to long-distance wiring without changing the cell arrangement in the block.

Hereinafter, specific embodiments of a method of designing a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the drawings. Specifically, a CMOS LSI with a standard cell design is taken as an example of a semiconductor integrated circuit device.

(Embodiment 1) FIG. 3 is a view for explaining a method of designing a semiconductor integrated circuit device according to the first embodiment. FIG. 3 (a) shows a chip layout pattern of the semiconductor integrated circuit. (B) shows a wiring prohibition pattern in the wiring prohibition area 5 in (a).

In FIG. 3, an H-shaped wiring path in the block represents a wiring shape after clock tree synthesis has been performed in the block. Although not shown at the end of the H-shaped wiring path, further fine H-shaped wirings are provided according to the number of stages of the clock tree, and are connected to cells such as flip-flops to which clock signals are supplied.

Normally, a block is divided to perform a chip layout of a semiconductor integrated circuit, a floor plan is performed before a block layout is performed, and a wiring route of each signal is determined to some extent to determine an external pin position of the block 1. I do.

Next, when laying out each block 1, a wiring prohibited area 5 is created as shown in FIG. 3A so as to be adjacent to the wiring path of the clock signal determined in the floor plan. I do. At this time, the wiring prohibition layer in the wiring prohibition area 5 to be created is, as shown in FIG. 3B, a vertical wiring layer when the wiring prohibition area 5 is on the left and right sides of a block adjacent to the vertical channel. In the case of the upper and lower sides of a block adjacent to the channel in the horizontal direction, only the horizontal wiring layer is used.

Here, by prohibiting the wiring layers only in the vertical direction or the horizontal direction, respectively, the path of the signal line for connecting the inside and the outside of the block 1 through the wiring prohibited area 5 is not blocked. Therefore, the influence on other signal lines due to the creation of the wiring prohibited area 5 can be minimized.

Then, at the stage of the delay adjustment processing between the blocks after the arrangement and wiring of the blocks are completed, the clock signal path from the clock signal supply source to the block at the longest distance and the clock signal path to each of the other blocks are changed. The difference between the wiring capacitance and the wiring resistance is calculated, and a wiring pattern corresponding to the calculated difference is formed in the wiring prohibited layer in the wiring prohibited area where the clock signal is supplied from the clock signal supply source. Equal length and equal capacity wiring to the signal supply destination can be realized.

(Embodiment 2) FIG. 4 is a diagram for explaining a method of designing a semiconductor integrated circuit device according to the second aspect. FIG. 4A shows a chip layout pattern of the semiconductor integrated circuit. (B) shows an arrangement diagram of the relay buffer cell 4 and the circuit correction cell 6 in the arrangement prohibited area in (a).

In FIG. 4A, the H-shaped wiring path in the block shows the wiring shape of the clock tree when the layout in the block is performed as in the first embodiment. Further, the processes up to the floor plan and the route determination of the clock signal are performed in the same manner as in the first embodiment. Subsequently, an arrangement prohibited area 7 is created around the block 1 by the same method as the method for determining the wiring prohibited area 5 in the first embodiment. The same area as the area where the placement prohibited area 7 is created is set as the wiring prohibited area 5 of the vertical wiring layer or the horizontal wiring layer as in the first embodiment, and the placement and wiring inside the block is completed. When performing inter-block wiring, first, general wiring is performed, and a wiring load capacity of a clock signal supply source and a destination which is the longest is calculated. If the capacity exceeds the allowable value, a relay buffer cell 4 is inserted.

Here, the relay buffer cells 4 are inserted into the placement prohibition areas 7 of the blocks adjacent to the wiring paths so that the wiring paths are equally divided by the number of the inserted relay buffer cells 4 with respect to the additional wiring capacity. Deterioration of speed performance can be reduced for the longest wiring.

Then, the same number of relay buffer cells 4 as the relay buffer cells 4 inserted on the longest clock wiring path are also inserted on other clock wiring paths, and the wiring prohibited area 5 created above is used. By designing the longest clock wiring path and the wiring pattern of the same length and the same capacity to minimize the skew of the clock signal and to reduce the speed performance degradation for long distance wiring Can be.

[0024]

As described above, according to the present invention, in a synchronous semiconductor integrated circuit device, a wiring prohibited area or a layout prohibited area having a limited layer inside a block is created according to a certain rule, and delay between blocks is adjusted. By using the area at the time of processing, delay adjustment can be performed without changing the arrangement and wiring inside the block. As a result, the TAT of the semiconductor design can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a design technique for arranging a relay buffer array according to a conventional technique.

FIG. 2 is a diagram showing a design technique using a delay adjustment cell according to the related art.

FIG. 3 is an explanatory diagram of a design method of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is an explanatory diagram of a design method for a semiconductor integrated circuit device according to a second embodiment of the present invention;

[Explanation of symbols]

 1 block 2 delay adjustment cell 3 chip 4 relay buffer cell 5 wiring prohibited area 6 circuit correction cell 7 placement prohibited area

Claims (2)

[Claims] 1. A design method for performing equal-length and equal-capacity wiring between a clock signal supply source and a clock signal supply destination, wherein a shape of a region is adjusted to a region adjacent to a wiring route in consideration of a clock wiring route. A vertical or horizontal wiring prohibited area in advance, and use that area to
A method for designing a semiconductor integrated circuit, wherein equal capacitance wiring is performed. 2. An equal-length / equal-capacity wiring is performed by setting a region similar to the wiring-prohibited region as a placement-prohibited region, arranging a relay buffer cell for amplifying a signal in the layout-prohibited region. 2. The method for designing a semiconductor integrated circuit according to 1.