JP2009105091A - Signal line arranging method and arrangement wiring apparatus for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily wire signal lines of a semiconductor device by decreasing the number of wiring tracks used to wire the signal lines. <P>SOLUTION: The signal line arrangement method includes: generating a clock tree and then dividing an LSI chip into a plurality of regions each including a clock buffer and a leaf cell (S15 in Fig. 1); moving clock buffers in the respective divided regions to a horizontal column where clock skew has a proper value (S16); and wiring output-side clock signal lines of the clock buffers disposed in the same horizontal column (S18). <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a signal line arrangement method for a semiconductor device and a semiconductor device arrangement / wiring apparatus.

In a semiconductor device using a clock signal with a high frequency, it is necessary to suppress a clock skew (time shift of the clock signal) in each part of the circuit to a certain value or less.
Patent Document 1 describes that clock skew is reduced by wiring signal wiring of a time reference signal of a semiconductor device adjacent to each other through a shield wiring.

  Patent Document 2 calculates the transition frequency ratio between all paths between flip-flops and adjacent paths, and changes the wiring order of paths and adjacent paths so that delay variation due to crosstalk is less likely to occur. It is described that an increase in area due to a change in wiring is suppressed and a layout in which crosstalk does not easily occur between adjacent wirings is described.

  When determining the wiring of the clock signal of the semiconductor device, the arrangement of a plurality of clock buffers is determined so that the clock skew of a cell such as a flip-flop is minimized, and the clock signal line for supplying the clock signal from the clock buffer to each cell Is determined.

However, in the conventional arrangement method, as the number of clock buffers constituting the clock tree increases, the number of wiring tracks used for the clock signal line increases, and the routable area for wiring other signal lines becomes narrower. There was a problem.
JP 2000-236068 A JP 2003-303217 A

  An object of the present invention is to reduce the number of wiring tracks used for wiring of signal lines of a semiconductor device so that wiring of other signal lines can be easily performed.

In this signal line arranging method, each of a plurality of different signal lines is arranged as a partial wiring on a wiring track in a routable area of the semiconductor device.
According to this signal line arrangement method, the number of wiring tracks used for signal line wiring can be reduced, so that a sufficient wiring area can be secured for wiring of other signal lines.

In the signal line arranging method, two or more signal lines of the plurality of signal lines are arranged on the same wiring track, and a common shield line is arranged for the two or more signal lines.
With this configuration, since the shield lines of the plurality of signal lines can be made common, the number of wiring tracks used for the wiring of the shield lines can be reduced.

  In the above signal line arrangement method, two or more signal lines of the plurality of signal lines are arranged in adjacent wiring tracks and common to two or more signal lines arranged in adjacent wiring tracks. Place the shield wire.

With this configuration, since the shield lines of the plurality of signal lines can be made common, the number of wiring tracks used for the wiring of the shield lines can be reduced.
In the above signal line arrangement method, when the clock skew of a plurality of cells connected to the plurality of signal lines is equal to or greater than a reference value, the line width of the corresponding signal line is adjusted so that the clock skew is less than the reference value. .

With this configuration, the clock skew can be made less than the reference value by adjusting the line width of the signal line.
The arrangement / wiring device arranges each of a plurality of different signal lines as a partial wiring on an area dividing unit that divides a routable area of the semiconductor device into a plurality of areas and a wiring track in the divided routable area. Arranging means.

According to this arrangement / wiring apparatus, the number of wiring tracks used for signal line wiring can be reduced, so that a wiring area that can be used for wiring of other signal lines can be secured.
In the above arrangement / wiring apparatus, the arrangement means arranges two or more signal lines of the plurality of signal lines on the same wiring track, and a common shield line for the two or more signal lines. Place.

  With this configuration, it is possible to reduce the wiring area used for signal line wiring and the wiring area used for shield line wiring.

  According to this signal line arrangement method, the number of wiring tracks used for signal line wiring can be reduced, and the wiring area usable for wiring of other signal lines can be increased. Thereby, the freedom degree of the wiring of a signal line can be raised.

  Hereinafter, preferred embodiments of the present invention will be described. The signal line placement method according to the embodiment is realized, for example, as a program for a placement / wiring device (such as a CAD device) that performs placement / wiring of a semiconductor device.

  FIG. 1 is a flowchart of signal line arrangement / wiring processing according to the embodiment. First, a floor plan is executed to determine a schematic arrangement of circuit blocks having a large device area such as ROM and RAM (FIG. 1, S11). Coordinate data such as the arranged ROM and RAM is stored in a storage device such as a memory of the arrangement / wiring device.

  Next, the initial arrangement of cells such as flip-flops is determined (S12). The position data of the arranged cells is stored in a memory or the like. Next, in the ideal mode assuming that the clock skew (difference in arrival time of the clock signal) is zero, the timing of the data path signal between cells such as flip-flops is optimized (S13).

  Next, clock tree synthesis (CTS) is performed (S14). In this processing, a clock tree from the clock source to the leaf cell through the clock buffer and its lower clock buffer is generated.

  Next, the LSI chip is divided into a plurality of areas and divided into a plurality of areas including a clock buffer and a leaf cell (such as a flip-flop) (S15). The coordinate data of each area divided by this processing is stored in a memory or the like.

  The divided clock buffers in each area are moved to the horizontal row (ROW) where the clock skew is minimized (S17). The coordinate data of the clock buffer arranged by this processing is stored in a memory or the like.

  Next, wiring channel sharing is selected based on the arrangement of each clock buffer and leaf cell (S17). In this processing, multiple clock signal lines, which are the main wiring, can be placed in the same column in the horizontal direction based on the positions of multiple clock buffers and the positions of multiple leaf cells that receive clock signals from those clock buffers. It is determined whether or not.

  Next, trunk wirings (for example, clock signal lines) of a plurality of clock buffers for which wiring channels are determined to be sharable in step S17 are wired in the same column in the horizontal direction, and branch wiring from these trunk wirings to each leaf cell. (S18). Coordinate data indicating the positions of the main wiring and the branch wiring is stored in a memory or the like.

  Next, the clock skew of each leaf cell after branch wiring is calculated, and the wiring width and wiring length of the main wiring are adjusted so that the clock skew is optimal (S19). In this process, when the clock skew of the leaf cell is greater than or equal to a specified value, the wiring width of the main wiring is increased. Alternatively, the clock skew is reduced by extending the terminal wiring of the main wiring.

After adjusting the wiring width and wiring length of the basic wiring, the timing of the data signal of the leaf cell is optimized in the propagation mode (S20).
FIG. 2 is a block diagram of the placement / wiring apparatus 11 that executes the placement / wiring process described above.

The placement / wiring device 11 includes an initial placement unit 12, a clock tree generation unit 13, a region division unit 14, and a placement / wiring unit 15.
The initial placement unit 12 performs initial placement of a RAM, a CPU, and the like having a large device area, a clock buffer, and a cell. The clock tree generation unit 13 generates a clock tree from the clock source to the leaf cells.

  The area dividing unit 14 divides the LSI into areas of a predetermined size. The placement / wiring unit 15 places the clock buffers in a horizontal column where the delay of the clock signal does not deteriorate, and places a plurality of clock signal lines of the plurality of clock buffers as partial wirings on the same wiring track. Further, branch wiring from each clock signal line to each cell is performed.

3 and 4 are more detailed flowcharts of the clock signal line arrangement / wiring process described above.
A CTS process is executed to generate a clock tree (FIG. 3, S31).

  FIG. 5A is a diagram illustrating an example of a clock tree generated by the process of step S31. As shown in FIG. 5A, the clock signal generated by the clock source 31 passes through the first-stage clock buffer 32, the second-stage clock buffers 33 and 34, and the final-stage leaf clock buffer 37. It is supplied to the leaf cell 38. The leaf portion clock buffer 37 includes leaf portion clock buffers 35a, 35b, 36a, 36b, and the like.

Next, to divide the LSI chip into a plurality of areas including the leaf portion clock buffer, the LSI chip is divided into a set size (S32).
FIG. 5B is a diagram illustrating an area divided by the process of step S32. The LSI chip 41 is divided into a plurality of regions of a certain size.

FIG. 6 is a diagram showing a part of the divided area of the LSI chip 41. In the upper area 41a of FIG. 6, the clock buffer 33, the leaf portion clock buffers 35a and 35b to which the clock signal output from the clock buffer 33 is input, and the clock signals are supplied from the leaf portion clock buffers 35a and 35b. A plurality of leaf cells 38 are arranged. A clock signal is supplied to the clock buffer 33 from an upper clock buffer (not shown).

  Returning to FIG. 3, the horizontal row (ROW) in which the leaf clock buffer of each area is arranged is determined (S33). The horizontal column in which the leaf clock buffers are arranged is determined at a position where deterioration of the clock skew of the leaf clock buffers is minimized.

Next, the main wiring is temporarily arranged in the determined horizontal column, and the leaf clock buffer is arranged on the main wiring (FIG. 4, S34). In this process, a column in which the main wiring is arranged is determined.
Next, wiring channel sharing is selected in consideration of the position of the leaf clock buffer and the leaf cell (S35). In this process, it is determined whether or not the main wiring, which is the output signal line of the plurality of leaf clock buffers, can be placed on the same wiring track.

  Next, a leaf clock buffer is arranged at a position below the main wiring (S36). In this process, for example, when the main wiring such as a clock signal line is performed on the upper layer of the LSI substrate and the clock buffer is disposed on the lower layer, the leaf clock buffer is disposed below the main wiring.

Next, branch wiring (fishbone wiring) from the leaf clock buffer to each leaf cell is performed (S37).
Finally, the clock skew of each leaf cell after branch wiring is calculated, and it is determined whether or not the clock skew is greater than or equal to the constraint value. If the clock skew is greater than or equal to the constraint value, the clock skew is less than the constraint value. The wiring width of the wiring and the length to the wiring end are adjusted (S38).

Next, the above-described signal line arrangement method will be specifically described with reference to FIGS.
FIG. 7 is a diagram illustrating an arrangement example of the leaf clock buffers. The leaf portion clock buffers 35a and 35b in the upper region 41a and the leaf portion clock buffer 35c in the lower region 41b in FIG. 7 are connected to the same clock buffer 33, and each leaf portion clock buffer 35a, 35b, It is arranged at a position where the clock skew of 35c is minimized.

  The broken line 51 in the upper region 41a in FIG. 7 indicates that the position of the leaf clock buffers 35a and 35b and the position of the plurality of leaf cells 38 that receive clock signals from the leaf clock buffers 35a and 35b are 2 The position (horizontal column) of the main wiring (clock signal line) where the two buffers 35a and 35b can be arranged is shown.

  The broken line 52 in the lower region 41b in FIG. 7 is based on the positions of the leaf clock buffers 36a and 36b and the positions of the plurality of leaf cells 38 that receive clock signals from the leaf clock buffers 36a and 36b. The position of the main wiring (horizontal column) where two buffers 36a and 36b can be arranged is shown.

FIG. 8 is a diagram showing a state when the leaf clock buffer is moved to the same column in the horizontal direction or a neighboring column by the process of step 34 in FIG.
The core wiring (clock signal line) of the leaf clock buffer 35a and the leaf clock buffer 35b in the upper region 41a in FIG. 8 may be arranged in the same horizontal column (position indicated by the broken line 51 in FIG. 8). Therefore, the leaf clock buffers 35a and 35b are arranged at the position of the broken line 51.

The core wiring of the leaf clock buffer 36a and the leaf clock buffer 36b in the lower area 41b in FIG. 8 can be arranged in the same horizontal column (position indicated by the broken line 52 in FIG. 8). The leaf clock buffers 36a and 36b are arranged at the position of the broken line 52. At this time, the basic wiring of the leaf clock buffer 35c cannot be arranged in the same column as the basic wiring of the leaf clock buffer 36b, and is therefore arranged in a column in the vicinity thereof.

  FIGS. 9A and 9B show examples of arrangement of clock signal lines and shield lines arranged by the process of step S35 of FIG. FIG. 9A shows an arrangement example in which the wiring track of the clock signal line can be shared, and FIG. 9B shows an arrangement example in which only the wiring track of the shield line can be shared.

  In the arrangement example of FIG. 9A, a clock signal line 61a that supplies the output of the leaf clock buffer 35a to each leaf cell (flip-flop) 38, and a clock signal that supplies the output of the leaf clock buffer 35b to each leaf cell 38. The line 61b is arranged on the same wiring track (wiring path in the same column in the horizontal direction). Further, two shield lines 62a and 62b sandwiching the clock signal lines 61a and 61b are arranged in common.

  In the example of FIG. 9A, the clock signal line 61a and the clock signal line 61b are arranged as partial wirings of the same wiring track, and further, by sharing the shield wiring, the wiring track used for wiring of the clock signal line. And the number of wiring tracks used for the wiring of the shield line can be halved.

  In the arrangement example of FIG. 9B, the clock signal line 63a that supplies the output of the leaf portion clock buffer 36a to each leaf cell 38 and the clock signal line 63b that supplies the output of the leaf portion clock buffer 36b to each leaf cell 38 are the same. Is placed on the wiring track. Further, common shield lines 64a and 64b are arranged so as to sandwich the clock signal lines 63a and 63b. The shield lines 64a and 64b are for suppressing crosstalk of the clock signal.

  The clock signal line 65 that supplies the output of the leaf clock buffer 35c to each leaf cell 38 is disposed on an adjacent wiring track with a space (double space) twice the minimum wiring pitch from the clock signal line 63b. One shield line of the clock signal line 65 is shared with the shield line 64a of the clock signal line 64b. Note that wiring the signal lines with an interval of twice the minimum wiring pitch is called double space wiring.

  In the example of FIG. 9B, by arranging the clock signal line 63a and the clock signal line 63b in the same wiring track, the number of wiring tracks used for the wiring of the clock signal lines 63a and 63b is halved. Can do. Furthermore, by sharing the shield line 64a between the clock signal lines 63a and 63b and the clock signal line 65, it is possible to reduce the number of wiring tracks used for wiring of the shield line.

  As described above, by disposing different clock signal lines 61a and 61b as partial wirings on the same wiring track, the number of wiring tracks used for clock signal line wiring can be reduced. Furthermore, by sharing the shield line, it is possible to reduce the number of wiring tracks necessary for wiring the shield line. As a result, a wiring area that can be used for wiring of a clock signal or other signal lines is widened, so that the degree of freedom of wiring of signal lines is increased.

Next, FIGS. 10A and 10B are diagrams showing the state in which the clock signal lines are arranged and branch wirings to the leaf cells 38 are performed by the processing in steps S36 and S37 in FIG.
FIG. 10A shows a state where the clock signal line and the shield line are wired. The clock signal line 61a on the output side of the leaf clock buffer 35a and the clock signal line 61b on the output side of the leaf clock buffer 35b are arranged as partial wirings on the same wiring track. In addition, a common shield line 64a is used for the clock signal line 63a, the clock signal line 63b, and the clock signal line 65.

FIG. 10B shows a state in which branch wiring from the clock signal line to each leaf cell 38 is performed.
Branch lines 71a, 71b,... From the clock signal line 61a to the leaf cells 38, and branch lines 72a, 72b,. Similarly, branch wiring 73a from the clock signal line 63a to each leaf cell 38, branch wiring 74a from the clock signal line 63b to each leaf cell 38, and branch wiring 75a from the clock signal line 65 to each leaf cell 38 are provided. Do.

  After branch wiring from the clock signal line to each leaf cell 38, the clock skew of each leaf cell 38 is calculated, and when the clock skew does not satisfy the constraint condition, the wiring width of the clock signal line or the length to the wiring end is calculated. Adjust to meet the constraints.

  10A and 10B, the clock signal lines 61a and 61b, the shield lines 62a and 62b, the leaf clock buffers 35a and 35b, and the leaf cell 38 are shown on the same plane. However, the clock signal line and shield line, and the clock buffer and leaf cell 38 are provided in different layers of the multilayer substrate, and the output terminal of the leaf clock buffer and the clock signal line are electrically connected by vias or the like.

FIG. 11 shows an example in which the line widths of the clock signal lines 63b and 61b are increased by the process of step S38 of FIG.
After branch wiring from the clock signal line to each leaf cell 38, when the clock skew of each leaf cell 38 is equal to or greater than the constraint value, for example, the clock signal lines 61b and 63b on the output side of the leaf clock buffers 35b and 36b are The line width is changed to wide wirings 61b 'and 63b. Alternatively, the clock skew is adjusted by adjusting the length to the end of the clock signal line.

FIG. 12 is a comparison diagram of the number of wiring tracks between the conventional signal line arrangement method and the signal line arrangement method of the embodiment.
In the conventional signal line arrangement method, as shown in FIG. 12, horizontal wiring necessary for wiring the clock signal line 81a on the output side of the leaf portion clock buffer 35a and the shield lines 82a and 82b on both sides thereof is provided. The number of tracks is “3”. Further, the number of horizontal wiring tracks necessary for wiring the clock signal line 81b on the output side of the leaf clock buffer 35b and the shield lines 83a and 83b is "3".

  That is, in the conventional signal line arrangement method, six wiring tracks are required to wire the two clock signal lines 81a and 81b and the four shield lines 82a, 82b, 83a, and 83b. .

  On the other hand, in the signal line arrangement method according to the embodiment, the clock signal line 61a and the clock signal line 61b are arranged on the same wiring track, and two shield lines are shared, so that the necessary number of wiring tracks is obtained. Becomes “3”.

Therefore, in this case, the number of wiring tracks necessary for wiring the two clock signal lines 61a and 61b and each shield line can be reduced to ½.
Similarly, in the conventional signal line arrangement method, the number of wiring tracks necessary for wiring the clock signal lines 84a, 84b, 81c of the leaf portion clock buffers 36a, 36b, 35c and the respective shield lines is “9”. "

  On the other hand, in the signal line wiring method of the embodiment, the clock signal line 63a of the leaf clock buffer 36a and the clock signal line 63b of the leaf clock buffer 36b are arranged in the same column in the horizontal direction. The clock signal lines 65 are arranged in the two adjacent columns. Further, the shield line 64a is shared by the clock signal line 65 and the clock signal lines 63a and 63b. As a result, the number of wiring tracks necessary for wiring the clock signal line and the shield line becomes “5”.

Therefore, in this case, the necessary number of wiring tracks for the clock signal line and the shield line can be reduced by “4”.
According to the embodiment described above, by arranging a plurality of clock signal lines as partial wirings on the same wiring track, the number of wiring tracks used for clock signal line wiring can be reduced. Further, by sharing the shield wiring with the adjacent clock signal lines, the number of wiring tracks used for the shield wiring can be reduced. This increases the wiring area that can be used for the wiring of the clock signal line or other signal lines, so that the degree of freedom of wiring of the signal lines can be increased.

In the above-described embodiment, the case where a plurality of clock signal lines are arranged on the same wiring track has been described, but the present invention can also be applied to the case where other signal lines other than the clock signal lines are arranged. Further, the present invention can also be applied when no shield wiring is used.
(Supplementary note 1) A signal line arrangement method for a semiconductor device, in which each of a plurality of different signal lines is arranged as a partial wiring on a wiring track in a routable area of the semiconductor device. (1)
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein two or more signal lines of the plurality of signal lines are arranged on the same wiring track, and a common shield line is arranged for the two or more signal lines. Signal line placement method. (2)
(Supplementary Note 3) Two or more signal lines of the plurality of signal lines are arranged in adjacent wiring tracks, and a shield line common to the two or more signal lines arranged in the adjacent wiring tracks is provided. The signal line arrangement method of the semiconductor device according to attachment 1, wherein the signal line is arranged. (3)
(Supplementary note 4) When the clock skew of a plurality of cells connected to the plurality of signal lines is equal to or greater than a reference value, the line width of the corresponding signal line is adjusted so that the clock skew is less than the reference value. Or a signal line arranging method of the semiconductor device according to 3. (4)
(Supplementary note 5) The signal line arrangement method for a semiconductor device according to supplementary note 1, 2 or 3, wherein the plurality of signal lines are a plurality of clock signal lines for supplying a clock signal to a plurality of cells.
(Appendix 6) When a double space wiring arranged with a certain interval from another signal line is applied to the signal line, a wiring prohibited track for two or more signal lines is arranged in the vicinity of the wiring track. 4. The signal line arrangement method according to appendix 1, 2 or 3, wherein
(Supplementary note 7) Area dividing means for dividing the routable area of the semiconductor device into a plurality of areas;
A placement / wiring apparatus comprising placement means for placing each of a plurality of different signal lines as a partial wiring on a wiring track in a divided routable area. (5)
(Additional remark 8) The said arrangement | positioning means arrange | positions two or more signal lines of these signal lines on the same wiring track, and arranges a common shield line with respect to the said two or more signal lines. 7. The arrangement / wiring device according to 7. (6)
(Additional remark 9) The said arrangement | positioning means arrange | positions two or more signal lines of said several signal lines to an adjacent wiring track, and with respect to two or more signal lines arrange | positioned at an adjacent wiring track 8. The placement / wiring device according to appendix 7, wherein a common shield line is placed.
(Supplementary Note 10) The plurality of signal lines are a plurality of clock signal lines for supplying a clock signal to a plurality of cells, and two or more of the plurality of clock signal lines are connected to adjacent wiring tracks. The placement / wiring apparatus according to appendix 7, 8 or 9, wherein a common shield line is placed for the two or more clock signals placed and placed on adjacent wiring tracks.
(Supplementary Note 11) A computer-executable program.

A signal line arrangement program for a semiconductor device, comprising a step of arranging each of a plurality of different signal lines as a partial wiring on a wiring track in a routable area of the semiconductor device.
(Supplementary note 12) The semiconductor device according to supplementary note 11, wherein two or more signal lines of the plurality of signal lines are arranged on the same wiring track, and a common shield line is arranged for the two or more signal lines. Signal line placement program.
(Supplementary note 13) Two or more signal lines of the plurality of signal lines are arranged in adjacent wiring tracks, and a shield line common to two or more signal lines arranged in adjacent wiring tracks is provided. 12. A signal line arrangement program for a semiconductor device according to appendix 11, which is arranged.

3 is a flowchart of clock signal line arrangement / wiring processing according to the embodiment; It is a block diagram of the arrangement / wiring device of the embodiment. It is a detailed flowchart (1) of the arrangement | positioning and wiring process of a clock signal line. It is a detailed flowchart (2) of arrangement | positioning / wiring process of a clock signal line. It is a figure which shows the area | region which divided | segmented the clock tree and LSI. It is a figure which shows a part of divided | segmented area | region. It is a figure which shows the example of arrangement | positioning of a leaf part clock buffer. It is a figure which shows the state which moved the leaf part clock buffer to the same or the vicinity row | line | column. It is a figure which shows the example of arrangement | positioning when the wiring track of a clock signal line can be shared, and the wiring track of a shield line can be shared. It is a figure which shows the wiring and branch wiring of a clock signal line. It is a figure which shows the example which made line width of a clock signal line wide. It is a comparison figure of the number of wiring tracks of the conventional signal line arrangement method and the signal line arrangement method of the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Arrangement / wiring device 12 Initial arrangement unit 13 Clock tree generation unit 14 Area division unit 15 Arrangement / wiring unit 35a-35c Leaf unit clock buffer 36a, 36b Leaf unit clock buffer 61a, 61b Clock signal line 64a, 64b Shield line 38 Leaf cell

Claims (6)

  A signal line placement method for a semiconductor device, wherein each of a plurality of different signal lines is placed as a partial wire on a wiring track in a routable area of the semiconductor device.   2. The signal line of a semiconductor device according to claim 1, wherein two or more signal lines of the plurality of signal lines are arranged on the same wiring track, and a common shield line is arranged for the two or more signal lines. Placement method.   2. Two or more signal lines of the plurality of signal lines are arranged in adjacent wiring tracks, and a common shield line is arranged for two or more signal lines arranged in adjacent wiring tracks. 2. A signal line arrangement method for a semiconductor device according to 1.   4. The line width of a corresponding signal line is adjusted so that the clock skew is less than a reference value when a clock skew of a plurality of cells connected to the plurality of signal lines is equal to or greater than a reference value. Signal line arrangement method of the semiconductor device. Area dividing means for dividing the routable area of the semiconductor device into a plurality of areas;
A placement / wiring apparatus comprising placement means for placing each of a plurality of different signal lines as a partial wiring on a wiring track in a divided routable area.   6. The arrangement unit according to claim 5, wherein two or more signal lines of the plurality of signal lines are arranged on the same wiring track, and a common shield line is arranged for the two or more signal lines. Placement and wiring equipment.

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