JP2003280762A - I/o block, source synchronous macro and information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a source synchronous macro having various bit widths by combining an I/O block for data and an I/O block for a source clock. <P>SOLUTION: This I/O block 21 for the source clock outputs a source clock signal from a channel area for distribution wiring by a 1st driver 2110, a 1st driver 2111, and a 1st driver 2112. The I/O block 11 for the data to the I/O block 20 for the data respectively receive the source clock signal by a 2nd driver 1120 to a 2nd driver 2020, and distribute the signal inside the block. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an I / O block,
The present invention relates to a source synchronous macro and an information processing apparatus, and more particularly to an I / O block, a source synchronous macro, and an information processing apparatus that implement a source clock distribution with high accuracy.

[0002]

2. Description of the Related Art Source synchronous transfer systems are
Used for high-speed data transfer between computer LSIs. The source-synchronous transfer method is a sending-side LSI that sends a data signal and a source clock signal (strobe signal).
From the same wiring board and cable, the receiving side LSI samples data with the transmitted source clock signal, and then synchronizes with the receiving side clock.

Therefore, since the delay variation of the LSI, the delay variation of the wiring board, the cable, the connector, etc. can be taken into consideration by the relative delay difference, the method is more effective than the synchronous transfer method at the time of high speed transfer. From the viewpoint of reducing delay variation, it is ideal to send the source clock signal and the data signal on a one-to-one basis. However, if this is done, the number of LSI pins will double, so in general the source clock signal Several data signals are collectively transferred to one line.

For example, "Japanese Patent Laid-Open No. 2000-347993"
The invention described in Japanese Patent Publication No. JP-A-2003-18732 relates to a source synchronous transfer system.

FIG. 14 is a block diagram showing an example of the source synchronous transfer system of the above publication.

Referring to FIG. 14, the F / F 43 holds one bit of data in synchronization with the clock on the sending side, and
44 generates a source clock from the sender clock.
The write address generation circuit 49 generates a write address signal from the source clock, the write selector 48 selects 1 bit of data according to the write address signal,
The data holding circuit 50 samples 1 bit of data with a source clock. The read address generation circuit 53 inputs the synchronization signal from the synchronization circuit 51 and generates a read address signal synchronized with the receiving side clock, and the read selector 52 outputs 1 bit of the data of the data holding circuit 50 according to the read address signal. And the F / F 54 samples and outputs 1 bit of data by the receiving clock.

As described above, in the source synchronous transfer system, in order to realize high-speed transfer by reducing the delay variation, the clock distribution delay and the source clock distribution delay in the source synchronous / function macro are made the same as much as possible. Since it is necessary, the layout is generally designed in macro units (hard macros) having the function.

The invention described in Japanese Patent Application Laid-Open No. 11-119854 discloses a group consisting of a dividing section for dividing a plurality of macros at the Nth stage arranged in an LSI into groups and a macro at the Nth stage. After generating, for each group,
It is a clock path generation device having a generation unit that generates a macro in the (N-1) th stage that supplies a clock signal to macros in the group.

[0009]

The problem of the above-mentioned conventional technique is that the number of man-hours for macro design and the libraries for various designs increase.

The reason for this is that the data bit widths used for transfer between LSIs are not uniform and there are many types. Therefore, when source synchronous hard macros corresponding to these are created, as many source synchronous hard macros as those are generated. This is because it is necessary to create a hard macro.

The second problem is that physical verification such as DRC and LVS also needs to be performed in macro units.

The reason is that the layout is done in macro units.

An object of the present invention is to realize a source synchronous macro having various bit widths by designing a data I / O block and a source clock I / O block and combining them.

[0014]

The first source clock I / O block of the present invention is equipped with at least one 1st driver for distributing a clock signal to the outside, and
A distribution wiring channel region including an output terminal for distributing the clock signal of the st driver is provided.

The first data I / O block of the present invention comprises one or more 2n for internally distributing a clock signal.
The present invention is characterized by including a d-driver and a distribution wiring channel region including an input terminal of the second driver for receiving a clock signal from the first driver.

The first source-synchronous macro of the present invention comprises one or more 1s for distributing a clock signal to the outside.
An I / O block for a source clock, which is equipped with an st driver and has the channel region for distribution wiring including an output terminal for distributing a clock signal of the 1st driver, and one or more internal I / O blocks for distributing the clock signal. Two
and a data I / O block having a distribution wiring channel region including an input terminal of the 2nd driver for receiving a clock signal from the 1st driver.

The second source clock I / O block of the present invention is equipped with one or more 1st drivers for distributing a clock signal to the outside and has an output terminal for distributing the clock signal of the 1st driver. It is characterized in that it includes a channel region for distribution wiring for wiring in a straight line with the 2nd driver including.

The second data I / O block of the present invention is one or more 2n for internally distributing a clock signal.
A d-driver is provided, and a distribution wiring channel region for wiring in a straight line with the 1st driver including an input terminal of the 2nd driver for receiving a clock signal from the 1st driver is provided.

The second source synchronous macro of the present invention comprises one or more 1's for distributing a clock signal to the outside.
An I / O block for a source clock, which has a st driver and a distribution wiring channel region for wiring in a straight line with a 2nd driver including an output terminal for distributing a clock signal of the 1st driver, and a clock signal inside Is provided with one or more 2nd drivers for distributing, and a distribution wiring channel region for linearly wiring with the 1st driver including an input terminal of the 2nd driver for receiving a clock signal from the 1st driver is provided. And a data I / O block.

A first information processing apparatus according to the present invention is provided with at least one 1st driver for distributing a clock signal to the outside, and for distribution wiring including an output terminal for distributing the clock signal of the 1st driver. It is characterized by including an I / O block for source clock having a channel region.

A second information processing apparatus of the present invention has therein one or more 2nd drivers for distributing a clock signal therein and includes an input terminal of the 2nd driver for receiving a clock signal from a 1st driver. It is characterized in that it is configured to include a data I / O block having a distribution wiring channel region.

A third information processing apparatus of the present invention has one or more 1st drivers for distributing a clock signal externally mounted, and the distribution wiring including an output terminal for distributing a clock signal of the 1st driver. I / O block for a source clock having a channel region for internal use, and one or more 2nd drivers for distributing a clock signal inside, and an input terminal of the 2nd driver for receiving a clock signal from the 1st driver. It is characterized by including a source synchronous macro having a data I / O block having a distribution wiring channel region including the same.

A fourth information processing apparatus of the present invention comprises a 2nd driver including one or more 1st drivers for distributing a clock signal to the outside and including an output terminal for distributing the clock signal of the 1st driver. It is characterized in that it is configured to include a source clock I / O block having a distribution wiring channel region for wiring in a straight line.

A fifth information processing apparatus of the present invention has one or more 2nd drivers for distributing a clock signal therein and includes an input terminal of the 2nd driver for receiving a clock signal from a 1st driver. It is characterized in that it is configured to include a data I / O block having a distribution wiring channel region for wiring in a straight line with the 1st driver.

A sixth information processing apparatus of the present invention comprises a 2nd driver including one or more 1st drivers for distributing a clock signal to the outside and including an output terminal for distributing the clock signal of the 1st driver. The source clock I / O block having a distribution wiring channel region for wiring in a straight line and one or more 2nd drivers for distributing a clock signal are mounted inside the block.
a source synchronous macro having the 1st driver including an input terminal of the 2nd driver for receiving a clock signal from the st driver and a data I / O block having a distribution wiring channel region for wiring in a straight line. It is characterized by being composed of.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

In the embodiment of the present invention, the I / O macro for the source synchronous data transfer method, which is one of the high-speed data transfer methods between LSIs, is not used in the layout (hard macro) in macro units having the function. Instead, the present invention relates to a soft macro in which layout is performed for each I / O single block, and these are collected and summarized as a functional block.

FIG. 1 is a configuration diagram showing a configuration of an embodiment of the present invention.

Referring to FIG. 1, the embodiment of the present invention is a source synchronous soft macro 120.

For example, the source synchronous soft macro 120 is a balanced signal in which the data is 10 bits and the source clock is positive / negative (True / Compliment), and the I / O blocks are vertically stacked in three stages. The source synchronous soft macro 120 includes a data I / O block 11, a data I / O block 12, and a data I / O block 12.
/ O block 13, data I / O block 14, data I / O block 15, data I / O block 1
6, data I / O block 17, data I / O block 18, data I / O block 19, data I / O
It is composed of an O block 20 and a source clock I / O block 21.

The first stage is a data I / O block 11,
The data I / O block 14, the data I / O block 16, and the data I / O block 18 are provided. The second stage is the data I / O block 12, the source clock I / O block 21, and the data. The third stage comprises a data I / O block 19, a data I / O block 13, a data I / O block 15, and a data I / O block 1.
7 and the data I / O block 20.

The intra-macro distribution signals (source macro signal, system clock signal, write address signal, read address signal, etc. intra-macro distribution signal) from the source clock I / O block 21 are respectively supplied to the data I / O block 11. ~ Is supplied to the data I / O block 20.

In order to suppress delay variation, it is necessary to make the distribution delay time of the source clock signal and the system clock signal of the intra-macro distribution signal as equal as possible. Therefore, the source clock I / O block 21
Is placed near the center of the source synchronous macro,
Around the data I / O block 11 to data I / O
The O block 20 is arranged.

The source clock I / O block 21 includes a 1st driver 2110, 1s for intra-macro distribution.
A t driver 2111, a 1st driver 2112 are installed. In addition, the data I / O block 11 to the data I / O block 20 each have a second driver 1120 that distributes the signals distributed from the 1st driver 2110, the 1st driver 2111, and the 1st driver 2112 to the I / O block. The 2nd driver 1220, the 2nd driver 1320, the 2nd driver 1420, the 2nd driver 1520, the 2nd driver 1620, the 2nd driver 1720, the 2nd driver 1820, the 2nd driver 1920, and the 2nd driver 2020 are mounted.

Further, the source clock I / O block 2
The 1st 2nd driver 212 distributes the signal distributed from the 1st driver 2112 to the I / O block.
The 0, 2nd driver 2121 is installed.

In the macro wiring, since the distribution wiring channel region 300, the distribution wiring channel region 301, and the distribution wiring channel region 302 provided at the end of each I / O block are wired in a straight line, each macro wiring Match the coordinates of the input and output terminals. Further, it is desirable to shield the periphery of this wiring so as not to be affected by other wiring.

It is desirable that the source clock signal distribution and the system clock distribution signal are distributed with the same delay value for both the macro having a small number of data bits and the macro having a large number of data bits. A plurality of dummy loads for load adjustment are also mounted on the second driver. The distribution line delay is adjusted by changing the number of dummy loads of the driving capability 2nd driver of the 1st driver.

This combination is determined by using circuit simulation such as SPICE and the information is stored as a soft macro library. The distribution wiring in the macro is automatically wired by the CAD tool based on this library.

Source synchronous soft macro 120
As a combination of blocks, transistors, wirings, etc. are physically manufactured as a whole. Thus, the signal is not split at the ends of each block, but across the blocks.

Next, the operation of the embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is an explanatory diagram showing the concept of signal distribution in the macro.

FIG. 3 is an explanatory diagram showing the concept of signal distribution in the macro.

FIG. 4 is a circuit diagram showing the configuration of the dummy load.

Referring to FIG. 2, the source clock I /
The drive capacity of the O block 21 is twice (x2) or three times (x) the standard for the source clock and the system clock.
3) 4x (x4) equivalent 1st driver is installed, and 2nd driver including dummy is 4x
Install 2 Note that FIG. 2 shows an example in which the number of data bits is relatively small.
A double load is used and three dummy loads are added. Data I / O block 22, data I / O
The signal is also connected to the dummy second driver of the block 23.

Referring to FIG. 3, this is an example in which the number of data bits is large, a 1st driver having a drive capacity equivalent to four times the standard is used, and no signal is connected to the dummy load.

It is desirable that the input capacitance of the 2nd driver is as small as possible in consideration of suppressing variations. Further, the dummy load has the configuration shown in FIG. 4 so that a through current does not flow even if the input is opened.

Next, the connection in the distribution wiring channel region between the drivers will be described.

FIG. 5 shows the 1st driver output section, 2nd
It is explanatory drawing which shows the connection of a driver input part.

Referring to FIG. 5, the source clock I /
The 1st driver (× 2) of the O block 21 is connected to the four 2nd drivers (three dummy loads) of the data I / O block 22 by wiring in the distribution wiring channel region. Circled circles indicate terminals. A source clock I / O block and a data I / O block are wired from this terminal via a VIA (via) hole, for example, in an upper layer distribution wiring channel region.

The driving ability can be changed by changing the connection position of the 1st driver output terminal. Also,
The load can be adjusted by changing the number of connections of the 2nd driver input terminal.

FIG. 6 is an explanatory diagram showing the structure of the distribution wiring channel region.

Referring to FIG. 6, the distribution wiring channel area is composed of four areas of source clock distribution, read address distribution, write address distribution, and system clock distribution, which are separated by shield wiring. It is not inevitable to include the read address distribution and the write address distribution in the distribution wiring channel region.

The wiring in the macro reduces wiring resistance and capacitance,
In order to simplify automatic wiring by a CAD tool, it is desirable to wire in a straight line. In order to realize this, it is desirable to arrange the input / output terminals for wiring in each macro as shown in FIG. FIG. 6 shows an example in which both the read address and the write address are 4 bits.

Next, the layout of the data I / O block and the source clock I / O block will be described.

FIG. 7 is an explanatory diagram showing the layout of the data I / O block.

FIG. 8 is an explanatory diagram showing the layout of the source clock I / O block.

Referring to FIG. 7, the data I / O block may include, for example, a source clock 2nd driver unit and a system clock 2n in the distribution wiring channel region.
The d driver section is arranged and the 1st driver section of the source clock I / O block is removed in a square shape.

Referring to FIG. 8, the source clock I /
The O block is, for example, in the distribution wiring channel region,
2nd driver part for source clock, 2nd driver part for system clock, 1st driver part for source clock, 1st driver part for system clock are arranged, and further, in a protruding form, 1st driver part for source clock, 1st driver for system clock Take the shape of arranging parts.

Next, a combination of the data I / O block and the source clock I / O block will be described.

FIG. 9 is an explanatory diagram showing the layout of the source synchronous soft macro 120.

Referring to FIG. 9, the source synchronous
The soft macro 120 is configured by combining a data I / O block and a source clock I / O block. That is, the data I / O block 11, the data I / O block 12, the data I / O block 13, the data I / O block 14, the data I / O block 1
5, data I / O block 16, data I / O block 17, data I / O block 18, data I / O
It comprises an O block 19, a data I / O block 20, and a source clock I / O block 21.

In FIGS. 1 and 9, the I / O blocks constitute the source synchronous soft macro as vertically stacked three stages, but one or two stages may be used. Further, the source clock is a positive / negative (True / Compliance) balanced signal, but a single signal may be used if source synchronous transfer is possible.

In FIG. 2 and FIG. 3, the first driver is provided with three types of drive capacity equivalent to double, triple and quadruple the standard, and the number of dummy loads of the second driver is three. Since it is necessary to select the optimum driving capability and the optimum number of dummy loads depending on the configuration of the eggplant soft macro, there is no need to be restricted to the configuration shown in FIGS.

The terminal positions in FIG. 6 are also arbitrary. The layouts of the I / O blocks in FIGS. 7 and 8 are also arbitrary as long as the design method can be performed.

Next, examples of various layouts will be described with reference to the drawings.

FIG. 10 is an explanatory diagram showing an example of the layout of the source synchronous soft macro.

FIG. 11 is an explanatory diagram showing an example of the layout of the source synchronous soft macro.

FIG. 12 is an explanatory diagram showing an example of the layout of the source synchronous soft macro.

FIG. 13 is an explanatory diagram showing an example of the layout of the source synchronous soft macro.

FIG. 10 shows a balanced signal in which the data is 10 bits and the source clock is True / Comp.
The block is an example of a source-synchronous soft macro 120 with three layers stacked vertically. In FIG. 11, the data is 20 bits and the source clock is True / Compliment.
Is a balance signal, and the I / O block is an example of a source-synchronous soft macro 121 with three stages stacked vertically. Figure 1
0 data I / O block 11 to data I / O block 20, and data I / O block 11 to data I / O block 20 and data I / O block 3 in FIG.
1 to 40 are all the same.

Similarly, the source clock I / O shown in FIG.
The block 21 and the source clock I / O block 21 of FIG. 11 are also the same.

In the examples of FIGS. 12 and 13, the data is 2
0 bit, source clock is True / Complim
With the balance signal of ent, the I / O blocks are the source-synchronous soft macro 122 and the source-synchronous soft macro 123 having the same functional configuration as that of FIG. The difference between FIGS. 11 to 13 is only the macro layout shape.

An information processing device in which a logic circuit is configured by the source synchronous soft macro described above is possible.

[0074]

The first effect of the present invention is that it can be created more easily than designing a source synchronous macro having various bit configurations as a hard macro laid out in macro units.

The reason is that when designing with a hard macro structure, it is necessary to create as many source synchronous hard macros as the bit structure changes, but when designing with a soft macro structure, I / O for data is used. This is because it is only necessary to design O and the I / O for the source clock and then combine them.

The second effect is that the LSI accommodation property is improved.

The reason is that the macro shape can be made flexible.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing the concept of signal distribution in a macro.

FIG. 3 is an explanatory diagram showing the concept of signal distribution in a macro.

FIG. 4 is a circuit diagram showing a configuration of a dummy load.

FIG. 5 is an explanatory diagram showing a connection between a 1st driver output section and a 2nd driver input section.

FIG. 6 is an explanatory diagram showing a configuration of a distribution wiring channel region.

FIG. 7 is an explanatory diagram showing a layout of a data I / O block.

FIG. 8 is an explanatory diagram showing a layout of a source clock I / O block.

9 is an explanatory diagram showing a layout of a source synchronous soft macro 120. FIG.

FIG. 10 is an explanatory diagram showing an example of a layout of a source synchronous soft macro.

FIG. 11 is an explanatory diagram showing an example of a layout of a source synchronous soft macro.

FIG. 12 is an explanatory diagram showing an example of a layout of a source synchronous soft macro.

FIG. 13 is an explanatory diagram showing an example of a layout of a source synchronous soft macro.

FIG. 14 is a block diagram showing an example of a source synchronous transfer system.

[Explanation of symbols]

11 Data I / O block 12 Data I / O block 13 Data I / O block 14 Data I / O block 15 Data I / O block 16 data I / O block 17 Data I / O block 18 Data I / O block 19 Data I / O block 20 I / O block for data 21 I / O block for source clock 22 Data I / O block 23 Data I / O block 31-40 I / O block for data 43 F / F 44 F / F 48 light selector 49 write address generation circuit 50 data holding circuit 51 Synchronization circuit 52 lead selector 53 Read address generation circuit 54 F / F 120 Source Synchronous Soft Macro 121 Source Synchronous Soft Macro 122 Source Synchronous Soft Macro 123 Source Synchronous Soft Macro 300 Distribution wiring channel area 301 Distribution wiring channel area 302 Distribution wiring channel area 1120 2nd driver 1220 2nd driver 1320 2nd driver 1420 2nd driver 1520 2nd driver 1620 2nd driver 1720 2nd driver 1820 2nd driver 1920 2nd driver 2020 2nd driver 2110 1st driver 2111 1st driver 2112 1st driver 2120 2nd driver 2121 2nd driver

Claims (12)

[Claims] 1. A device for distributing a clock signal to the outside.
An I / O block for source clock, comprising the above 1st driver and a distribution wiring channel region including an output terminal for distributing a clock signal of the 1st driver. 2. A distribution wiring channel region including one or more 2nd drivers for distributing a clock signal therein and including an input terminal of the 2nd driver for receiving a clock signal from a 1st driver. Characteristic data I / O block. 3. A device for distributing a clock signal to the outside.
The source clock I / O equipped with the above 1st driver and provided with the distribution wiring channel region including the output terminal for distributing the clock signal of the 1st driver
O block and 1 for distributing clock signal inside
A data I / O block including the above-mentioned 2nd driver and having a distribution wiring channel region including an input terminal of the 2nd driver for receiving a clock signal from the 1st driver. Synchronous macro. 4. A device for distributing a clock signal to the outside.
2n including the above 1st driver and including an output terminal for distributing the clock signal of the 1st driver
I / D for source clock, which is provided with a channel region for distribution wiring for wiring in a straight line with the d driver
O block. 5. A device for internally distributing a clock signal.
The above-mentioned 2nd driver is mounted, and a distribution wiring channel region for wiring in a straight line with the 1st driver including an input terminal of the 2nd driver for receiving a clock signal from the 1st driver is provided. / O block. 6. A device for distributing a clock signal to the outside.
2n including the above 1st driver and including an output terminal for distributing the clock signal of the 1st driver
A clock signal from the 1st driver, which is equipped with a source clock I / O block having a distribution wiring channel region for wiring in a straight line with the d driver and one or more 2nd drivers for internally distributing the clock signal. A source synchronous macro, comprising: the 1st driver including an input terminal of the 2nd driver for receiving the data; and a data I / O block having a distribution wiring channel region for wiring in a straight line. 7. A device for distributing a clock signal to the outside.
Information processing characterized by including the above 1st driver and including a source clock I / O block having a distribution wiring channel region including an output terminal for distributing a clock signal of the 1st driver apparatus. 8. For data, wherein one or more 2nd drivers for distributing a clock signal are mounted inside, and a distribution wiring channel region including an input terminal of the 2nd driver for receiving a clock signal from a 1st driver is provided. An information processing apparatus comprising an I / O block. 9. A device for distributing a clock signal to the outside.
The source clock I / O equipped with the above 1st driver and provided with the distribution wiring channel region including the output terminal for distributing the clock signal of the 1st driver
O block and 1 for distributing clock signal inside
A source synchronous macro including the above-mentioned 2nd driver and a data I / O block having a channel region for distribution wiring including an input terminal of the 2nd driver for receiving a clock signal from the 1st driver is included. An information processing device comprising: 10. An externally mounted one or more 1st drivers for distributing a clock signal and including an output terminal for distributing a clock signal of the 1st driver 2
An information processing apparatus comprising: an I / O block for a source clock having a distribution wiring channel region for wiring in a straight line with an nd driver. 11. A wiring for linearly connecting to the 1st driver including an input terminal of the 2nd driver for receiving a clock signal from the 1st driver, wherein one or more 2nd drivers for internally distributing the clock signal are mounted. Data I with distribution wiring channel region
An information processing apparatus comprising an I / O block. 12. A device including one or more 1st drivers for distributing a clock signal to the outside and including an output terminal for distributing the clock signal of the 1st driver.
a source clock I / O block having a distribution wiring channel region for wiring in a straight line with an nd driver;
A distribution wiring channel for internally wiring one or more 2nd drivers for distributing a clock signal, and including the input terminal of the 2nd driver for receiving a clock signal from the 1st driver, for wiring in a straight line with the 1st driver An information processing apparatus comprising a source synchronous macro having a data I / O block having an area.