JP2000031285A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce clock screw by employing a low resistance substance in a clock signal line connecting a signal source unit and a logic circuit unit. SOLUTION: Between a signal source unit, i.e., a clock signal source cell 101, and a logic circuit unit, i.e., a flip-flop cell 103, every plurality of stages of clock buffer cell 102 are connected through a clock signal line 104 of low resistance substance. Delay of bus is determined for each system by calculating delay for each net of the clock signal line 104 and a screw occurring for other bus is calculated. The line length is made uniform so that the screw is minimized and the number of drive is made uniform. According to the method, absolute clock screw can be reduced without modifying the route.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device provided with a method for reducing clock skew.

[0002]

2. Description of the Related Art In general, a semiconductor device is constituted by circuit modules having various functions, and these modules are provided with one or more clock signals, and a logic unit such as a flip-flop in the circuit module has
It operates in synchronization with the clock signal.

A circuit arrangement having a tree structure in which clock signals are distributed and connected to a plurality of flip-flops in the circuit module will be described with reference to FIG.

Here, when the clock signal source cell 401 drives the flip-flop cell 403, when there are a large number of flip-flop cells to be driven, the driving capability of the clock signal source cell becomes insufficient, or the wiring is routed, etc. It is difficult to reduce the clock skew between them. Therefore, the clock buffer 402 is inserted between the clock signal source cells and the flip-flops arranged at random, so that the wiring length and the number of drives from the signal source cells to the clock buffer are equal, and from the clock buffer to each flip-flop. A method of eliminating the signal skew of the clock signal of the terminal flip-flop from the clock source cell by equalizing the wiring length and the number of drives of the clock source cell has been used.

[0005]

The above-described conventional clock skew reduction method basically adjusts the wiring layout so that the wiring lengths from the clock source cell to the clock buffer and from the clock buffer to each flip-flop become equal. In order to make the number of drives even, a clock buffer is added. However, since the clock source cell, clock buffer, and flip-flop cell are wired at random, skew may occur due to the difference in the wiring length of the clock signal, and the clock source cell, the clock buffer, and the flip-flop cell may be used to bypass the wiring prohibited area caused by the arrangement of other cells. Skew was sometimes caused by physical restrictions.

Therefore, in order to solve such a problem, the wiring path is changed and the wiring delay time is adjusted so that the wiring length from the clock source cell to the clock buffer and from the clock buffer to each flip-flop are equalized. Was.

However, in this method, extra wiring must be routed in order to adjust the delay to the path delay of the slow signal path. Therefore, when the wiring is complicated and congested, the optimum wiring path is used. It is difficult to change, and it is necessary to redo the placement and routing in consideration of the delay again.

[0008]

[Means for Solving the Problems] (Means 1) A signal source unit of a clock driver group for distributing a clock signal on the same substrate of a semiconductor substrate, and a logic such as a flip-flop cell driven by the signal source unit. In the semiconductor device having a circuit unit, the clock signal is divided into a plurality of systems, and the signal source units are cascade-connected in a plurality of stages for each system and supplied to at least one logic circuit unit. In the clock skew reduction method for adjusting the wiring between the logic circuit units to have the same length so that the delay time is equal between the systems, the clock signal wiring connecting the signal source unit and the logic circuit unit is made of a material having a small resistance. Therefore, it is characterized by wiring.

(Means 2) A semiconductor device having a signal source unit of a group of clock drivers for distributing clock signals and a logic circuit unit such as a flip-flop cell driven by the signal source unit on the same semiconductor substrate. In the above configuration, the clock signal is divided into a plurality of systems, and the signal source units are cascade-connected by a plurality of stages for each system, and are supplied to at least one logic circuit unit. In the clock skew reduction method for equalizing the delay time between the systems by adjusting the wiring to the same length, the delay value of each net of the clock wiring is calculated, the delay of the path of each system is calculated, and the other paths are determined. Skew that occurs between the signal source units and the skew to minimize the skew. There is characterized in that to wire interconnection between the signal units and logic circuit unit partially resistance is small materials.

[0010]

According to the above configuration of the present invention, clock skew can be reduced by wiring with a material having a small resistance without changing the wiring path of the clock wiring whose wiring delay is to be adjusted.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an arrangement diagram showing an embodiment of the means 1. In FIG. 1, reference numeral 101 denotes a clock signal source cell, 1
02 is a clock buffer cell, 103 is a flip-flop cell, 104 is a clock signal wiring made of a material having a small resistance, 105 and 106 are logic cells other than cells synchronized with the clock signal, and 107 is an aluminum clock signal wiring.

In the semiconductor device according to the present invention, a plurality of clock buffer cells 102 are provided between a clock signal source cell 101 and a flip-flop cell 103 by using a conventional technique for reducing clock skew in a circuit arranged and wired. The cascade connection is performed step by step, the wiring length is made uniform, the number of drives is made uniform, and processing is performed so as to reduce clock skew. However, in the present embodiment, since the placement and routing is performed before the clock tree processing, the logic cell 106 that does not depend on the clock signal has already been placed, and the physical constraint for bypassing the routing prohibited area by this cell is established. The wiring is routed by this. Therefore, the wiring length of the clock wiring 104 cannot be completely equalized, so that the clock skew cannot be eliminated. Increasing the number of clock buffer stages to be inserted can further reduce clock skew, but increasing the number of elements also increases path delay.

Therefore, in this embodiment, in order to reduce the wiring delay of the clock signal wiring 104 formed of the clock tree of the specified number of stages, the resistance is higher than that of the conventional wiring layer material (in this embodiment, aluminum). Wiring is performed using a small substance, for example, gold.

As a result, since the wiring delay of the clock signal wiring 104 is reduced, it becomes possible to reduce the absolute amount of skew which remains even when the clock tree structure is used.

FIG. 2 is an arrangement diagram showing an embodiment of the means 2. In FIG. 2, reference numeral 201 denotes a clock signal source cell, 2
02 denotes a clock buffer cell, 203 denotes a flip-flop cell, 204 denotes a clock signal wiring made of a material having a small resistance, 205 and 206 denote logic cells other than cells synchronized with the clock signal, and 207 denotes an aluminum clock signal wiring.

In the semiconductor device of the present invention, a plurality of clock buffer cells 202 are provided between a clock signal source cell 201 and a flip-flop cell 203 by using a conventional technique for reducing clock skew in a circuit arranged and wired. The cascade connection is performed step by step, the wiring length is made uniform, the number of drives is made uniform, and processing is performed so as to reduce clock skew. However, in the present embodiment, since the placement and routing is performed before the clock tree processing, the logic cells 206 that do not depend on the clock signal are already placed, and physical constraints for bypassing the routing prohibited area by this cell are set. The wiring is routed by this. Therefore, since the wiring length of the clock wiring 204 cannot be completely equalized, the clock skew cannot be eliminated. Increasing the number of clock buffer stages to be inserted can further reduce clock skew, but increasing the number of elements also increases path delay.

Therefore, in the present embodiment, the path delay of each system is calculated, and the clock signal source 201 and the clock buffer 202, the clock buffer 202, Alternatively, the wiring between the clock buffer 202 and the flip-flop cell 203 is partially wired with a material having low resistance. As a result, it is possible to reduce the remaining skew even when the clock tree structure is used.

FIG. 3 shows a processing flow chart of the layout used in the means 2.

In the placed and routed circuit, a clock buffer cell 202 is inserted between the clock signal source cell 201 and the flip-flop cell 203 by using a conventional method for reducing clock skew in a process 301. Then, a process for reducing the clock skew is performed by making the wiring lengths equal and the number of drives equal.

Next, in the process of 302, wiring of the clock tree wired in the process 301 from the clock signal source cell to the clock buffer cell, between the clock buffer cells, or from the clock buffer cell to the flip-flop cell for each net. Perform length extraction.

Next, in the process of 303, the wiring resistance of each net is extracted from the wiring resistance and the wiring capacitance of aluminum or a substance having a low resistance (such as gold) using the wiring length of the net obtained in 302.

Next, at step 304, the wiring delay of each path of each clock wiring system is calculated, and the aluminum clock signal wiring 20 is set so as to minimize the clock skew between the paths.
The combination of 7 and the clock signal wiring 204 made of a material having a small resistance is determined.

Next, in the processing of 305, the net whose delay is to be reduced is changed to the clock signal wiring 204 made of a material having a small resistance in accordance with the distribution information obtained in 304.

As a result, it is possible to finely adjust the delay for each path while reducing the wiring delay of the clock signal wiring, and it is possible to reduce the remaining skew even when the clock tree structure is used.

[0026]

According to the invention described in the procedure 1, the absolute amount of the clock skew can be reduced without changing the wiring route for the clock skew remaining after the clock tree method.

According to the second aspect of the present invention, after arranging and wiring cells, the wiring length of each net is extracted, the wiring delay is obtained from the wiring length, and the resistance value is determined in consideration of the wiring length delay value. By selecting a net to be adjusted and using a material having a small resistance for the selected wiring, clock skew can be reduced without changing the wiring path.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing one embodiment of a semiconductor device according to Means 1 of the present invention.

FIG. 2 is a layout diagram showing one embodiment of a semiconductor device according to means 2 of the present invention.

FIG. 3 is a flowchart showing an example of a layout processing method for a semiconductor device according to means 2 of the present invention.

FIG. 4 is a layout view showing an example of a conventional semiconductor device having a tree structure.

[Explanation of symbols]

101: Clock signal source cell 102: Clock buffer cell 103: Flip-flop cell 104: Clock signal wiring of a material having low resistance 105, 106: Logic cell 107 independent of clock signal Aluminum clock signal wiring 201 ・ ・ ・ Clock signal source cell 202 ・ ・ ・ Clock buffer cell 203 ・ ・ ・ Flip-flop cell 204 ・ ・ ・ Clock signal wiring of a material having small resistance 205, 206 ・ ・ ・ Logic independent of clock signal Cell 207: Aluminum clock signal wiring 401: Clock signal source cell 402: Clock buffer cell 403: Flip-flop cell

Claims (2)

[Claims] 1. A semiconductor device comprising a signal source unit of a group of clock drivers for distributing clock signals and a logic circuit unit, such as a flip-flop cell, driven by the signal source unit on the same semiconductor substrate. In a configuration in which the clock signal is divided into a plurality of systems, the signal source units are cascade-connected by a plurality of stages for each system, and are supplied to at least one logic circuit unit. In the clock skew reduction method for adjusting the delay time to be equal between the systems by adjusting the length to the same length, the clock signal wiring connecting the signal source unit and the logic circuit unit is wired with a material having low resistance. Semiconductor device. 2. A semiconductor device comprising: a signal source unit of a group of clock drivers for distributing a clock signal; and a logic circuit unit such as a flip-flop cell driven by the signal source unit, on the same semiconductor substrate. In a configuration in which the clock signal is divided into a plurality of systems, the signal source units are cascade-connected by a plurality of stages for each system, and are supplied to at least one logic circuit unit. In the clock skew reduction method for equalizing the delay time between the systems by adjusting the length to the same length, the delay of each net of the clock wiring is calculated, the delay of the path of each system is obtained, and the delay between the other paths is calculated. Skew generated between the signal source units or between the signal units so that the skew is minimized. Tsu DOO and the semiconductor device, characterized in that to wire interconnection between the logic circuit unit partially resistance is small materials.