JP3104746B2 - Clock tree layout device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to an automatic clock tree placement device.

[0002]

2. Description of the Related Art In general, as a semiconductor integrated circuit becomes larger in scale, the semiconductor integrated circuit is designed as a synchronous circuit. Therefore, how to reduce the skew and distribute the clocks is a major problem. Conventionally, as a clock distribution of a semiconductor integrated circuit, for example, a clock distribution described in Japanese Patent Application Laid-Open No. 63-0205720 is known. I have.

[0003] Referring to FIG.
Is provided with a first-stage buffer 101, a second-stage buffer 102, a third-stage buffer 103, and a load circuit 104, and an N-phase clock T0, T1,
.., TN are given. As illustrated, each of the clock signals T0 to TN is supplied to a load circuit 1 via a first-stage buffer 101, a second-stage buffer 102, and a third buffer 103.
04.

As shown, if the stages are the same, all phases have the same number of buffers. For example, the clock T0
And the number of second-stage buffers 102 related to the clock TN is the same, that is, three. In addition, if the stage is the same, the load capacity of one buffer is the same in the buffers of any phase. A dummy block is used to make the same capacity.

[0005]

By the way, in the conventional method, a clock tree used to make the same capacity and the same length is not generated, and in addition, the number of flip-flops for each phase is greatly different. In the case where the clock tree generation was not considered in the case where the arrangement was erratic or the case of the gated clock,
There is a problem that too many dummy blocks are required.

That is, in the conventional method, it is difficult to form a clock tree having the same capacitance and the same resistance for all phases, and it is difficult to make the delays the same. For this reason, there is a problem that it is difficult to reduce the skew of the out-of-phase clock.

In addition, the conventional method has a problem that the number of dummy blocks is increased, so that not only the gate scale is increased but also the power consumption is increased.

It is an object of the present invention to provide an automatic clock tree arrangement device which can reduce the skew of a different-phase clock.

Another object of the present invention is to provide an automatic clock tree arrangement device which can reduce the gate scale and reduce power consumption.

[0010]

According to the present invention, there is provided a large-scale semiconductor logic circuit which distributes a plurality of clock signals to a plurality of load circuits such as flip-flops in a chip. An apparatus for generating and arranging a dummy block to equalize a delay to generate a clock tree layout, wherein the dummy block is generated near a load circuit connected to another clock different from a clock designated in advance. A first means, a second means for generating a connection relationship between the predetermined clock and the dummy block, and a cluster for generating one cluster for each clock phase to generate a load in each clock phase. Third means for further generating a plurality of clusters in consideration of the arrangement position of the circuit and the dummy block, and for each of the plurality of clusters Fourth generating disposed a buffer at a position where the balance of the serial load circuit and the dummy block can take
Means, and when the output destination of the buffer is all the dummy blocks, fifth means for deleting a connection relationship with the dummy block of the output destination and replacing the buffer with a dummy block. Thus, a clock tree layout apparatus is obtained. A gated clock signal is used as the plurality of clock signals.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

Referring to FIG. 1, the automatic clock tree arrangement device according to the present invention generates and arranges a clock tree according to the flowchart shown in FIG. First, step s1
Then, each cell is arranged. Then, in step s2, (n-1) dummy blocks are generated and arranged near the flip-flop (FF) to which the clock i is connected. Thereafter, a connection relationship is generated between each dummy block and the different-phase clock (step s3). Then, i = 1 is set in step s4.

In step s5, clustering of the clock i is generated, and in step s6, further clustering is performed in consideration of the arrangement position of the FF. Then, a buffer is generated and arranged at a position where the load can be balanced for each cluster (step s7). Then, step s
In step 8, if the output destinations of the placement buffer are all dummy blocks, the dummy blocks at the output destination and their connection relations are deleted, and the placement buffer is replaced with a dummy block. Then, in step s9, it is checked whether or not i <n, and
If i <n, i = i + 1 in step s10,
It returns to step s5.

On the other hand, if i <n is not satisfied in step s9, that is, if i ≧ n, equal delay wiring of the clock tree is performed in step s11.

FIG. 2 shows two clocks C1 and C2.
3 shows an example of a circuit having phases. 1 to the case where the processing shown in FIG. 1 is applied to the circuit example shown in FIG.
This will be described with reference to FIG.

First, each cell is arranged (step s).
1). As a result, for example, the cell arrangement shown in FIG. 3 is obtained. As shown in FIG. 4, a dummy block 12 is generated and arranged near the flip-flop 11 to which the clock C1 is connected. The number of dummy blocks generated for each flip-flop is 1 when the number of clocks is two.
In this case, two are generated and arranged in the case of three, and n-1 are generated and arranged in the case of n (step s2).

A connection relationship is generated between each dummy block and the clock C2 (step s3). Similarly, in step s2, a dummy block 12 is generated and arranged near the flip-flop 11 to which the clock C2 is connected, and in step s3, a connection relationship is generated between each dummy block and the clock C1. FIG. 4 shows the result of the dummy block generation arrangement and connection relation generation.

In step s5, a cluster of the clock C1 is generated. Then, in step s6, the cluster 13 is further generated in consideration of the arrangement positions of the flip-flop 11 and the dummy block 12. Clock C1
FIG. 5 shows the result of clustering.

In step s7, a buffer 14 is generated and arranged at the position of the center of gravity of each flip-flop 11 in the cluster 13. The position of the center of gravity is used to suppress clock skew in the same phase. Further, each cluster 1
Buffer 1 at the center of gravity of buffer 14 count generated in 3
5 is generated and arranged. Then, a clock tree of the clock C1 is configured. FIG. 6 shows the result of the clock tree configuration.

In step s8, if the output destinations of the buffers 14 and 15 forming the tree are all dummy blocks, the output destination dummy block 12 is deleted and the buffer 14 is replaced with the dummy block 12. FIG. 7 shows the result of deleting the dummy block 12 and replacing the buffer 14 with the dummy block 12. The same operation as the clock C1 is performed for the clock C2.

FIG. 8 shows the clustering result of C2.
Similarly, the result after arranging the clock tree is shown in FIG.
And FIG. FIG. 10 is a diagram in which the cluster lines in FIG. 9 are deleted. FIG. 11 shows a circuit diagram after the clock tree configuration. Note that a gated clock signal is used as the clock signal.

Next, a second example of the present invention will be described.

FIG. 12 shows a circuit having a multi-input circuit 16 for stopping a clock signal. The circuit shown in FIG. 12 is often used for low power consumption. The circuit shown in FIG. 12 operates with a one-phase clock C1. It is necessary to equalize the delay from the preceding block of the multi-input circuit 16 to all flips 11 groups.

First, each output of the multi-input circuit 16 is
Assume clock. If there are n multi-input circuits,
The clock has n phases.

When performing a clock tree configuration for an n-phase clock, the processing shown in FIG. 1 is performed, and a clock tree of the multi-input circuit 16 and the flip-flop group 11 is configured. Next, assume that the multi-input circuit 16 is a flip-flop. The clock tree 17 is configured by a one-phase clock equal delay arrangement wiring method. FIG. 13 shows a circuit diagram after the clock tree configuration.

[0026]

As described above, according to the present invention, (the total number of clocks minus one) is provided near the block connected to the clock.
) Dummy blocks are generated and arranged, the connection relation between each dummy block and the different phase is generated, and then the buffer is placed at a position where the load can be balanced in consideration of the arrangement relation of the blocks connected to each clock. At this time, if the output destination of the buffer is all dummy blocks, the dummy block of the output destination and its connection relation are deleted, the buffer is replaced with the dummy block, and this is replaced with the dummy block of each phase. Since a clock is used, a clock tree having the same capacity and the same resistance can be generated for each clock phase. For this reason, the delay amount can be made the same,
There is an effect that the skew of the different-phase clock can be reduced.

Further, according to the present invention, unnecessary dummy blocks are deleted, so that there is an effect that an increase in gate scale and power consumption can be suppressed.

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining processing of a layout apparatus according to the present invention.

FIG. 2 is a diagram illustrating an example of a logic circuit.

FIG. 3 is a diagram for explaining a clock tree layout of the logic circuit shown in FIG. 2;

FIG. 4 is a diagram for explaining a clock tree layout of the logic circuit shown in FIG. 2;

FIG. 5 is a diagram for explaining a clock tree layout of the logic circuit shown in FIG. 2;

FIG. 6 is a diagram for explaining a clock tree layout of the logic circuit shown in FIG. 2;

FIG. 7 is a diagram illustrating a clock tree layout of the logic circuit shown in FIG. 2;

FIG. 8 is a diagram for explaining a clock tree layout of the logic circuit shown in FIG. 2;

FIG. 9 is a diagram for explaining a clock tree layout of the logic circuit shown in FIG. 2;

FIG. 10 is a diagram for explaining a clock tree layout of the logic circuit shown in FIG. 2;

11 is a diagram illustrating a circuit after a clock tree is generated in the example of the logic circuit illustrated in FIG. 2;

FIG. 12 is a diagram illustrating another example of the logic circuit.

13 is a diagram illustrating a circuit after a clock tree is generated in the logic circuit illustrated in FIG. 12;

FIG. 14 is a diagram showing a conventional clock tree layout.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Flip-flop 12 Dummy block 13 Cluster 14, 15, 17 Clock tree buffer 16 Multi-input circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 G06F 1/10 H01L 21/82

Claims (6)

(57) [Claims] 1. A large-scale semiconductor logic circuit for distributing a plurality of clock signals to a plurality of load circuits in a chip, wherein a dummy block is generated and arranged to equalize a delay between respective phases of the clock. An apparatus for generating a tree layout, comprising: first means for generating the dummy block near a load circuit connected to another clock different from a previously specified clock; And a second means for generating a connection relationship with the dummy block. 2. The clock tree layout device according to claim 1, wherein said load circuit is a flip-flop. 3. The clock tree layout device according to claim 1, further comprising: generating one cluster for each clock phase, and arranging a load circuit and the dummy block in each clock phase. A clock tree layout apparatus comprising a third means for generating a plurality of clusters in consideration of positions. 4. The clock tree layout apparatus according to claim 3, further comprising a fourth means for generating and arranging a buffer at a position where the load circuit and the dummy block can be balanced for each of the plurality of clusters. A clock tree layout device comprising: 5. The clock tree layout apparatus according to claim 4, wherein when all the output destinations of the buffer are the dummy blocks, the connection relationship with the dummy block of the output destination is deleted to replace the buffer with the dummy block. A clock tree layout apparatus, comprising: 6. The clock tree layout device according to claim 1, wherein said plurality of clock signals are gated clock signals.