JPH07141406A - Arranging and wiring device - Google Patents

Abstract

PURPOSE:To provide an arranging and wiring device for reducing the wiring capacity of an LSI and lowering the power consumption. CONSTITUTION:This device is composed of a state transition analysis means 11, a switching probability analysis means 13 and an arranging and wiring means 12. The state transition analysis means 11 obtains the probability that the same state transition of signals in a circuit is simultaneously generated, the switching probability analysis means 13 obtains the switching probability of the signals and constraint conditions are prepared from both results. The arranging and wiring means 12 preferentially arranges the signals, whose simultaneous and the same state transition probability and switching probability are large, adjacently to each other and performs wiring. Thus, a coupling capacity is reduced and the power consumption is reduced as well.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an ASIC (Application Spe
The present invention relates to a placement and routing device used in the design of a cific integrated circuit).

[0002]

2. Description of the Related Art In recent years, ASIC (eg, cell-based LSI and gate array LSI) technology has rapidly developed due to progress in process technology and design technology. CAD (Computer Aided Design) tools play an important role in high performance and high integration of LSI. Unlike custom LSIs, ASICs have a large percentage of CAD design automation, and LSI performance is CAD.
It depends largely on the performance of the tool itself.

A placement and routing device is a CAD tool that is deeply involved in both performance and integration. This is a tool that automatically performs cell placement and inter-cell wiring in cell-based LSIs, and has been the subject of active technological development aimed at achieving desired performance while maintaining the degree of integration. Generally, the most important point in terms of performance is the operation speed of the LSI, but the technique that has been used to solve this problem has been to place a delay constraint on the placement and routing equipment. In this circuit, a part that operates slowly in the circuit is preferentially treated, and the wiring length of the part is shortened to reduce the delay to satisfy the constraint.

[0004]

However, in the above method, the constraint is simply determined by the magnitude relation of the delay of the signal propagation path such as the critical path, and the viewpoint of power consumption is lacking. Since one of the power consumption components of the LSI is expressed in a form proportional to the product of the wiring capacity and the number of times of switching, it is effective to reduce the wiring capacity of the path having a high switching probability. At the same time, in recent fine devices, the wiring capacitance is not determined only by the wiring length, but a placement and routing method considering the influence of adjacent wiring is required.

The present invention has been made in view of the above circumstances of the prior art, and an object of the present invention is to provide a placement and routing apparatus having a function of reducing the power consumption in consideration of the influence of adjacent wiring and the switching probability.

[0006]

The invention of claim 1 devised to achieve the above object comprises at least a state transition analysis means, a switching probability analysis means, and a placement and routing means. The state transition analysis means analyzes the state transition between at least two signals in the circuit to be placed and routed to obtain the probability that the same state transition occurs at the same time, and the switching probability analysis means analyzes the switching probability of the signals in the circuit. Then, the function value of the simultaneous same-state transition probability and the switching probability is output as a constraint condition. The placement and routing means refers to the constraint conditions and preferentially places and routes the signals having the large simultaneous simultaneous state transition probability and the switching probability so as to be adjacent to each other.

According to a second aspect of the present invention, the state transition analysis means considers that the overlapping period of the rising period or the falling period of the signal waveform is a certain value or more as a simultaneous state transition.

According to a third aspect of the present invention, the state transition analysis means sets the rising period or the falling period of the signal waveform to
A constant K, a load capacitance CL, and a delay change amount Δt per unit capacitance of an element that drives the signal are used to represent K * Δt * CL.

[0009]

According to the present invention, the state transition analysis means can determine the simultaneous and same state transition probabilities occurring in the circuit. Usually, coupling capacitance exists between adjacent wirings. The coupling capacitance becomes remarkable when the related wirings undergo different state transitions, but does not exist between the wirings where the same state transitions occur at the same time. In the present invention, since the wiring with a large simultaneous same-state transition probability is preferentially placed and arranged adjacently,
The coupling capacity is reduced, and as a result, power consumption can be reduced.

Further, it is effective to reduce the wiring capacitance of the wiring having a large switching probability with respect to power consumption, and this also enables the switching probability analysis means to know the switching probability of the signal by the configuration according to claim 1. In the present invention, signals having a high switching probability are preferentially arranged adjacent to each other, so that the coupling capacitance is reduced, and as a result, the power consumption can be reduced.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing this embodiment.
As shown in FIG. 1, this embodiment comprises a logic simulation means 1 and a placement and routing apparatus 10.

First, the data flow between the respective components will be described. The logic simulation means 1 executes the logic simulation according to the test pattern 4 while referring to the netlist 2 and the device library 3 of the target circuit,
The result is output to the logic simulation result 5. Here, the net list 2 shows connection information of elements in the circuit. Further, the element library 3 has information such as element functions, characteristics, and layout. The placement and routing apparatus 10 includes a state transition analysis unit 11, a switching probability analysis unit 13, and a placement and routing unit 12. The state transition analysis unit 11 analyzes the logic simulation result 5 and outputs the result to the constraint condition 6 while referring to the netlist 2 and the device library 3 of the target circuit. The switching probability analysis unit 13 analyzes the logic simulation result 5 and outputs the result to the constraint condition 6 while referring to the netlist 2 of the target circuit and the element library 3. The placement and routing unit 12 performs placement and routing according to the constraint condition 6 while referring to the netlist 2 and the element library 3 of the target circuit, and outputs the result to the placement and routing result 7.

Next, the operation of the placement and routing apparatus 10 will be described in detail. State transition analysis means 1 using the circuit shown in FIG. 4 as an example.
It will be described from 1. This circuit is composed of two-input NANDs 50 and 52 and inverters 51 and 53, and has input signals A, B and C, output signals F and G and internal signals D and E. A coupling capacitor 54 exists between the internal signals D and E. Now, consider applying signals as shown in FIG. 5 to the input signals A, B, and C. Here, the horizontal axis of FIG. 5 represents time and the vertical axis represents logical value. Then, the results shown in FIG. 5 are obtained for the internal signals D and E.
The state transition analysis means 11 counts the same simultaneous state transition between two signals as indicated by the arrow in the part surrounded by the ellipse in FIG. 5, and obtains the occurrence probability. Generally, the state transition between two signals is as shown in FIG. 7 when viewed as a voltage waveform. Here, the horizontal axis of FIG. 7 represents time and the vertical axis represents voltage. The phase at the time of state transition and the rising or falling period (slew rate) differ depending on the signal. Therefore, in the present invention, the simultaneity of state transition is determined as follows. Rising period T1 of signal X (hatched part in Fig. 7)
And the overlap of the rising period T2 (hatched portion in FIG. 7) of the signal Y is examined. Next, this overlap period T3
Two signals are considered to have changed at the same time when a certain value is larger than a certain fixed value, while they are not considered to be simultaneous when the overlap period is smaller than a certain certain value. The rising period and the falling period used here are determined as follows. Generally, the rising or falling period of the waveform of a signal is related to the driving ability of a device that drives the signal. In the present invention, the rising or falling period is defined as K *
It is expressed as Δt * CL. Here, K is a constant, CL is a load capacitance, and a delay change amount Δt per unit capacitance of a driven element. The constant K can be chosen freely. In this way, the state transition analysis means 11 analyzes the logic simulation result 5 similar to that shown in FIG. An example of the obtained simultaneous same-state transition probabilities is shown in (Table 1). Simultaneous same-state transition probabilities are shown for each combination of two signals.

[0015]

[Table 1]

The switching probability analysis means 13 will be described. In the circuit, the switching frequency and probability of the required signal are calculated with reference to the signal with the highest switching frequency. In this way, the switching probability analysis means 13 analyzes the logic simulation result 5 similar to that shown in FIG.
An example of the obtained switching probabilities is shown in (Table 2). The switching probability is shown for each combination of the two signals.

[0017]

[Table 2]

Next, the product of the simultaneous same-state transition probabilities and the switching probabilities is obtained, and this is set as constraint condition 6. Table 1 and Table 2
Is obtained as a product (Table 3).

[0019]

[Table 3]

Finally, the placement and wiring means 12 will be described. Figure 2
An example of a wiring cross-sectional view is shown in FIG. Here, 20 and 21 are wirings for two signals, 22 and 23 are capacitances from the wirings to the substrate, and 24 is a coupling capacitance between the wirings. Coupling capacity 24
Changes depending on the potential relationship between the wiring 20 and the wiring 21. Wiring 20
When the wiring 21 and the wiring 21 make a state transition at different potentials, the coupling capacitance exists, and when the wiring 20 and the wiring 21 make a state transition at the same potential, the coupling capacitance 24 becomes zero.
Assuming that the value of the capacitor 22 is C22, the value of the capacitor 23 is C23, and the value of the capacitor 24 is C24, for example, when the logic state of the wiring 20 changes from 0 to 1 and the wiring 21 remains 0 or 1, the total capacitance is
It becomes (C22 + C23 + C24). On the other hand, the logic state of the wiring 20 is 0
When the wiring 21 changes from 1 to 0, the total capacitance becomes (C22 + C23 + 2 * C24). When the logic state of the wiring 20 changes from 0 to 1 and the wiring 21 also changes from 0 to 1, the coupling capacitance becomes zero and the total capacitance becomes (C22 + C23). Therefore, it is effective to reduce the wiring capacitance by making the same state transition between the adjacent wirings. FIG. 6 shows the placement and routing result of the placement and routing apparatus of the present invention for the circuit of FIG. Here, 60 is a layout, 61 is an element region, and 62 is a wiring. Due to the constraint condition, the two wirings 62 corresponding to the two signals D and E in FIG. 4 are horizontally adjacent to each other, and the coupling capacitance 54 becomes zero when the signals D and E simultaneously make the same state transition during operation. become.

As described above, in the placement and routing apparatus of this embodiment,
Signals that have the same state transition at the same time and have a high switching frequency are preferentially placed adjacent to each other, so that the coupling capacitance is reduced, and as a result, low power consumption can be achieved.

In this embodiment, the wiring is arranged horizontally adjacent to the substrate as shown in FIG. 2, but the wiring is arranged vertically adjacent to the substrate as shown in FIG. It may be arranged and wired. Here, 30 and 31 are wirings, and 32, 33 and 34 are wiring capacitances. As in the case of FIG. 2, if the signals simultaneously undergo the same state transition, the coupling capacitance 32 becomes zero. As a result, in the upper layer wiring 30, the shielding effect of the lower layer wiring 31 can be combined and the capacity can be remarkably reduced.

In this embodiment, the constraint condition is set for the state transition between two signals, but the state transition between three or more signals may be treated in the same manner. In that case, when the target wiring groups are horizontally adjacent to each other, as shown in FIG.
Further, in the case of vertically adjoining, placement and wiring may be performed as shown in FIG.

Further, in this embodiment, the product of the simultaneous same-state transition probability and the switching probability is used as the function value which is the constraint condition, but another function may be used.

Further, in this embodiment, the constraint condition is composed of the simultaneous same-state transition probability and the switching probability, but it may be used together with the conventional method of controlling the wiring length by the delay constraint condition.

[0026]

According to the placement and routing apparatus of the first aspect,
The state transition analysis means and the switching probability analysis means have a high probability of simultaneously making the same state transition among the signals of the circuit, and a signal with a high switching frequency is selected and preferentially arranged and wired adjacent to each other. The coupling capacity is reduced, and as a result, it is possible to reduce the power consumption, which was difficult in the past. Further, with respect to the wiring having the reduced coupling capacitance, the delay is also reduced, so that the speedup can be achieved and the coupling noise can be reduced.

According to the placement and routing apparatus of the second aspect, since the simultaneity of the state transition of each signal is determined only by the magnitude relation with respect to the constant value of the overlap period of the transition, the processing can be easily performed, and as a result, the processing time can be increased. Can be shortened.

According to the arrangement and wiring device of the third aspect, the rising period and the falling period can be easily determined only from the load capacity of the signal and the driving capability of the element for driving the signal.
As a result, the processing time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in an embodiment of the present invention.

FIG. 2 is a sectional view for explaining the influence of wiring capacitance in the embodiment of the present invention.

FIG. 3 is a sectional view for explaining the influence of wiring capacitance in the embodiment of the present invention.

FIG. 4 is a circuit diagram of a circuit example according to an embodiment of the present invention.

FIG. 5 is a timing diagram illustrating the operation of the circuit example according to the embodiment of the invention.

FIG. 6 is a layout diagram of a circuit example according to an embodiment of the present invention after placement and routing.

FIG. 7 is a voltage waveform diagram of two signals in the embodiment of the present invention.

FIG. 8 is a sectional view of an example of arrangement and wiring in a multi-wiring system according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view of a placement and wiring example in a multi-wiring system according to an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 logic simulation means 2 netlist 3 element library 4 test pattern 5 logic simulation result 6 constraint condition 7 placement and routing result 10 placement and routing device 11 state transition analysis means 12 placement and routing means 13 switching probability analysis means 20, 21, 30, 31, 62 wiring 22,23,24,32,33,34 wiring capacitance 50,52 2-input NAND 51,53 inverter 54 coupling capacitance 60 layout 61 element area

Claims (3)

[Claims] 1. At least two of the circuits to be placed and routed.
State transition analysis means for determining the probability that the same state transition occurs at the same time by analyzing the state transition between two signals, and by analyzing the switching probability of the signal in the circuit,
Switching probability analysis means for outputting a function value of the simultaneous same-state transition probability and the switching probability as a constraint condition, and referring to the constraint condition, preferentially a signal with a large simultaneous simultaneous-state transition probability and the switching probability. And a placement and routing device for placing and routing adjacent to the wiring. 2. The state transition analysis means considers that the overlapping period of the rising period or the falling period of the signal waveform is a certain value or more as a simultaneous state transition. Placement and wiring equipment. 3. The state transition analysis means uses a constant K, a load capacitance CL, and a delay change amount Δt per unit capacitance of a device that drives the signal as K during the rising period or the falling period of a signal waveform. 3. The placement and routing device according to claim 2, wherein the placement and routing is represented by * Δt * CL.