JP3305176B2 - Automatic element placement device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an automatic element arranging apparatus for automatically performing a layout design of a semiconductor integrated circuit, a printed circuit board, a multi-chip module, and the like.

[0002]

2. Description of the Related Art Conventionally, as a method for automatically designing a layout of a semiconductor integrated circuit, a printed circuit board, a multi-chip module, etc., a method using a floor plan process is known.

[0003] The floor plan step is a step of determining an arrangement constraint using information relating to signal connection between elements, element shape, element pin position, and the like.
This floor plan process greatly affects the ease of placement and wiring in the subsequent placement and wiring processes, chip size, chip performance (operating characteristics), and the like.

As a method of executing the floor plan process, there are a method of performing automatic calculation using a computer and a method of performing manual calculation.

Here, in a floor plan process using a computer, when the circuit configuration is simple, a method of determining the placement restriction conditions in units of elements is generally used. In this method, the placement constraint may be determined in consideration of connection information between elements, performance constraints, and the like.

On the other hand, in a floor plan process using a computer, when the circuit configuration is complicated, a general method is to divide the entire circuit into a plurality of groups and determine the placement constraints on a group basis. . In this method, first, the entire circuit is divided into a plurality of groups in consideration of the circuit hierarchical structure and signal connection information. Next, regarding the group as a kind of element, connection information between the groups,
An optimization problem (group placement problem) is solved using performance constraints, group shapes, group overlaps, and the like as cost functions, thereby determining constraint conditions. Then, using this as a constraint on the element arrangement, an arrangement step and a wiring step are executed as subsequent steps.

[0007]

When grouping is performed in a conventional floor plan process, as described above,
In addition to connection information between elements, performance constraints, and the like, constraint conditions must be determined at the same time in consideration of the shape and overlap of the groups. For this reason, the cost function has a large degree of freedom and becomes very complicated, so that it is very difficult to set an appropriate cost function and obtain an optimal solution.

Further, since the cost function is complicated as described above, it is difficult in the conventional floor plan process to accurately predict the degree of wiring congestion and the performance in the floor plan creation process and after the determination.

[0009] For this reason, conventionally, when the placement and wiring process is performed as a post-process of the floor plan process, the layout size may become large or the wiring may not be possible.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and has an automatic element arrangement capable of reducing the layout size and guaranteeing the performance even in a large-scale circuit. It is intended to provide a device.

[0011]

According to the automatic element arranging apparatus of the present invention, a temporary arranging section for arranging a temporary element for each element and a temporary arranging section for each element arranged by the temporary arranging section are provided. A wiring congestion degree estimating unit that determines a wiring path and estimates the degree of congestion of these wiring paths, a performance analyzing unit that performs performance analysis on each element arranged by the temporary arrangement unit, and a temporary Based on the placement, the wiring congestion estimation by the wiring congestion estimation unit, and the result of the performance analysis by the performance analysis unit, the final grouping of each element is determined, and the final placement constraint of each group is determined. A main placement constraint generation unit that generates a final placement unit that performs a final element placement based on the placement constraints generated by the main placement constraint generation unit; Characterized by comprising. Each element is further divided into temporary groups, and further includes a temporary placement constraint generation unit that generates a placement constraint of each group as a temporary placement constraint, wherein the temporary placement constraint generation unit generates the temporary placement constraint using the temporary placement constraint. It is advisable to perform a provisional element arrangement.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of an automatic element placement device according to the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a system configuration of the automatic element placement device according to the present embodiment.

In FIG. 1, a control unit 101 controls the entire system.

The data input / output unit 102 reads component information, signal connection information, performance constraints, control parameters, and the like (described later) used in the floor plan process, and stores them in the data storage unit 103. These input data and data generated in the system (placement data, placement constraint data, wiring congestion degree estimation data, performance data, etc .; described later) are also used when reading from the data storage unit 103 and outputting from the system. Is done.

The placement constraint generation unit 104 includes a data storage unit 1
The placement constraint is determined based on the data and the like read from the program 03. Then, the generated placement constraint data is stored in the data storage unit 103.

The arranging unit 105 performs an arranging process by using the same arrangement constraint data read from the data storage unit 103 as in the main arranging step. Then, the generated arrangement data is stored in the data storage unit 103. As will be described later, the arranging unit 105 is used in a tentative arranging process for determining a relative position value of a group and an arranging process after a floor plan process.

The wiring congestion estimating unit 106 uses the placement data read from the data storage unit 103 to predict the wiring route at high speed by a stochastic virtual wiring method. Then, a wiring congestion degree map is created based on the prediction result. This wiring congestion degree map is stored in the data storage unit 103 as wiring congestion degree estimation data. As will be described later, the wiring congestion degree estimation data is used when determining a utility of a group or when performing a merge process.

The performance analysis unit 107 analyzes the performance of the circuit (analysis for guaranteeing the operation speed) using the arrangement data read from the data storage unit 103.
Perform The result of the performance analysis is stored in the data storage unit 103 as performance data. As will be described later, the performance data is used when determining a utility of a group or when performing a merge process.

Next, a procedure for performing automatic element placement using the system as shown in FIG. 1 will be described with reference to FIGS.

FIG. 2 is a flowchart schematically showing the procedure of automatic element placement by the automatic element placement apparatus according to this embodiment.

First, the data input / output unit 102 inputs component data, connection information, performance constraints and control parameters from outside the system, and
3 (S201).

Here, the component data is composed of data such as the size and shape of the logic gate, the pin position, the prohibited area of the wiring, the required time from signal input to signal output, and the capacitance when the wiring is connected to the pin. Have been.

The connection information is information indicating a connection relationship between elements, and includes hierarchical information.

The performance constraint is data representing a constraint on the operating frequency of the chip and the arrival time from input to output.

The control parameter is a parameter indicating the degree of importance in determining the placement constraint with respect to the degree of wiring congestion and the performance.

Here, since the data input in step S201 is data for provisional placement, the performance constraints and control parameters are assumed to be the same or less restrictive as in the case of the regular placement.

Next, the placement constraint generation unit 104 generates a provisional placement constraint (S202; corresponding to the operation of the "temporary placement constraint generation unit" in claim 2).

In this generation process, first, at step 201
(Part data, connection information, performance constraints and control parameters)
Read from 3. Next, elements are divided into temporary groups based on these input data. Then, a loose arrangement constraint is determined for each group. The temporary placement constraint obtained in this way is stored in the data storage unit 103 as placement constraint data.

In this arrangement restriction, restrictions on the vertical and horizontal lengths and the length of a half circumference (the sum of the vertical and horizontal lengths) are defined for each group.

The provisional placement constraint need not be executed if it is not necessary.

Subsequently, the arranging unit 105 performs a tentative arrangement (S203; corresponding to the operation of the "temporary arranging unit" in claims 1 and 2).

In this process, first, the temporary placement constraint (location constraint data) generated in step S202 is read from the data storage unit 103. Then, the absolute position of each element is determined using this data. At this time, by using the same method (for example, the mini-cut method or the like) as the later-described real arrangement, the accuracy of the temporary arrangement can be increased, and the optimization of the real arrangement restriction can be promoted. After that, the data of the temporary arrangement thus obtained is stored in the data storage unit 103 as arrangement data.

If step S202 is not executed, the component data, connection information, performance constraints, and control parameters input in step S201 are read from the data storage unit 103, and the provisional arrangement is performed using these data. Do.

Next, the wiring congestion degree estimating section 106 estimates a wiring congestion location (S204; this corresponds to the operation of the "wiring congestion degree estimating section" in claim 1).

In this process, first, the temporary arrangement data (arrangement data) generated in step S203 is read from the data storage unit 103. Next, based on the placement data, a wiring route is predicted using a stochastic virtual wiring technique. Further, based on the expected result, an estimation of a portion where the wiring is congested is performed. Then, a map (wiring congestion degree estimation data) indicating the result of the estimation is stored in the data storage unit 103. The wiring congestion degree estimation data is used for adjustment of utility (ratio of element area to circuit area) for each group and generation of constraint conditions such as merging (integrating a plurality of groups).

Next, the performance analysis unit 107
The performance is analyzed (S205; corresponds to the operation of the "performance analysis unit" in claim 1).

Also in this process, first, the data (arrangement data) of the temporary arrangement generated in step S203 is read from the data storage unit 103. Next, performance analysis is performed based on the arrangement data. Then, data (performance data) indicating the analysis result is stored in the data storage unit 103. This performance data also
It is used for adjusting the utility for each group and generating constraints such as merging.

After that, the placement constraint generation unit 104 determines the main placement constraint using the data of the provisional placement, the estimated data of wiring congestion, and the performance data obtained as described above (S206; claim 1). This corresponds to the operation performed by the “real arrangement constraint generation unit”).

In this process, first, in steps S203 to S203,
Data of the temporary arrangement (arrangement data) generated in S205,
Wiring congestion estimation data and performance data
The data is read from the data storage unit 103.

Next, based on these input data, constraints on the relative positional relationship of the above-mentioned group (S203) are determined. If it is determined that it is better to integrate a plurality of groups, those groups are merged. Then, for the group after the merge, the constraint of the relative positional relationship is updated.

Further, in this process, the shape of the group and the utility are optimized. These optimizations are performed using the area of the element in the group (obtained from the data of the provisional arrangement) and the data of the degree of congestion of the wiring.

The data of the main placement constraint obtained in this way is used as placement constraint data in the data storage unit 1.
03.

Finally, using this placement constraint data,
The final arrangement is performed (S207; corresponds to the operation by the "main arrangement unit" in claim 1).

In this process, first, the placement constraint data generated in step S206 is read from the data storage unit 103. Then, using this data, the absolute position of each element is determined by the same method as the temporary arrangement. afterwards,
The data of the real arrangement thus obtained is stored in the data storage unit 103 as arrangement data, and the automatic element arrangement is completed.

Next, the above-described placement constraint generation process (S20)
6) and a specific example of the main placement process (S207)
This will be described with reference to FIG.

In FIG. 3, (a) shows a provisional arrangement process (S2
03) It is a conceptual diagram showing the position of each group after,
(B) is a conceptual diagram showing the position of each group after the main placement process (S207).

Here, it is assumed that as a result of the wiring congestion estimation process (S204) performed after the tentative placement process (S203), it is found that the wiring congestion of the group A becomes extremely large (FIG. 3A). reference). For this reason, in the present placement constraint generation process (S207), the utility is adjusted to
Relax the restrictions on the area of group A. Thus, in the actual arrangement, the area of the group A is larger than that in the temporary arrangement (see FIG. 3B).

As a result of the performance analysis step (S205) after the provisional arrangement step (S203), the signals output from the group B cannot reach the groups C and I within a desired time, and a timing violation occurs. It is assumed that it has occurred (see FIG. 3A). Therefore, in the placement constraint generation process (S207), the groups B, C, and I are merged and the shape is changed. As a result, the groups B, C, and I are treated as one group (see FIG. 3B), so that the degree of freedom in element arrangement in this arrangement is increased, and it is easy to prevent occurrence of timing violation.

On the other hand, in the groups D and E, the boundary portions are complicated and complicated, and the optimal element arrangement (that is, the arrangement that reduces the layout size and the degree of wiring congestion) during the provisional arrangement (S203). Have difficulty. Therefore, in the main placement constraint generation step (S207), the groups D and E are merged, thereby facilitating the optimization of the element arrangement in the main placement step (see FIG. 3B).

Further, the group H is included in the group G, and causes a meaningless provisional placement constraint (see FIG. 3A). For this reason, the main placement constraint generation process (S2
In 07), the group H and the group I are merged to facilitate the optimization of the element arrangement in the actual arrangement process (see FIG. 3B).

As described above, the automatic element placement apparatus according to the present embodiment does not input data such as component data, connection information, and performance constraints from the outside to determine placement constraints as they are, but first, Is used to determine a temporary placement constraint, and final placement constraints are determined using temporary placement data, wiring congestion estimation data, and performance analysis data generated based on the temporary placement constraint. .

Therefore, according to the automatic element placement apparatus according to the present embodiment, the optimization problem can be simplified, the optimization efficiency can be increased, the layout size and the degree of wiring congestion can be reduced, and the performance can be reduced. It is effective for the security of In addition, since the same method (for example, the mini-cut method) as that of the real placement (S207) is used in the temporary placement step (S203), the accuracy of the temporary placement can be improved, and the optimization of the real placement constraint can be performed. Can be promoted.

[0054]

As described above in detail, according to the present invention, there is provided an automatic element placement device capable of reducing the layout size even in a large-scale circuit and guaranteeing the performance. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of an automatic element placement device according to an embodiment of the present invention.

FIG. 2 is a flowchart schematically showing a procedure of automatic element arrangement by the automatic element arrangement apparatus according to the embodiment shown in FIG. 1;

3A and 3B are diagrams for explaining a specific example of a real placement constraint generation process and a real placement process shown in FIG. 2, wherein FIG. 3A is a conceptual diagram showing the position of each group after provisional placement, and FIG. Is a conceptual diagram showing the position of each group after the actual arrangement.

[Explanation of symbols]

 Reference Signs List 101 control unit 102 input / output unit 103 data storage unit 104 placement constraint generation unit 105 placement unit 106 wiring congestion degree estimation unit 107 performance analysis unit

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-6-180733 (JP, A) JP-A-5-35822 (JP, A) JP-A-5-2626 (JP, A) JP-A-4- 48651 (JP, A) JP-A-3-242953 (JP, A) JP-A-3-25953 (JP, A) Toshihiro Akiyama, two others, layout technology of high-performance ASIC, Toshiba Review, Toshiba Corporation, Vol. 50, No. 1, June 1, 1995. 6, p. 460-464, CSNS 199700246005 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/50 658

Claims (2)

(57) [Claims] 1. A tentative placement unit for arranging tentative elements for each element, and tentative wiring paths for each element arranged by the tentative placement unit are determined, and the congestion degree of these wiring paths is estimated. A wiring congestion degree estimating unit, a performance analysis unit that performs performance analysis on each element arranged by the temporary arrangement unit, a temporary arrangement by the temporary arrangement unit, a wiring congestion degree estimation by the wiring congestion degree estimation unit, and A final placement constraint generation unit that determines a final grouping of each element based on a result of the performance analysis by the performance analysis unit and generates a final placement constraint of each group; And a main placement unit that performs a final placement of elements based on the placement constraint generated by the automatic placement apparatus. 2. The apparatus according to claim 1, further comprising: a provisional placement constraint generation unit that divides each element into a provisional group and generates a placement constraint of each group as a provisional placement constraint. The automatic element placement device according to claim 1, wherein the temporary element placement is performed using a constraint.