JPH09146997A - Automatic element arranging method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the layout size of even a large-scale circuit and guarantee the performance by performing final element arrangement according to arrangement restrictions generated in a final arrangement restriction generating process. SOLUTION: A data input/output part 102 inputs component data, connection information, performance restrictions, and control parameters from outside the system and stores them in a data storage part 103. Then, an arrangement restriction generation part 104 generates tentative arrangement restrictions. Then an arrangement part 105 performs tentative arrangement, and further, estimates a wiring congestion place. A performance analysis part 107 analyzes the performance. Then, the arrangement restriction generation part 104 determines final arrangement restrictions by using the data on the tentative arrangement, wiring congestion degree estimation data, and performance data. The data on the obtained final arrangement restrictions are stored as arrangement restriction data in the data storage part 103. Lastly, the arrangement restriction data are used to perform the final arrangement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic element arranging method for automatically designing a layout of a semiconductor integrated circuit, a printed circuit board, a multichip module or the like.

[0002]

2. Description of the Related Art Conventionally, as a method for automatically designing a layout of a semiconductor integrated circuit, a printed circuit board, a multi-chip module, etc., a method using a floor plan process is known.

The floorplanning step is a step of deciding the layout constraint condition by using the constraint conditions such as the information about the signal connection between the devices, the shape of the device, the pin position of the device and the like.
This floorplanning process greatly affects the ease of placement / wiring in the placement / wiring process as a post-process, the chip size, the chip performance (operating characteristics), and the like.

As a method for executing the floor plan process, there are a method of automatically calculating using a computer and a method of manual work.

Here, in a floor plan process using a computer, when the circuit configuration is simple, it is general to determine the constraint condition of the placement for each element. In this method, the layout constraint condition may be determined in consideration of the connection information between elements and the performance constraint.

On the other hand, in a floor plan process using a computer, when the circuit configuration is complicated, it is common to divide the entire circuit into a plurality of groups and determine the layout constraint condition for each group. . In this method, first, the entire circuit is divided into a plurality of groups in consideration of the hierarchical structure of the circuit and signal connection information. Next, consider the group as a kind of element, and connect information between groups,
The optimization problem (group placement problem) is solved using performance constraints, group shapes, group overlaps, etc. as cost functions, and the constraint conditions are determined by this. Then, with this as a constraint for the element placement, the placement step / wiring step as a post step is executed.

[0007]

When performing grouping in the conventional floorplanning process, as described above,
In addition to the connection information between elements and the performance constraint, the constraint condition must be determined at the same time by considering the shape and overlap of the group. Therefore, the cost function has a large degree of freedom and becomes very complicated, and it is very difficult to set an appropriate cost function and obtain an optimum solution.

Further, since the cost function is complicated as described above, it is difficult in the conventional floorplanning process to accurately predict the wiring congestion degree, the performance, etc. after the floorplan making process and after the decision.

Therefore, conventionally, when the layout / wiring process is performed as a post-process of the floor plan process, the layout size may be increased or wiring may be impossible.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and it is possible to reduce the layout size even in a large-scale circuit and to ensure the performance of an automatic element arrangement. The purpose is to provide a method.

[0011]

According to the automatic element placement method of the present invention, a temporary placement step for performing a temporary element placement for each element and a temporary wiring route for each element placed in the temporary placement step are provided. To determine the congestion degree of these wiring paths, a performance analysis step of performing a performance analysis for each element arranged in the temporary placement step, the temporary placement step, and the wiring congestion. Based on the results of the degree estimation process and the performance analysis process, the final grouping of each element is determined, and the final placement constraint generation process for generating the final placement constraint for each group, and the final placement constraint generation process. A main placement step of performing a final element placement based on the placement constraint generated in the step.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of an automatic element arranging method according to the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing the system configuration of an apparatus for executing the automatic element placement method according to this embodiment.

In FIG. 1, a control unit 101 controls the entire system.

The data input / output unit 102 also reads component information, signal connection information, performance constraints, control parameters and the like (described later) used in the floorplan process and stores them in the data storage unit 103. It is also used when these input data and data generated in the system (placement data, placement constraint data, wiring congestion degree estimation data, performance data, etc .; described later) are read from the data storage unit 103 and output from the system. To be done.

The layout constraint generation unit 104 includes a data storage unit 1.
The layout constraint is determined based on the data read from 03. Then, the placement constraint data thus generated is stored in the data storage unit 103.

The placement unit 105 uses the placement constraint data and the like read from the data storage unit 103 to perform placement processing by the same method as the main placement process. Then, the generated layout data is stored in the data storage unit 103. As will be described later, the placement unit 105 is used in a temporary placement process for determining the relative position value of the group and a placement process after the floorplanning process.

The wiring congestion degree estimation unit 106 uses the placement data read from the data storage unit 103 to predict the wiring route at high speed by the stochastic virtual wiring method. Then, a wiring congestion degree map is created based on this prediction result. The wiring congestion degree map is stored in the data storage unit 103 as wiring congestion degree estimation data. This wiring congestion degree estimation data is used when determining the utility of the group and when performing merge processing, as described later.

The performance analysis unit 107 uses the arrangement data read from the data storage unit 103 to analyze the performance of the circuit (analysis for ensuring the operation speed).
Perform The result of this performance analysis is stored in the data storage unit 103 as performance data. As will be described later, this performance data is used when determining the utility of the group and performing the merge process.

Next, a procedure for performing automatic element placement using the system as shown in FIG. 1 will be described with reference to FIGS. 2 and 3.

FIG. 2 is a flow chart schematically showing the procedure of automatic element placement according to this embodiment.

First, the data input / output unit 102 inputs component data, connection information, performance constraints and control parameters from outside the system, and the data storage unit 10
3 (S201).

Here, the component data is composed of data such as the size and shape of the logic gate, the pin position, the wiring prohibited area, the time required from signal input to signal output, and the capacitance when the wiring is connected to the pin. Has been done.

The connection information is information indicating the connection relationship between elements and includes hierarchical information.

Performance constraints are data representing constraints on the operating frequency of the chip and the arrival time from input to output.

The control parameter is a parameter indicating the degree of importance in determining the placement constraint with respect to the wiring congestion degree, the performance, and the like.

Here, since the data input in step S201 is data for temporary placement, performance constraints and control parameters are set equal to or looser than those in the main placement.

Next, the placement constraint generation unit 104 generates a temporary placement constraint (S202; corresponds to the "temporary placement constraint generation process" in claim 2).

In this generation process, first, step 201
The data (part data, connection information, performance constraints, and control parameters) input in step 3 is stored in the data storage unit 10.
Read from 3. Next, the elements are divided into temporary groups based on these input data. Then, a soft placement constraint is determined for each group. The temporary placement constraint obtained in this way is stored in the data storage unit 103 as placement constraint data.

This layout constraint defines the length / width and half circumference length (the sum of the length and width) of each group.

It should be noted that this temporary placement constraint may not be executed if it is unnecessary.

Subsequently, the placement unit 105 performs temporary placement (S203; corresponds to the "temporary placement step" in claims 1 and 2).

In this process, first, the temporary placement constraint (placement constraint data) generated in step S202 is read from the data storage unit 103. Then, using this data, the absolute position of each element is determined. At this time, by using a method similar to the main placement described later (for example, the mini-cut method), the accuracy of the temporary placement can be increased and the optimization of the main placement constraint can be promoted. Thereafter, the temporary placement data obtained in this way is stored in the data storage unit 103 as placement data.

If step S202 described above is not executed, the component data, connection information, performance constraints and control parameters input in step S201 are read from the data storage unit 103, and temporary placement is performed using these data. To do.

Next, the wiring congestion degree estimation unit 106 estimates the wiring congestion location (S204; corresponds to the "wiring congestion degree estimation process" in claim 1).

In this process, first, the temporary placement data (placement data) generated in step S203 is read from the data storage unit 103. Next, based on this arrangement data, a wiring route is predicted by using a probabilistic virtual wiring technique. Further, based on the prediction result, the place where the wiring is congested is estimated. Then, a map showing the result of this estimation (wiring congestion degree estimation data) is stored in the data storage unit 103. The wiring congestion degree estimation data is used to generate a constraint condition such as adjustment of utility (ratio of element area to circuit area) for each group and merge (integration of a plurality of groups).

Next, the performance analysis unit 107
The performance is analyzed (S205; corresponds to the "performance analysis process" in claim 1).

Also in this process, first, the temporary placement data (placement data) generated in step S203 is read from the data storage unit 103. Next, the performance is analyzed based on this arrangement data. Then, the data (performance data) indicating the analysis result is stored in the data storage unit 103. This performance data also
It is used to adjust the utility of each group and generate constraints such as merging.

After that, the placement constraint generating unit 104 determines the real placement constraint by using the temporary placement data, the wiring congestion degree estimation data and the performance data obtained as described above (S206; claim 1). It corresponds to the "book layout constraint generation process").

In this process, first, steps S203-
Temporary placement data (placement data) generated in S205,
Wiring congestion estimation data and performance data,
It is read from the data storage unit 103.

Next, based on these input data, the constraint on the relative positional relationship of the above-mentioned group (S203) is determined. If it is determined that a plurality of groups should be integrated, those groups are merged. Then, the relative positional relationship constraint is updated for the group after the merge.

Further, in this process, the shape of the group and the utility are optimized. These optimizations are performed using the area of elements in the group (obtained from data of temporary placement) and the wiring congestion degree estimation data.

The data of the main placement constraint obtained in this way is used as placement constraint data, and the data storage unit 1
03.

Finally, using this arrangement constraint data,
Final placement is performed (S207; corresponds to the "main placement process" in claim 1).

In this process, first, the placement constraint data generated in step S206 is read from the data storage unit 103. Then, using this data, the absolute position of each element is determined by a method similar to the temporary placement. afterwards,
The data of the main arrangement thus obtained is stored in the data storage unit 103 as arrangement data, and the automatic element arrangement is completed.

Next, the above-mentioned main placement constraint generation process (S20)
6) and a specific example of the main placement process (S207),
This will be described with reference to FIG.

In FIG. 3, (a) is a temporary placement process (S2
03) is a conceptual diagram showing the position of each group after
(B) is a conceptual diagram showing the position of each group after the main placement process (S207).

Here, as a result of the wiring congestion degree estimation step (S204) performed after the temporary placement step (S203), it is assumed that the wiring congestion degree of the group A becomes extremely large (FIG. 3A). reference). Therefore, in the placement constraint generation process (S207), by adjusting the utility,
The restrictions on the area of group A are relaxed. As a result, in the main arrangement, the area of the group A becomes larger than that in the temporary arrangement (see FIG. 3B).

As a result of the performance analysis process (S205) after the temporary placement process (S203), the signals output from the group B cannot reach the groups C and I within a desired time, and the timing violation occurs. It is assumed that it will be generated (see FIG. 3A). Therefore, in the main placement constraint generation process (S207), the groups B, C, and I are merged and the shape is changed. As a result, the groups B, C, and I are treated as one group (see FIG. 3B), which increases the degree of freedom in element arrangement in this arrangement and makes it easy to prevent timing violations.

On the other hand, the boundaries of the groups D and E are intricately complicated, and the optimum element layout (that is, layout in which the layout size and the degree of wiring congestion are reduced) during the temporary layout (S203). Have difficulty. Therefore, in the main placement constraint generation process (S207), the groups D and E are merged to facilitate the optimization of element placement in the main placement process (see FIG. 3B).

Further, the group H is included in the group G, which causes a meaningless temporary placement constraint (see FIG. 3A). Therefore, this placement constraint generation process (S2
In 07), the group H and the group I are merged to facilitate optimization of element placement in the main placement process (see FIG. 3B).

As described above, in the automatic element placement method according to this embodiment, data such as component data, connection information, and performance constraints are not externally input to determine placement constraints as they are. Is used to determine the temporary placement constraint, and the final placement constraint is determined using the temporary placement data, the wiring congestion degree estimation data, and the performance analysis data generated based on the temporary placement constraint. .

Therefore, according to the automatic element arranging method of this embodiment, the optimization problem can be simplified, so that the optimization efficiency can be increased, the layout size and the wiring congestion degree can be reduced, and the performance can be improved. It is effective for the security of. Further, in the temporary placement step (S203), since the same method as the main placement (S207) (for example, the mini-cut method) is used, the accuracy of the temporary placement can be increased and the main placement constraint can be optimized. Can be promoted.

[0054]

As described in detail above, according to the present invention, there is provided an automatic element arranging method capable of reducing the layout size even in a large-scale circuit and ensuring the performance. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of an apparatus that executes an automatic element placement method according to an embodiment of the present invention.

FIG. 2 is a flow chart schematically showing a procedure of automatic element placement according to the embodiment shown in FIG.

3A and 3B are diagrams for explaining a specific example of the main placement constraint generation process and the main placement process shown in FIG. 2, where FIG. 3A is a conceptual diagram showing the position of each group after temporary placement, and FIG. FIG. 3 is a conceptual diagram showing the position of each group after the main arrangement.

[Explanation of symbols]

 Reference numeral 101 control unit 102 input / output unit 103 data storage unit 104 placement constraint generation unit 105 placement unit 106 wiring congestion degree estimation unit 107 performance analysis unit

Claims (2)

[Claims] 1. A temporary placement process for performing a temporary device placement for each device, and a temporary wiring route for each device placed in this temporary placement process is determined to estimate the congestion degree of these wiring routes. Wiring congestion degree estimation process, a performance analysis process of performing a performance analysis for each element placed in the temporary placement process, based on the results of the temporary placement process, the wiring congestion degree estimation process and the performance analysis process, Based on the final placement constraint generation process that determines the final grouping of each element and generates the final placement constraint of each group, and the final placement constraint generated in this real placement constraint generation process, An automatic element placement method comprising: a main placement process for performing various element placements; 2. A provisional placement constraint generation process for dividing each element into a provisional group and generating a placement constraint of each group as a provisional placement constraint, the provisional placement generated in the provisional placement constraint creation process. The automatic element placement method according to claim 1, wherein the temporary placement step is performed using a constraint.