JP3587184B2 - Clock distribution circuit with clock tree structure - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock distribution circuit having a clock tree structure and a method for designing the same, and more particularly, to a clock distribution circuit capable of reducing clock skew in a semiconductor integrated circuit and reducing circuit size and power consumption, and a method for designing the same.
[0002]
[Prior art]
2. Description of the Related Art In a semiconductor integrated circuit, a clock signal from one oscillator is distributed to drive many circuits such as flip-flops in many cases. In order to speed up the operation of such a synchronous circuit, it is necessary to reduce clock skew as much as possible.
[0003]
A conventional distribution circuit having an H-tree structure distributes such a clock signal to a large number of circuits. In the H-tree structure, as shown in FIG. 2, a clock signal is applied from a clock generator to the center of an H-shaped circuit, and circuits that are orthogonal to the ends of the straight circuits on both sides of the H-shape are further connected. A circuit having a tree structure in which an H-shaped circuit in the center portion is repeatedly combined with a circuit which is orthogonal to the end of this orthogonal circuit, and the circuit which is orthogonal to the circuit is repeated. The end of the linear circuit is positioned at the center of the next linear circuit, and the circuit is branched so that clock skew does not occur. Usually, a clock driver is arranged at each branch point. Although this H-tree structure is effective for adjusting clock skew, it is necessary to arrange a clock driver at a position that is not actually necessary so that the signal propagation time of each branched circuit is the same. However, installation of a large number of redundant clock drivers causes problems in terms of the circuit scale and power consumption of the integrated circuit.
[0004]
As another conventional clock distribution circuit design method that does not use the H-tree structure, there is CTS (Clock Tree Synthesis). The CTS uses a computer to provide a wiring path that minimizes clock skew from a clock signal generator to a circuit to which a clock signal is distributed in consideration of the influence of a wiring length, a resistance, a capacitance, and an intervening clock driver or the like. Although it is not necessary to provide a redundant clock driver in the determination method, it has been difficult to sufficiently reduce clock skew.
[0005]
[Problems to be solved by the invention]
In the conventional clock distribution circuit using the H-Tree structure, the circuit scale and power consumption of the integrated circuit have become problems due to a large number of redundant clock drivers. On the other hand, in the design of a clock signal distribution circuit using CTS, it has been difficult to sufficiently reduce clock skew.
[0006]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock distribution circuit having a clock tree structure and a method of designing the clock distribution circuit that can sufficiently reduce clock skew without providing a redundant clock driver.
[0009]
In the clock distribution circuit according to the clock tree structure of the present invention, the upper stage (1 in FIG. 1) near the clock signal generator has an H-tree structure (15 in FIG. 1),
The lower stage (2 in FIG. 1), which is a part other than the upper stage, has a structure determined by clock tree synthesis, and the lower end clock driver at each end of the H-tree structure of the upper stage is: The H-tree structure is characterized by being arranged in a band-shaped region (3 in FIG. 1) extending in one direction with respect to the end of the H-tree structure.
[0010]
In the clock distribution circuit having the clock tree structure of the present invention, the upper stage (1 in FIG. 1) near the clock signal generator has an H-tree structure (2 in FIG. 1).
The lower stage, which is a portion other than the upper stage, has a structure determined by clock tree synthesis, and extends in one direction at each end of the H-tree structure of the upper stage (4 in FIG. 3). Is divided into a plurality of small areas (5 and 6 in FIG. 3) equally divided in the one direction, and a clock driver directly connected to an end of the H-tree structure of the upper stage is provided at the center of the plurality of small areas. The clock driver of the next stage after the clock driver directly connected to the terminal (5 in FIG. 3) is disposed in any of the plurality of small areas so as not to overlap with another clock driver. It is characterized by a structure.
[0013]
In the method of designing a clock distribution circuit based on the clock tree structure according to the present invention, after the upper stage (1 in FIG. 1) near the clock signal generator is determined as the H-tree structure (15 in FIG. 2),
Using the H-tree structure as fixed wiring, a lower stage (2 in FIG. 1), which is a part other than the upper stage, is determined by clock tree synthesis, and each terminal of the H-tree structure in the upper stage is determined. The clock driver is arranged in a band-shaped area (3 in FIG. 1) extending in one direction with respect to the end of the H-tree structure.
[0014]
In the method of designing a clock distribution circuit based on the clock tree structure according to the present invention, after the upper stage (1 in FIG. 1) near the clock signal generator is determined as the H-tree structure (15 in FIG. 2),
Using the H-tree structure as fixed wiring, a lower stage (2 in FIG. 1), which is a part other than the upper stage, is determined by clock tree synthesis, and each terminal of the H-tree structure in the upper stage is determined. The area (4 in FIG. 3) extending in one direction is divided into a plurality of small areas (5 and 6 in FIG. 3) equally divided in the one direction, and directly divided into the ends of the H-tree structure in the upper stage. The clock driver to be connected is arranged at the one located at the center of the plurality of small areas (5 in FIG. 3), and the clock driver at the next stage of the clock driver directly connected to the terminal is not overlapped with another clock driver. And a structure arranged in any one of the plurality of small areas.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a diagram schematically showing a clock distribution circuit of a semiconductor integrated circuit according to an embodiment of the present invention.
[0017]
In FIG. 1, a clock driver 11 directly receives a clock signal from a clock signal generator (not shown), branches the clock signal, and sends it to two clock drivers 12. Each of the clock drivers 12 branches and sends out a clock signal to two clock drivers 13, and each of the clock drivers 13 branches and sends a clock signal to two clock drivers.
[0018]
That is, the clock drivers 11 to 14 constitute a clock tree, the clock driver 11 constitutes a first stage, and the clock drivers 12, 13 and 14 respectively comprise a second stage, a third stage and a fourth stage. Make up the eyes.
[0019]
In the present embodiment, the upper stage 1 of the first and second stages is configured by H-Tree, and the lower stage 2 of the third and fourth stages is configured by CTS.
[0020]
FIG. 2 is a diagram showing an arrangement of the clock distribution circuit on the semiconductor integrated circuit. The clock drivers 11 and 12 constitute an H-tree 15 indicated by thick lines, and the clock drivers 13 and 14 are constituted by CTS. However, unlike the schematic diagram of FIG. 1, one clock driver 12 branches and sends out a clock signal to four clock drivers 13.
[0021]
Further, the arrangement position is limited so that the clock drivers 13 and 14 generated by the CTS are contained only in the region 3, and the connection between the end of the H-Tree 15 and the clock drivers 13 and 14 generated by the CTS is performed simultaneously with the arrangement. It should be connected or connected by simple wiring such as only one direction.
[0022]
In the design of the clock distribution circuit of the present embodiment, the H-tree 15 including the clock drivers 11 and 12 is arranged and determined according to the designer's judgment even if a computer is used by CAD (computer-aided design). At this time, the end of H-tree 15 is located in region 3. The region 3 is defined for each end of the H-tree 15 so that the clock drivers 13 and 14 connected to the lower end of one of the H-trees 15 can be connected to the wiring in one wiring direction with respect to the end. It is an area located. In FIG. 2, one region 3 is provided for each of the two ends because two ends of the H-tree 15 are in the same wiring direction.
[0023]
Next, using the H-tree 15 thus determined as fixed wiring, the clock drivers 13 and 14 are determined by CTS using a computer under the condition that these are positioned in the area 3. By arranging the clock drivers 13 and 14 in the region 3, the wiring between the end of the H-tree 15 and the clock driver 13 can be simplified to prevent the wiring length from varying, and the wiring between the clock drivers 13 and 14 can be prevented. Can be simplified, and wiring of clock trees that are accurately synchronized can be easily performed.
[0024]
In the H-Tree portion of the clock distribution circuit shown in FIG. 2, the clock driver is fixedly arranged and the clock wiring is fixedly wired, so that the effect of reducing the skew of the clock signal is large. Further, in the CTS portion, it is possible to design such that only a clock driver as necessary is arranged, and it is not necessary to prepare a redundant clock driver. In FIG. 2, the clock driver 13 is connected to all the terminals of the H-tree 15, but the clock driver 13 is not disposed at some terminals depending on the arrangement of circuits such as flip-flops that require a clock signal. Such a CTS execution result may be obtained.
[0025]
In FIG. 1, the number of clock distribution stages configured by the H-Tree is two, and the number of stages distributed by the CTS is two. However, each of the stages may be configured by an arbitrary number of stages. The number of distributions in each stage may be arbitrary.
[0026]
Although the arrangement position of the clock drivers 13 and 14 in the region 3 in the CTS in FIG. 2 is not limited, even if the arrangement of each stage distributed by the CTS is specified separately as in FIG. Good. That is, in FIG. 3, the band-shaped region 4 in one wiring direction is equally divided into five small regions in one wiring direction with respect to the end of the H-tree, and the clock driver 13 is arranged in the central small region 5. One or zero clock drivers 14 are arranged in each of the other small areas 6 to facilitate adjustment of clock skew.
[0027]
In FIG. 2, the H-Tree 15 is a combination of the shapes of H. However, if the wiring length from the branch point to the next branch point or terminal or the delay time of the signal is equal in each stage, any H-Tree 15 can be used. Shape may be sufficient. For example, three or more branches may be made at one branch point, or the wiring may be in a diagonal direction other than vertical and horizontal. However, in the execution of CTS, it is a condition that H-tree is fixed wiring.
[0028]
【The invention's effect】
As described above, by configuring the upper stage of the clock tree with the H-Tree structure and the lower stage with the CTS, a redundant configuration is achieved as compared with the case where the entire clock tree is configured with the H-Tree to the end. No clock driver is required, and the number of clock drivers placed at the end can be reduced, so that the effect of reducing the circuit scale and power consumption can be obtained, and the skew adjustment becomes easier compared to the case where all are configured by CTS. , Sufficient clock skew adjustment is obtained.
[Brief description of the drawings]
FIG. 1 is a diagram schematically illustrating a clock distribution circuit having a clock tree structure according to an embodiment of the present invention.
FIG. 2 is a diagram showing an arrangement of a clock distribution circuit based on a clock tree structure shown in FIG. 1 on an integrated circuit.
FIG. 3 is a diagram in which clock drivers 13 and 14 are arranged in small regions 5 and 6 obtained by dividing the region 3 shown in FIG.
[Explanation of symbols]
1 Upper stage 2 Lower stage 3 Areas 11 to 14 Clock driver 15 H-tree

Claims (4)

The upper stage near the clock signal generator has an H-tree structure,
  The lower stage, which is a part other than the upper stage, has a structure determined by clock tree synthesis, and a clock driver connected to a lower end of each of the upper H-tree structures has a lower end than the upper H-tree structure. A clock distribution circuit having a clock tree structure, wherein the clock distribution circuit has a structure arranged in a band-shaped region extending in one direction. The upper stage near the clock signal generator has an H-tree structure,
The lower stage, which is a part other than the upper stage, has a structure determined by clock tree synthesis, and an area extending in one direction at each end of the H-tree structure of the upper stage is defined in the one direction. A clock driver which is divided into a plurality of equally divided small areas and which is directly connected to an end of the H-tree structure of the upper stage is arranged at a center of the plurality of small areas, and a clock driver which is directly connected to the end. A clock distribution circuit having a clock tree structure, wherein a clock driver at the next stage of the driver is arranged in any of the plurality of small areas so as not to overlap with another clock driver . After determining the upper stage near the clock signal generator as the H-tree structure,
  A clock driver in which the H-tree structure is fixed wiring and a lower stage other than the upper stage is determined by clock tree synthesis, and a lower end of each of the ends of the H-tree structure of the upper stage is connected to the lower side. Are arranged in a band-like region extending in one direction with respect to the end of the H-tree structure. After deciding the upper stage near the clock signal generator as the H-tree structure,
Using the H-tree structure as a fixed wiring, a lower stage, which is a part other than the upper stage, is determined by clock tree synthesis, and extends in one direction at each end of the H-tree structure of the upper stage. The area is divided into a plurality of small areas equally divided in the one direction, and a clock driver directly connected to an end of the H-tree structure in the upper stage is arranged at a center of the plurality of small areas. A clock distribution by a clock tree structure, wherein a clock driver at the next stage of a clock driver directly connected to the terminal is arranged in any of the plurality of small areas so as not to overlap with another clock driver. Circuit design method .

Images