JP2003078014A - Clock distribution circuit by clock tree structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce skew, circuit scale and power consumption in clock distribution of a semiconductor integrated circuit. SOLUTION: Clock drivers 11-14 constitute a clock tree wherein the clock driver 11 constitutes the first stage and the clock drivers 12, 13 and 14 constitute the second, third and fourth stages, respectively. Upper states, i.e., the first and second stages, are constituted of H-Tree 15 whereas the lower stages, i.e., the third and fourth stages, are constituted of CTS. The placing position is limited such that the clock drivers 13 and 14 generating the CTS are contained only in an area 3 and the end of the H-Tree is connected with the clock drivers 13 and 14 generated by the CTS simultaneously with placement or through simple unidirectional routing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock distribution circuit having a clock tree structure and a design method thereof,
In particular, the present invention relates to a clock distribution circuit that can reduce clock skew in a semiconductor integrated circuit, and can reduce circuit scale and power consumption, and a design method thereof.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, a clock signal from one oscillator is often distributed to drive a large number of circuits such as flip-flops in synchronization. In order to speed up the operation of such a synchronous circuit, it is necessary to reduce the clock skew as much as possible.

A conventional distribution circuit having an H-tree structure is used to distribute such a clock signal to a large number of circuits. With the H-tree structure, as shown in FIG. 2, a clock signal is applied from the clock oscillator to the center of the H-shaped circuit, and circuits that are orthogonal to the ends of the linear circuits on both sides of the H-shape are further connected, By repeating the connection of the circuit orthogonal to this to the end of this orthogonal circuit, a tree-shaped circuit in which H-shaped circuits that are gradually smaller centered on the H-shaped circuit in the center are combined is a straight line. The end of the circuit is positioned at the center of the next linear circuit to branch the circuit to prevent clock skew. Normally, a clock driver is arranged at each branch point. This H-tree structure is effective for adjusting the clock skew, but it is necessary to place the clock driver at an unnecessary position so that the signal propagation time of each branched circuit is the same. However, installing a large number of redundant clock drivers causes a problem in terms of circuit scale and power consumption of the integrated circuit.

Another conventional clock distribution circuit designing method that does not use the H-tree structure is CTS (clock tree synthesis). The CTS uses a computer to determine a wiring path that minimizes the clock skew from the clock signal oscillator to the circuit to which the clock signal is distributed, in consideration of the influence of the wiring length, resistance, capacitance, and a clock driver interposed in the middle. Although it is not necessary to provide a redundant clock driver in the determination method, it is difficult to sufficiently reduce the clock skew.

[0005]

In the conventional clock distribution circuit using the H-Tree structure, the circuit scale and power consumption of the integrated circuit have been problems due to a large number of redundant clock drivers. On the other hand, it is difficult to sufficiently reduce the clock skew in the design of the CTS clock signal distribution circuit.

An object of the present invention is to provide a clock distribution circuit having a clock tree structure which can sufficiently reduce clock skew without providing a redundant clock driver, and a design method thereof.

[0007]

In the clock distribution circuit having the clock tree structure of the present invention, the upper stage (1 in FIG. 1) near the clock signal generator has an H-tree structure (15 in FIG. 2). The lower stage (2 in FIG. 1) other than the upper stage has a structure determined by clock tree synthesis.

In the clock distribution circuit according to the clock tree structure of the present invention, the upper stage (1 in FIG. 1) near the clock signal generator has the Htree structure (15 in FIG. 1), and the parts other than the upper stage. The lower stage (2 in FIG. 1) is determined by clock tree synthesis so that the clock driver is located in the region (3 in FIG. 2) where the clock driver is easily connected to the H-tree structure circuit of the upper stage. It is characterized by having a structure.

In the clock distribution circuit according to the clock tree structure of the present invention, the upper stage (1 in FIG. 1) near the clock signal generator has the H-tree structure (15 in FIG. 1), except for the upper stage. The lower stage (2 in FIG. 1) which is a part of the structure is a structure determined by clock tree synthesis, and the clock driver connected to the lower end of each H-tree structure of the upper stage is the H tree structure. The structure is arranged in a band-shaped region (3 in FIG. 1) extending in one direction with respect to the end.

In the clock distribution circuit according to the clock tree structure of the present invention, the upper stage (1 in FIG. 1) near the clock signal generator has an H-tree structure (2 in FIG. 1),
The lower stage, which is a part other than the upper stage, has a structure determined by clock tree synthesis and extends in one direction at each end of the H-tree structure of the upper stage (4 in FIG. 3). Is divided into a plurality of small areas (5 and 6 in FIG. 3) equally divided in the one direction, and a clock driver directly connected to the end of the H-tree structure of the upper stage is provided in the center of the plurality of small areas. The clock driver of the next stage of the clock driver directly connected to the end (5 in FIG. 3) is arranged in any of the plurality of small areas so as not to overlap with other clock drivers. It is characterized by a structure.

In the method of designing a clock distribution circuit according to the clock tree structure of the present invention, after the upper stage (1 in FIG. 1) near the clock signal generator is determined as the H-tree structure (15 in FIG. 2). The H-tree structure is used as a fixed wiring, and a lower stage (2 in FIG. 1) other than the upper stage is determined by clock tree synthesis.

In the method of designing the clock distribution circuit according to the clock tree structure of the present invention, after the upper stage (1 in FIG. 1) near the clock signal generator is determined as the H-tree structure (15 in FIG. 2). , In the region (3 in FIG. 2) where the clock driver easily connects the lower stage other than the upper stage with the H-tree structure as fixed wiring to the circuit of the upper stage H-tree structure. It is characterized in that the position is determined by clock tree synthesis.

According to the method of designing a clock distribution circuit having the clock tree structure of the present invention, after determining the upper stage (1 in FIG. 1) near the clock signal generator as the Htree structure (15 in FIG. 2). , The lower stage (2 in FIG. 1) other than the upper stage is determined by clock tree synthesis using the H-tree structure as fixed wiring, and the end of the H-tree structure of the upper stage is determined. It is characterized in that the clock driver connected to the lower order for each is arranged in a strip-shaped region (3 in FIG. 1) extending in one direction with respect to the end of the H-tree structure.

In the method of designing the clock distribution circuit according to the clock tree structure of the present invention, after the upper stage (1 in FIG. 1) near the clock signal generator is determined as the H-tree structure (15 in FIG. 2). , The lower stage (2 in FIG. 1) other than the upper stage is determined by clock tree synthesis using the H-tree structure as fixed wiring, and the end of the H-tree structure of the upper stage is determined. Each of the regions (4 in FIG. 3) extending in one direction is divided into a plurality of small regions (5, 6 in FIG. 3) equally divided in the one direction, and is divided at the end of the H-tree structure of the upper stage. The directly connected clock driver is arranged at the center of the plurality of small areas (5 in FIG. 3), and the clock driver at the next stage of the clock driver directly connected to the end is connected to another clock driver. Characterized in that it is a structure in which any one of said plurality of small areas so as not to overlap.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram schematically showing a clock distribution circuit of a semiconductor integrated circuit according to an embodiment of the present invention.

In FIG. 1, the clock driver 11 is
A clock signal is directly input from a clock signal oscillator (not shown), branched, and sent to the two clock drivers 12. Each clock driver 12 branches and sends a clock signal to two clock drivers 13, and each clock driver 13 branches and sends a clock signal to two clock drivers.

That is, the clock drivers 11-14
Form a clock tree, the clock driver 11 forms a first stage, and the clock drivers 12, 13 and 14 form a second stage, a third stage and a fourth stage, respectively.

In this embodiment, the upper stage 1 of the first and second stages is composed of H-Tree, and the lower stage 2 of the third and fourth stages is composed of CTS. There is.

FIG. 2 is a diagram showing the arrangement of the clock distribution circuit on the semiconductor integrated circuit. The clock drivers 11 and 12 form an H-tree 15 indicated by a thick line,
The clock drivers 13 and 14 are composed of CTS. However, unlike the schematic diagram of FIG. 1, one clock driver 12 has four clock drivers 13.
The clock signal is branched and sent to.

Further, the arrangement positions are limited so that the clock drivers 13 and 14 generated by CTS are contained only in the region 3, and the connection between the end of the H-Tree 15 and the clock drivers 13 and 14 generated by CTS is It should be connected at the same time as the arrangement or by simple wiring such as only in one direction.

In the design of the clock distribution circuit of this embodiment, the H-tree 15 including the clock drivers 11 and 12 is arranged and determined according to the designer's judgment even if the computer is used by CAD (computer-aided design). To do. At this time, the end of H-tree 15 is located in the region 3. This area 3 is H-tree15
Of each H-tr
This is a region located so that the clock drivers 13 and 14 connected to the lower end of the end of the ee 15 can be connected to the wiring in one wiring direction with respect to the end thereof. In FIG. 2, Ht
Since two ends of the ree 15 are on the same wiring direction, one region 3 is provided for the two ends.

Next, the H-tree1 thus determined
Clock driver 13 and 1 with 5 as fixed wiring
4 is determined by CTS using a computer under the condition that they are located in region 3. Clock driver 1
By arranging 3 and 14 in the region 3, it is possible to simplify the wiring between the end of the H-tree 15 and the clock driver 13 and prevent the wiring length from varying, and the wiring between the clock drivers 13 and 14 is also simple. This makes it easy to wire clock trees that are accurately synchronized.

The H-Tre of the clock distribution circuit shown in FIG.
In the portion e, the clock driver is fixedly arranged and the clock wiring is fixedly wired, and the skew reduction effect of the clock signal is great. Further, in the CTS part, it is possible to design so that only the clock driver according to need is arranged, and it is not necessary to prepare a redundant clock driver. Although the clock driver 13 is connected to all the ends of the H-tree 15 in FIG. 2, the clock driver 13 is not arranged at some ends depending on the arrangement of circuits such as flip-flops that require a clock signal. In some cases, such a CTS execution result may result.

In FIG. 1, the number of clock distribution stages formed by the H-Tree is two and the number of stages distributed by the CTS is two, but each number of stages may be any number. Also, the number of distributions in each stage may be arbitrary.

Although the arrangement positions of the clock drivers 13 and 14 in the CTS in the area 3 are not limited in FIG. 2, the arrangement of each stage distributed by the CTS is designated separately as shown in FIG. You may. That is, in FIG.
With respect to the end of the tree, the strip-shaped area 4 in one wiring direction is equally divided into five small areas in the one wiring direction, the clock driver 13 is arranged in the small area 5 in the center, and each of the other small areas 6 is divided. Arranging one or zero clock drivers 14 facilitates adjustment of clock skew.

In FIG. 2, the H-Tree 15 is a combination of H shapes, but in each stage,
Any shape may be used as long as the wiring length from the branch point to the next branch point or the end or the signal delay time is the same. For example, one branch point may be branched into three or more lines, and the wiring may be in an oblique direction other than the vertical and horizontal directions. However, CTS
In the execution of, H-tree must be fixed wiring.

[0028]

As described above, by constructing the upper stage of the clock tree with the H-Tree structure and the lower stage with the CTS, the H-tree reaches the end of the entire clock tree.
Compared with the tree configuration, redundant clock drivers are not required and the number of clock drivers placed at the end can be reduced, so that the effect of reducing the circuit scale and power consumption can be obtained. Skew adjustment becomes easier than in the case of configuration, and sufficient clock skew adjustment can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing an outline of a clock distribution circuit having a clock tree structure according to an embodiment of the present invention.

FIG. 2 is a diagram showing an arrangement of a clock distribution circuit having the clock tree structure shown in FIG. 1 on an integrated circuit.

FIG. 3 is a diagram showing subregions 5 and 6 obtained by dividing the region 3 shown in FIG.
It is the figure which arranged the clock drivers 13 and 14 in FIG.

[Explanation of symbols]

1 upper level 2 lower level 3 areas 11-14 Clock driver 15 H-tree

Claims (8)

[Claims] 1. An upper stage near a clock signal generator has an H-tree structure, and a lower stage other than the upper stage has a structure determined by clock tree synthesis. A clock distribution circuit with a clock tree structure. 2. A circuit having an H-tree structure in an upper stage near a clock signal generator has a H-tree structure, and a lower stage other than the upper stage has a clock driver having a H-tree structure in the upper stage. A clock distribution circuit with a clock tree structure characterized by having a structure determined by clock tree synthesis so that it is located in an area that is easy to connect to. 3. The upper stage near the clock signal generator has an H-tree structure, and the lower stages other than the upper stage have a structure determined by clock tree synthesis and the upper stage. The clock distribution circuit according to the clock tree structure is characterized in that the clock driver connected to the lower end of each of the H-tree structures is arranged in a band-shaped region extending in one direction with respect to the end of the H-tree structure. . 4. The upper stage near the clock signal generator has an H-tree structure, and the lower stages other than the upper stage have a structure determined by clock tree synthesis and the upper stage. A clock driver that divides the region extending in one direction at each end of the H-tree structure of the first stage into a plurality of small regions equally divided in the one direction and connects directly to the end of the H-tree structure of the higher stage. Is arranged in the center of the plurality of small areas, and any one of the plurality of small areas is provided so that the clock driver in the next stage of the clock driver directly connected to the end does not overlap with other clock drivers. A clock distribution circuit having a clock tree structure characterized by being arranged. 5. The Ht after the upper stage of the portion near the clock signal generator is determined as the Htree structure.
A method of designing a clock distribution circuit having a clock tree structure, characterized in that a ree structure is used as fixed wiring and a lower stage other than the upper stage is determined by clock tree synthesis. 6. The Ht after the upper stage of the portion close to the clock signal generator is determined as the Htree structure.
The ree structure is used as fixed wiring, and the clock driver drives the lower stage other than the upper stage to the H-tr of the upper stage.
A method of designing a clock distribution circuit having a clock tree structure, characterized in that it is determined by clock tree synthesis so that it is located in a region that is easily connected to a circuit having an ee structure. 7. After the upper stage near the clock signal generator is determined as an H-tree structure, the H-tree structure is used as a fixed wiring, and the lower stages other than the upper stage are clocked. A clock driver that is determined by tree synthesis and that is connected to the lower end of each of the upper H-tree structure ends is arranged in a strip-shaped region extending in one direction with respect to the end of the H-tree structure. Design method of clock distribution circuit by clock tree structure. 8. After the upper stage near the clock signal generator is determined as an H-tree structure, the H-tree structure is used as fixed wiring, and the lower stages other than the upper stage are clocked. The region which is determined by tree synthesis and extends in one direction at each end of the H-tree structure of the upper stage is divided into a plurality of small regions equally divided in the one direction, and the H-stage of the upper stage is divided. A clock driver directly connected to the end of the tree structure is arranged at the center of the plurality of small areas, and a clock driver in the next stage of the clock driver directly connected to the end is not overlapped with other clock drivers. 2. A method for designing a clock distribution circuit having a clock tree structure, characterized in that the structure is arranged in any of the plurality of small areas.