JP2523702B2 - Automatic wiring method for semiconductor integrated circuits - Google Patents

Description

The present invention relates to an automatic wiring method for a semiconductor integrated circuit in which automatic wiring is performed by a single-layer wiring, and a purpose is to eliminate unnecessary wiring trials and speed up automatic wiring. In an automatic wiring method of a semiconductor integrated circuit in which a plurality of points to be wired are automatically wired by a single layer wiring, a wiring area having the plurality of points to be wired on a side is divided into a plurality of rectangular areas, and A pair of wiring points corresponding to the plurality of wiring points are provided on the sides of each of the plurality of rectangular areas, and a straight line intersects between the pair of wiring points in each of the plurality of rectangular areas. After determining whether or not the single-layer wiring is possible based on the presence or absence of the wiring, the wiring determined to be the single-layer wiring between the plurality of wiring points is automatically wired.

[Industrial applications]

The present invention relates to an automatic wiring method for a semiconductor integrated circuit, and more particularly to an automatic wiring method for a semiconductor integrated circuit that performs automatic wiring by single-layer wiring.

Generally, in a semiconductor integrated circuit, cells (circuit blocks) such as flip-flops, NANDs, and NORs are separately formed on a semiconductor chip, and wiring in the cells is performed to form circuit elements,
The plurality of cells are connected by wiring, and automatic wiring for setting the wiring inside and between the cells by a computer has been conventionally performed.

It takes time to execute the above-mentioned program for automatic wiring, and there is a demand for higher speed.

[Conventional technology]

Conventionally, when performing automatic wiring, the wiring area is treated as a set of switch boxes. The switch box is a rectangular wiring area as shown in FIG. 8, and points A ₁ , A ₂ , B ₁ , B ₂ , C ₁ , C ₂ to be wired are arranged on the side thereof.

For example, as shown in FIG.
4 to 4 are arranged, the wiring area 5 between
It can be considered as a set of switch boxes 6 to 10 shown in FIG.

Conventionally, wiring is performed in the above switch box based on a wiring algorithm such as a line search method or a maze method.

[Problems to be solved by the invention]

For example, in the switch box shown in FIG. 8, wiring is performed between points A ₁ and A _2, between B ₁ and B _{2, and} between C ₁ and C ₂ , which should be wired only by one-layer wiring. In this case, first wire between A ₁ and A ₂ ,
Next, the points B ₁ and B ₂ are wired to determine whether or not this wiring intersects the points A ₁ and A ₂ wiring. If they do not intersect, point C ₁ , C
Wiring between the _two is determined whether or not this intersects with the wiring between the points A ₁ and A ₂ and the wiring between the points B ₁ and B ₂ . If crossed, point C ₁ , C
The wiring between the _two is searched by another route, and if it is not found, the wiring between the points A ₁ and A ₂ that does not intersect with the wiring between the points C ₁ and C ₂ is searched.

However, in the example of FIG. 8, points A ₁ and A ₂ , points B ₁ and B ₂ , points C ₁ and C
_In principle, one-layer wiring between _two cannot be performed. Despite this, the conventional automatic wiring method has a problem that wasteful wiring trials are continued endlessly and the time for executing the automatic wiring becomes long. This also has the same problem when the in-cell wiring is performed by the single-layer wiring.

The present invention has been made in view of the above points, and an object of the present invention is to provide an automatic wiring method for a semiconductor integrated circuit that can eliminate unnecessary wiring trials and speed up automatic wiring.

[Means for solving problems]

The automatic wiring system for a semiconductor integrated circuit according to the present invention has a plurality of points (A ₃ , A ₄ , B ₃ , B ₄ ,
In an automatic wiring method of a semiconductor integrated circuit in which a single layer wiring is automatically provided between C ₃ and C ₄ ), a plurality of wiring points (A ₃ , A ₄ , B ₃ , B ₄ , C ₃ , C ₄ ) by dividing the wiring area (5) a plurality of rectangular regions having on the side (6-10), a plurality of rectangular areas (6-10) It should be a plurality of lines on the respective sides (a _3, a _{4, B 3, B 4,} C 3, C 4) to the corresponding points to be wired pairs with ([alpha] 1, .beta.1, [alpha] 2, .gamma.2) a provided plurality of rectangular areas (6-10), respectively in one another in 1 from the presence or absence of the intersection of the straight lines (a1, b1, c1) connecting the pair of wiring points
After semi-deciding whether or not layer wiring is possible, automatically route the wiring that is determined to be one-layer wiring between multiple wiring points (A ₃ , A ₄ , B ₃ , B ₄ , C ₃ , C ₄ ). To do.

[Action]

In the method of the present invention, whether or not wiring is possible is determined by intersecting straight lines in each of the plurality of rectangular regions (6 to 10), and only those that can be wired are automatically routed based on the determination result.
Therefore, unnecessary wiring trials are not performed, and the time required for automatic wiring is shortened.

〔Example〕

1 (A) and 1 (B) are flowcharts of an embodiment of an automatic wiring method for a semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram of a system for realizing the method according to the present invention.

In FIG. 2, 20 is a CPU, and 21 to 24 are storage devices. The memory device 21 stores a program for performing the process of the automatic wiring method shown in FIGS. 1 and 2, and this program is read by the CPU 20 at each step and executed by the CPU 20.

The storage device 22 stores logical information that defines a logical inter-cell connection identified by the cell name of each of a plurality of cells formed on a semiconductor chip and the terminal name of each cell, and this logical information is necessary. Is read by the CPU 20 in accordance with

The memory device 23 stores the shape, size, terminal position of each of the plurality of cells, and the positional relationship between the plurality of cells, that is, graphic information indicating each cell position on the semiconductor chip, and the graphic information is stored as necessary. It is read by the CPU 20.

The storage device 24 is used as a work area and stores wiring data obtained by executing the program.

In FIG. 1 (A), first, at step 30, a wiring feasibility is judged. The process for determining whether or not wiring is possible is the algorithm shown in FIG.

For example, when wiring between cells 1 to 4 shown in FIG. 10, the wiring area 5 is divided into switch boxes 6, 7, 8, 9, and 10 in step 40 in FIG. 1 (B).

After that, the number of wires for each switch box is counted from the types (A, B, C, etc.) of wiring points for each of the switch boxes 6 to 10 (step 41).

Next, an arbitrary switch box is selected and it is determined whether or not the number of wires is 2 or more (step 42).

For example, in the case of the switch box 9, since the number of wirings is 2, the process proceeds to step 43, where points to be wired are generated. In this case, since the points A ₃ and A ₄ and the points B ₃ and B ₄ are wired, the points A ₄ and B _{4 are respectively provided} on the side 9a shown in FIG. 3 (A) in the switch box 9. It is necessary to generate points to be wired.

When the points α1 and β1 are generated on the side 9a, the X coordinate is α1 <
Since there are cases of β1 shown in FIG. 3 (B) and cases of α1> β1 shown in FIG. 3 (C), a straight line between points A ₄ and α1 and a straight line between points B ₄ and β1 Fig. 3 (C) that does not intersect
The points α1 and β1 in the relationship shown in are adopted.

Next, an arbitrary switch box is selected and it is determined whether the number of wires is 2 or more (step 42).

For example, in the case of switch box 10, between points A ₃ and A ₄ and point C
_{Since 3} and C ₄ are wired, it is necessary to generate points to be wired with points A ₃ and C ₄ on the side 10a shown in FIG. 4A in the switch box 10.

When the points α2 and γ2 are generated on the side 10a, the Y coordinate is α2.
Since there are cases shown in FIG. 4 (B) where> γ2 and cases shown in FIG. 4 (C) where α2 <γ2, the points A ₃ and α2
Linear and point C ₄ between the point of the relationship shown in FIG. 4 (B) that the straight line does not intersect between .gamma.2 [alpha] 2, to adopt a .gamma.2.

After execution of step 43 or when it is determined in step 42 that the number of wires is less than 2, the process proceeds to step 44, and the point to be wired is set in the adjacent switch box. For example, when the points α1 and β1 to be wired are generated in the switch box 9, the side 9a is set in the shared switch box 8.
In the case of switch box 6, switch box 6,
Side of switch box 8 shared by 8 (X coordinate is arbitrary)
Set the point corresponding to the point B ₃ at.

After this, it is judged whether or not the points to be wired have been set for all the switch boxes (step 45),
If not completed, the process proceeds to step 41. If this is completed, the routine proceeds to step 46.

As a result, as shown in FIG. 5, points to be wired are set in each of the switch boxes 5-10. Of these, only the switch box 8 is shown in FIG. In Fig. 6, a point corresponding to the point B ₃ is provided on each side of the switch box 8.
Point C ₁ corresponding to B ₁ and point C ₃ , Point A ₂ and B corresponding to point A ₄ and B ₄ , point C
A point C ₂ corresponding to ₄ is provided.

In step 46, a straight line connecting each pair of wiring points is obtained for each switch box, and when there are a plurality of straight lines, the presence or absence of these crossings is checked to create a cross table.

For example, in the switch box 8 shown in FIG. 6, the straight line a1
Intersects with the straight line c1, and the straight line b1 intersects with the straight line c1. Therefore, the intersection table shown in FIG. 7 is created. In FIG. 7, “0” indicates no crossing, “1” indicates crossing,
"-" Is an unnecessary part. From this table, between points A ₁ and A ₂ , points B ₁ and
It can be seen that the wiring between B _{2 and} between the points C ₁ and C ₂ cannot be further wired, and that only between the points A ₁ and A _{2 or} between the points B ₁ and B ₂ can be further wired.

Returning to FIG. 1A, in step 31, attention is paid to a straight line without intersection from the intersection table of each switch box. The lengths of continuous straight lines (for example, straight lines a1, a2, and a3 in FIG. 5) are found in adjacent switch boxes, and the length of the continuous straight lines is used as the evaluation function of this wiring. If there is an intersection, one is ignored, the other is regarded as no intersection, and a wiring combination that maximizes the sum of the evaluation functions of all the wirings that do not intersect each other is selected. Of course, at this time, the wirings of the straight lines (for example, the straight lines c1, c2, c3 in FIG. 5) intersecting with each other are ignored.

Thereafter, automatic wiring is performed for the selected wiring combination (step 32). At this time, the wiring extends parallel to the X-axis and the Y-axis, respectively, but the coordinates of the points to be wired generated in steps 43 and 44 (for example, α1, β1, α2, γ2) in order to obtain the wiring path. Is used.

Further, patterning is performed from the data obtained by the automatic wiring process (step 33).

In this way, in step 30, it is determined from the intersection of the straight lines in each of the switch boxes 6 to 10 whether or not each wiring is possible or impossible in one layer wiring, and based on the result of this determination, the one layer wiring is performed. Only those that can be automatically wired.

Therefore, unnecessary wiring trials are not performed, and the time required for automatic wiring is shortened and speeded up.

In the above-mentioned embodiment, the inter-cell wiring has been described as an example, but this is the same for the in-cell wiring in which the single-layer wiring is usually performed, and is not limited to the above-mentioned embodiment.

〔The invention's effect〕

As described above, according to the automatic wiring method for a semiconductor integrated circuit of the present invention, useless wiring trials are eliminated, and automatic wiring can be speeded up, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a flowchart of an embodiment of an automatic wiring method for a semiconductor integrated circuit according to the present invention, FIG. 2 is a block diagram of a system for realizing the method according to the present invention, and FIGS. 3 to 6 show the method according to the present invention. FIG. 7 is a diagram for explaining wiring, FIG. 7 is a diagram showing a cross table, and FIGS. 8 to 10 are diagrams for explaining a switch box. In the figure, 1 to 4 are cells, 5 is a wiring region, 6 to 10 are switch boxes, 30 to 46 are steps, A _{1 to} A ₃ , B _{1 to} B ₃ , C _{1 to} C ₃ , α1, α2 and β1. , β2, γ2 are points to be wired, and a1 to a3, b1, c1 to c3 are straight lines.

Claims (1)

(57) [Claims] 1. An automatic semiconductor integrated circuit for automatically wiring a plurality of wiring points (A ₃ , A ₄ , B ₃ , B ₄ , C ₃ , C ₄ ) on a semiconductor chip with a single-layer wiring. in the wiring method, points to be wired of the plurality _{(a 3, a 4, B} 3, B 4, C 3, C 4) to have on the side wiring region (5) a plurality of rectangular regions (6-10) Into a pair of points corresponding to the points (A ₃ , A ₄ , B ₃ , B ₄ , C ₃ , C ₄ ) to be wired on each side of the rectangular areas (6 to 10). Points to be wired (α1, β1, α2, γ2) are provided, and the straight lines (a1, b1, c1) connecting the points to be wired are formed in each of the plurality of rectangular regions (6 to 10). 1 from the presence or absence of intersection
After determining whether or not layer wiring is possible, the wiring that is determined to be one layer wiring between the plurality of wiring points (A ₃ , A ₄ , B ₃ , B ₄ , C ₃ , C ₄ ) is automatically routed. An automatic wiring method for a semiconductor integrated circuit, comprising: