JPH03124045A - Wiring of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To shorten a wiring route by a method wherein a chip region is divided into a plurality of regions, the wiring route between the regions is decided according to information on a position of an obstacle inside the regions and the wiring route inside the regions is decided by using one part of its interconnection. CONSTITUTION:A chip region 21 is divided into a plurality of circuit regions 22 composed of circuit cells or circuit blocks. Then, points of the same sign stretching over the regions 22 and points of the same sign confined inside the regions 22 are gusted, and an interconnection stretching between the regions is selected. Then, regarding the selected interconnection, a wiring route stretching between the regions is decided by using a line-segment search method by taking into consideration points of another sign which constitute an obstacle in the other regions 22. The points of the same sign inside the regions 22 are wired; one part of an interconnection between the regions which has been already decided at this time is utilized. Thereby, it is possible to prevent an inessential detour interconnection and to shorten the interconnection between the regions.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a wiring method for a standard cell type semiconductor integrated circuit device, and particularly relates to a wiring method using automatic wiring processing using a computer. .

(Prior Art) A standard cell type semiconductor integrated circuit device arranges rectangular circuit cells and circuit blocks having logic functions and memory functions in a chip, and wires the input and output terminals of each circuit cell and circuit block. By doing so, desired circuit operation can be obtained. As circuit cells, we handle relatively small-scale circuits such as NAND gate cells and NOR gate cells.As circuit blocks, we handle ROM, PLA, ALU, and CPU.
It handles circuits that are larger in scale than equal-circuit cells.

By combining circuit cells and circuit blocks in this way, a semiconductor integrated circuit device consisting of a complex and large-scale circuit system can be realized.

FIG. 6 shows a schematic configuration of a semiconductor integrated circuit chip using a general standard cell method. The chip has a plurality of circuit cell rows 41. which are element regions. Wiring area 42 between each circuit cell row. and an input/output circuit area 43 provided in the periphery.
It is divided into

Usually 2 to 3 layers of metal wiring are used for wiring, and water number ■l
Separate layers are assigned to the direction and vertical direction.

When determining the wiring layout in such a semiconductor integrated circuit device by automatic wiring processing using a computer, it is necessary to minimize the area of the integrated circuit and the length of each wiring. Known automatic wiring methods for this purpose include the maze method and the line segment search method. According to these methods, wiring processing can proceed over the entire area of the chip, but there are problems in that unwired areas occur and a large amount of calculation processing time is required. For this purpose, a chip is usually divided into circuit areas consisting of multiple circuit cells or circuit blocks, first, routes between these circuit areas are determined, and then detailed wiring routes are determined for each of these multiple circuit areas. A method has been proposed in which the wiring route is determined over the entire surface of the chip. However, this method alone has the problem that a large number of detour wiring and through holes are generated, and the degree of integration cannot be efficiently increased.

This problem will be explained in more detail using FIG. 5.

The chip is divided into six circuit areas (area 1 to area 6), and points with the same symbol are terminals connected to the same signal. Furthermore, for the sake of simplicity, it is assumed that only two types of wiring grids exist in the vertical and horizontal directions in this circuit area. In this state, consider the case of wiring from A1 to A2 using the line segment search method, for example. Regarding A2, there is only information about which direction it exists, and area 2
゜Since there is no positional information of obstacles existing in area 3, if A1 is taken as the starting point, an arbitrary boundary point, for example, the point marked with an X, will be determined at the boundary between area 1 and area 2. For the first time, information on point B, which is an obstacle in area 2, is obtained, and in order to prevent a collision with point B, the vehicle takes a detour and reaches the boundary point marked with an X between areas 2 and 3. Obtain information on area 3,
Reach A2.

The same applies to A3. Also, wiring routes for A1 and A4 in the same area 1 are similarly determined using the line segment search method.

In this wiring method, when determining a global route on a circuit area, boundary points indicated by X marks are determined without information on other areas, and then detailed wiring routes within the area are determined. . Therefore, as shown in the figure, detour wiring occurs in the wiring between each area, and the wiring inside the area that uses a part of the wiring becomes redundant. There was a problem that effective wiring processing was difficult.

(Problem to be Solved by the Invention) As described above, in the conventional wiring method, when determining the global wiring route between each block, terminal position information within other areas is not accurately referred to. Wiring between regions takes a detour, and wiring within the region that uses part of the detour wiring also becomes redundant. Therefore, there are problems in that the wiring area is inefficiently used and wiring processing aimed at improving the degree of integration is difficult.

An object of the present invention is to provide a wiring method for a semiconductor integrated circuit device to solve such problems.

[Structure of the Invention (Means for Solving the Problems) The present invention has been made in view of the above-mentioned circumstances, and the present invention has been made in view of the above-mentioned circumstances, in which a circuit cell on a semiconductor substrate has a wiring path between input and output terminals of a circuit block by automatic wiring processing. When determining, the semiconductor substrate is divided into a plurality of circuit areas including the circuit cells or the circuit blocks, the positional information of an obstacle present in the circuit area is detected, and the positional information of the obstacle is detected. Provided is a wiring method for a semiconductor integrated circuit, characterized in that a wiring route between the circuit areas is determined, and a part of the determined wiring route is used to determine a wiring route within each of the divided circuit areas. do.

(Function) In this way, according to the present invention, when determining a broad-pulse wiring route between circuit areas, the route is determined by referring to information on other areas, so that unnecessary detour wiring can be prevented. Also,
It is also possible to shorten the wiring inside the area by using a part of the wiring.

Therefore, a highly integrated and high-speed wiring processing method becomes possible.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows the processing procedure of this wiring method.

After starting, the chip area is divided into circuit areas each consisting of a plurality of circuit blocks or circuit cells (Sl). Next, points with the same sign that extend between the circuit areas and points with the same sign that are closed within the circuit area are determined, and a signal line that extends between the circuit areas is selected (S2). Next, the selected signal line is routed using a line segment search method, taking into account points of other codes that may cause obstacles in other circuit areas (S3). Next, the processes of S2 and S3 are repeated for all points with the same sign that span the areas divided by Sl (
S4). Next, one of the circuit areas divided by Sl is selected (S5). Next, wiring is performed using the maze method within the area determined by Sl for points with the same sign in the circuit area (S6, S7, S8). At this time, it is used as part of the wiring of the signal line wired in S3. Next, S6゜S
7. Each processing step in S8 is repeated for all nets in the area (S9). Next, the wiring process is repeated for all of the circuit areas divided by 81 (S10).
. With the above steps, wiring for the entire chip is completed.

FIG. 2 is a wiring diagram processed using this wiring method. A chip area 21 is decomposed into a plurality of circuit areas 22 consisting of circuit cells or circuit blocks. Inside the circuit area 22
Dots with the same sign are input/output terminals connected to the same signal line. Figure 1 SL, S2. S3. S4: The wiring route indicated by the solid line in FIG. 2 is determined by each processing step.

Specifically, from A1 of the circuit area 22□ to the circuit area 22
Consider the case of wiring to A2 of No. 3 using the line segment search method.

Figure 3 shows the wiring method. First, each circuit area 22 is further divided into grid-like wiring units. For example, 5X
Divide into 5-25 wiring units. Therefore, A1 is address 6 in the circuit area 22.

A2 is address 19 of the circuit area 223, B is the circuit area 222
(Figure 3(a)). Next, as shown in FIG. 3(b), a vertical line segment 30 is drawn from A1. Further perpendicularly from this vertical line segment 30 are line segments 31, 31 .
,······pull. This line segment 2 31 . 31 , . . . are obstacle B and the boundaries of circuit areas 2 22 and 22 . 22 and 223 intersect 1
2 2 , but it still does not intersect with A2. Next, perpendicular to the line segment 312 is a line segment 32.32□...32□2゜32
When we draw the line segment 3213, we find that it intersects with A2, which means that we have discovered a route as shown by the solid line.

Next 35. Points with the same sign to be noted are determined by each processing step in S6. Next, Figure 1 S7. The wiring route within the circuit area 22 is determined by each processing step in S8. Specifically, A1 and A in the circuit area 22
Consider the case where 4 is wired using the route search method. Figure 4 shows the wiring method. The wiring unit is the same as that shown in FIG. 3(a). First, the three adjacent points on the top, bottom, left and right sides that can be connected from A1 are designated as "1" as the first arrival point. Next, specify "2" to the three adjacent points that have not been reached yet from the point of view of the three "11". Similarly, 3", "
When searching to write "4" around "3" which specifies "4", A4 is discovered. From here, one can easily return to the starting point A1 by tracing the numbers in reverse.

At this time, when wiring between the circuit areas 22 within the circuit area 22, a part of the determined route shown by the solid line is used to determine the route shown by the dotted line. If there are more points with the same sign in the circuit area 221, the process proceeds to step S6. S7. Each processing step of S8 is stored in the circuit area 22□
Iterative circuit area 22 for terminal positions with the same sign within
, complete the internal wiring. In this case, the process ends with one process of determining the wiring routes for AI and A4. Next, in the process step 810, the wiring process within the area is repeated for all of the areas divided by 81, and the wiring process for the entire chip is completed.

According to the wiring method described above, when determining the wiring route between each block, the route is determined by referring to information in other areas, so that unnecessary detour wiring can be prevented. Moreover, the wiring inside the area using a part of the wiring can also be shortened. Therefore, a highly integrated and high-speed wiring processing method becomes possible.

[Effects of the Invention] As described above, according to the present invention, global wiring route determination and detailed wiring route determination are closely connected, preventing unnecessary detour wiring and frequent occurrence of through holes, and achieving high-speed It becomes possible to perform automatic wiring processing, and it is also possible to improve the degree of integration of standard cell type semiconductor integrated circuit chips.

[Brief explanation of drawings]

Fig. 1 is a flowchart showing the processing procedure of the embodiment of the present invention, Fig. 2 shows the processing results of wiring using this processing procedure, and Fig. 3 shows the wiring method using the line segment search method of the invention. Figure 4 is a diagram for explaining the wiring method using the maze search method of the present invention, Figure 5 is a diagram showing the conventional wiring process, and Figure 6 is a diagram for explaining the wiring method using the maze search method of the present invention. FIG. 2 is a configuration diagram of a semiconductor integrated circuit according to the method. In the figure, 21... Entire area of integrated circuit chip, 22... Circuit block, 30... Vertical line segment, 31... Line segment, 32...
. . . horizontal line segment, 41 . . . row of circuit cells, 42 . . . area dedicated to wiring, 43 . . . input/output circuit area.

Claims (3)

[Claims] (1) When determining wiring routes between input and output terminals of circuit cells or circuit blocks on a semiconductor substrate by automatic wiring processing, the semiconductor substrate is divided into a plurality of circuit areas including the circuit cells or circuit blocks. , detecting positional information of obstacles existing in the circuit area, determining a wiring route between the circuit areas according to the positional information of the obstacle, and using a part of the determined wiring route to perform the division. 1. A wiring method for a semiconductor integrated circuit, comprising determining a wiring route within a circuit area. (2) The wiring method for a semiconductor integrated circuit according to claim 1, wherein a line segment search method is used as a method for determining the wiring route between the circuit areas. (3) A maze search method is used as a method for determining the wiring route within the divided circuit area.