CN111950228A - Wiring method, apparatus, device and storage medium - Google Patents
Wiring method, apparatus, device and storage medium Download PDFInfo
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
- G06F30/3947—Routing global
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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Abstract
The invention discloses a wiring method, a wiring device, wiring equipment and a storage medium. The method comprises the following steps: determining at least two chip units to be wired; selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network; determining a wiring constraint condition between the at least one first chip unit and a corresponding power supply network to obtain at least one wiring constraint condition; routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network.
Description
Technical Field
The present invention relates to semiconductor technology, and more particularly, to a wiring method, apparatus, device, and storage medium.
Background
With the rapid development of intelligent electronic devices, chip units in the intelligent electronic devices are closely related to semiconductors. With the shortening of semiconductor manufacturing processes, power networks are more and more dense, and pins of chip units are shorter and shorter, when wiring is performed on the chip units, if the chip units and the power networks are distributed and arranged on different circuit layers, the situation that connection points of the pins of the chip units are covered by the power networks may occur, a user needs to manually change the layout, and the number of times of change is large, so that the overall wiring speed is affected.
Therefore, a technical solution for increasing the wiring speed is continuously found.
Disclosure of Invention
In view of the above, embodiments of the present invention are intended to provide a wiring method, apparatus, device and storage medium.
The technical scheme of the invention is realized as follows:
the embodiment of the invention provides a wiring method, which comprises the following steps:
determining at least two chip units to be wired;
selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network;
determining a wiring constraint condition between the at least one first chip unit and a corresponding power supply network to obtain at least one wiring constraint condition;
routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network.
In the foregoing solution, the selecting at least one first chip unit from the at least two chip units to be wired includes:
carrying out global wiring on the at least two chip units to be wired and generating a global wiring report;
and regarding each chip unit of the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be covered by the power network according to the global wiring report, using the corresponding chip unit as a first chip unit to obtain at least one first chip unit.
In the foregoing solution, the determining a routing constraint condition between the at least one first chip unit and the corresponding power supply network includes:
for the at least one first chip unit, determining a relative distance between the respective first chip unit and the respective power supply network;
calculating the difference between the preset standard distance and the relative distance to obtain a difference value;
and the corresponding difference value of the at least one first chip unit is used as a wiring constraint condition between the at least one first chip unit and the power supply network.
In the foregoing solution, the determining a relative distance between the corresponding first chip unit and the corresponding power supply network includes:
determining a first boundary position of a corresponding first chip unit;
determining a second boundary position of the power supply network corresponding to the corresponding first chip unit according to the first boundary position of the corresponding first chip unit;
calculating a first distance between the first boundary position and the second boundary position;
the first distance is taken as the relative distance between the respective first chip unit and the respective power supply network.
In the foregoing solution, the calculating a first distance between the first boundary position and the second boundary position includes:
determining a minimum number of spacings between the first boundary location and the second boundary location;
taking the product of the minimum spacing number and the preset spacing length to obtain a numerical value;
the value is taken as the first distance between the first boundary position and the second boundary position.
In the foregoing solution, after the routing the at least one first chip unit, the method further includes:
selecting at least one second chip unit from the at least two chip units to be wired; at least one connection point of the second chip unit, which is a pin, is not covered by a power supply network and is in an unavailable state;
determining wiring constraint conditions between the at least one second chip unit and the corresponding power supply network to obtain at least one wiring constraint condition;
and according to the at least one wiring constraint condition, wiring the at least one second chip unit so as to enable the connection point of the pin of the at least one second chip unit to be in an available state.
In the foregoing solution, the selecting at least one second chip unit from the at least two chip units to be wired includes:
carrying out detailed wiring on the at least two chip units to be wired and generating a detailed wiring report;
and regarding each chip unit in the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be in an unavailable state according to the detailed wiring report, using the corresponding chip unit as a second chip unit to obtain at least one second chip unit.
An embodiment of the present invention provides a wiring device, including:
the first processing unit is used for determining at least two chip units to be wired; selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network;
the second processing unit is used for determining a wiring constraint condition between the at least one first chip unit and the corresponding power supply network to obtain at least one wiring constraint condition; routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network.
In the foregoing solution, the first processing unit is specifically configured to:
carrying out global wiring on the at least two chip units to be wired and generating a global wiring report;
and regarding each chip unit of the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be covered by the power network according to the global wiring report, using the corresponding chip unit as a first chip unit to obtain at least one first chip unit.
In the foregoing solution, the second processing unit is specifically configured to:
for the at least one first chip unit, determining a relative distance between the respective first chip unit and the respective power supply network;
calculating the difference between the preset standard distance and the relative distance to obtain a difference value;
and the corresponding difference value of the at least one first chip unit is used as a wiring constraint condition between the at least one first chip unit and the power supply network.
In the foregoing solution, the second processing unit is specifically configured to:
determining a first boundary position of a corresponding first chip unit;
determining a second boundary position of the power supply network corresponding to the corresponding first chip unit according to the first boundary position of the corresponding first chip unit;
calculating a first distance between the first boundary position and the second boundary position;
the first distance is taken as the relative distance between the respective first chip unit and the respective power supply network.
In the foregoing solution, the second processing unit is specifically configured to:
determining a minimum number of spacings between the first boundary location and the second boundary location;
taking the product of the minimum spacing number and the preset spacing length to obtain a numerical value;
the value is taken as the first distance between the first boundary position and the second boundary position.
In the foregoing solution, the second processing unit is further configured to:
selecting at least one second chip unit from the at least two chip units to be wired; at least one connection point of the second chip unit, which is a pin, is not covered by a power supply network and is in an unavailable state;
determining wiring constraint conditions between the at least one second chip unit and the corresponding power supply network to obtain at least one wiring constraint condition;
and according to the at least one wiring constraint condition, wiring the at least one second chip unit so as to enable the connection point of the pin of the at least one second chip unit to be in an available state.
In the foregoing solution, the second processing unit is specifically configured to:
carrying out detailed wiring on the at least two chip units to be wired and generating a detailed wiring report;
and regarding each chip unit in the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be in an unavailable state according to the detailed wiring report, using the corresponding chip unit as a second chip unit to obtain at least one second chip unit.
An embodiment of the present invention provides an electronic device, including: a processor and a memory for storing a computer program capable of running on the processor,
wherein the processor is configured to implement the steps of any of the above methods when executing the computer program.
An embodiment of the present invention provides a storage medium, on which a computer program is stored, which when executed by a processor implements the steps of any of the above-mentioned methods.
The wiring method, the device, the equipment and the storage medium provided by the embodiment of the invention determine at least two chip units to be wired; selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network; determining a wiring constraint condition between the at least one first chip unit and a corresponding power supply network to obtain at least one wiring constraint condition; routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network. By adopting the technical scheme of the embodiment of the invention, the wiring constraint condition between the corresponding chip unit and the corresponding power network is determined for the chip unit of which the connection point of the pin is covered by the power network, and wiring is carried out according to the wiring constraint condition so as to ensure that the connection point of the pin of the chip unit avoids the power network.
Drawings
FIG. 1 is a schematic diagram of a connection point of a pin of a chip unit in the related art;
FIG. 2 is a schematic diagram of a process for implementing a wiring method according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a first boundary position of a chip unit and a second boundary position of a power network according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating an implementation flow of determining a routing constraint between a first chip unit and a power supply network according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a first chip unit according to an embodiment of the present invention;
FIG. 6 is a schematic illustration of a first boundary location and a second boundary location in accordance with an embodiment of the present invention;
FIG. 7 is a schematic diagram of the wiring of the chip units according to the embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating global routing with increased placement constraints compared to global routing without increased placement constraints, according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a wiring device according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
Before describing the technical solution of the embodiment of the present invention in detail, a description will be given of a related art.
In the related art, as the semiconductor manufacturing process is shortened, the power supply network is more and more dense, and the pins of the chip units are shorter and shorter, when the chip units are wired, if the chip units and the power supply network are respectively arranged on different circuit layers, the connection points of the pins of the chip units may be covered by the power supply network. Fig. 1 is a schematic diagram of connection points of pins of a chip unit in the related art, taking the chip unit as a standard unit as an example, as shown in fig. 1, one connection point of a Pin a of the standard unit is covered by a power supply network Vdd or Vss, and the other connection point is not covered by the power supply network Vdd or Vss; two connection points of the pin b of the standard unit are covered by a power supply network Vdd or a power supply network Vss; one connection point of the pin c of the standard cell is covered by the power supply network Vdd or Vss, and the other connection point is not covered by the power supply network Vdd or Vss. Because two connection points of the pin b of the standard unit are covered by the power supply network Vdd or the power supply network Vss, the standard unit cannot be wired, a user needs to manually change the layout, and the overall wiring speed is affected due to more times of change. The standard unit may include a plurality of basic units such as an inverter, an and gate, a register, a selector, and a full adder.
Based on this, in various embodiments of the present invention, at least two chip units to be wired are determined; selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network; determining a wiring constraint condition between the at least one first chip unit and a corresponding power supply network to obtain at least one wiring constraint condition; routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network.
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
The embodiment of the invention provides a wiring method, and fig. 2 is a schematic flow chart of the implementation of the wiring method according to the embodiment of the invention; as shown in fig. 2, the method includes:
step 201: determining at least two chip units to be wired;
step 202: selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network;
step 203: determining a wiring constraint condition between the at least one first chip unit and a corresponding power supply network to obtain at least one wiring constraint condition;
step 204: routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network.
Here, in step 201, the sizes of the areas occupied by the at least two chip units to be wired in the circuit board may be the same or different, and the patterns corresponding to the areas may be the same or different. For example, assume that the chip unit to be wired includes a chip unit a, a chip unit b, and a chip unit c, where the patterns corresponding to the areas occupied by the chip unit a, the chip unit b, and the chip unit c in the circuit board are all rectangles, the area corresponding to the chip unit a is the largest, and the area corresponding to the chip unit c is the smallest.
Here, in step 202, in practical application, the circuit layer where the at least two chip units to be wired are located may be different from the circuit layer where the power supply network is located. For example, when the at least two chip units to be wired are disposed at a layer below a circuit layer where the power network is located, and the power network and the chip units are vertically distributed, and the pins of the chip units are short, a situation that the connection points of the pins of the chip units are covered by the power network may occur.
Here, in step 203, in an actual application, in order to perform an iterative wiring, for a chip unit in which all connection points of the pins are covered by the power supply network, a layout constraint condition between the chip unit and the corresponding power supply network may be determined, and then, according to the layout constraint condition, the iterative wiring is performed on the chip unit in which the connection points of the pins are covered by the power supply network, so that the connection points of the pins of the chip unit avoid the corresponding power supply network, and the wiring is performed on the chip unit; the power supply network may refer to a power supply or a ground, and a plurality of power supply networks are distributed in the circuit board at regular intervals.
In practical application, global wiring can be performed on at least two chip units to be wired, and according to a wiring report obtained by the global wiring, whether all connection points of pins in the at least two chip units to be wired are covered by a power network or not is detected.
Based on this, in an embodiment, the selecting at least one first chip unit from the at least two chip units to be wired includes:
carrying out global wiring on the at least two chip units to be wired and generating a global wiring report;
and regarding each chip unit of the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be covered by the power network according to the global wiring report, using the corresponding chip unit as a first chip unit to obtain at least one first chip unit.
The global wiring can be referred to as global wiring, and the global wiring can refer to global planning of the wiring of the chip unit, specifically, the global wiring can be targeted, and then specific planning can be made in combination with the characteristics of the wiring design.
For example, assuming that at least two chip units to be wired are represented by a chip unit a, a chip unit b, a chip unit c and a chip unit d, after global wiring is performed, a global wiring report can be obtained; if the connection points of the pins of the chip unit b and the chip unit c are marked by red fork symbols in the global wiring report, all the connection points of the pins of the chip unit b and the chip unit c are covered by the power supply network. The position of the power network corresponding to the chip unit b in the circuit board may be the same as or different from the position of the power network corresponding to the chip unit c in the circuit board.
In practical applications, if the distance between the power network and the connection point of the pin of the chip unit is short, the connection point of the pin of the chip unit is easily covered by the power network, and therefore, the relative distance between the chip unit and the power network needs to be readjusted to make the connection point of the pin of the chip unit avoid the power network.
Based on this, in an embodiment, the determining a routing constraint between the at least one first chip unit and the corresponding power supply network includes:
for the at least one first chip unit, determining a relative distance between the respective first chip unit and the respective power supply network;
calculating the difference between the preset standard distance and the relative distance to obtain a difference value;
and the corresponding difference value of the at least one first chip unit is used as a wiring constraint condition between the at least one first chip unit and the power supply network.
In practical application, a first boundary position of the first chip unit can be determined according to a connection point of a pin covered by a power supply network of the first chip unit; according to the first boundary position of the first chip unit, a second boundary position of the power supply network can be determined, and according to the first boundary position and the second boundary position, a relative distance between the first chip unit and the power supply network can be determined.
Based on this, in an embodiment, the determining a relative distance between the respective first chip unit and the respective power supply network includes:
determining a first boundary position of a corresponding first chip unit;
determining a second boundary position of the power supply network corresponding to the corresponding first chip unit according to the first boundary position of the corresponding first chip unit;
calculating a first distance between the first boundary position and the second boundary position;
the first distance is taken as the relative distance between the respective first chip unit and the respective power supply network.
Wherein the second boundary position and the first boundary position may be relatively parallel.
For example, fig. 3 is a schematic diagram of a first boundary position of a chip unit and a second boundary position of a power supply network, as shown in fig. 3, the first chip unit includes two connection points, which are denoted by a and b; and the connection point a is covered by a power supply network, the connection point b is not covered by the power supply network, and 3 first boundary positions of the first chip unit are determined according to the connection point a and are represented by a position 1, a position 2 and a position 3. The second boundary position of the power supply network determined from the first boundary position of the first chip unit comprises: position 11 parallel to position 1, position 22 parallel to position 2, and position 33 parallel to position 3. The first distance between position 1 and position 11, the first distance between position 2 and position 22, and the first distance between position 3 and position 33 can be used as the relative distance between the chip unit and the power network.
In practical applications, the chip unit may be moved by using the minimum pitch when performing the wiring, and therefore, the minimum number of pitches between the first boundary position and the second boundary position may be calculated, and then the first distance between the first boundary position and the second boundary position may be determined according to the minimum number of pitches and the length of the minimum pitch.
Based on this, in an embodiment, the calculating a first distance between the first boundary position and the second boundary position includes:
determining a minimum number of spacings between the first boundary location and the second boundary location;
taking the product of the minimum spacing number and the preset spacing length to obtain a numerical value;
the value is taken as the first distance between the first boundary position and the second boundary position.
In one embodiment, as shown in FIG. 4, a process for determining routing constraints between a first chip unit and a power supply network is described, comprising:
step 401: and selecting a first chip unit from the at least two chip units to be wired.
Fig. 5 is a schematic diagram of determining a first chip unit, and as shown in fig. 5, the chip unit to be wired includes a chip unit 1, a chip unit 2, and a chip unit 3; all connection points of the pins of the chip unit 2 are covered by the power supply network, so that the chip unit 2 is the selected first chip unit.
Step 402: a first boundary position of the first chip unit is determined according to a connection point of a pin covered by a power supply network in the first chip unit.
Step 403: and determining a second boundary position of the power supply network corresponding to the first chip unit according to the first boundary position of the first chip unit.
Fig. 6 is a schematic diagram of a first boundary position and a second boundary position, and as shown in fig. 6, there are 3 first boundary positions of the first chip unit, namely position 1, position 2 and position 3. There are 3 second boundary positions of power network, include: position 11 corresponding to position 1, position 22 parallel to position 2, and position 33 parallel to position 3.
Step 404: a first distance between the first boundary position and the second boundary position is calculated.
Here, the first distance between the first boundary position and the second boundary position is calculated according to equation (1), specifically as follows:
d＝L1-L2 (1)
wherein d represents the first distance, L1 represents the first boundary position, and L2 represents the second boundary position.
Step 405: calculating the difference between a preset standard distance and the first distance to obtain a difference value; and taking the difference value as a wiring constraint condition between the first chip unit and the power supply network.
Here, the difference between the preset standard distance and the first distance is calculated according to formula (2), which is as follows:
m＝D-d (2)
wherein m represents the difference, D represents the preset standard distance, and D represents the first distance.
Here, determining the wiring constraint between the first chip unit and the power supply network has the following advantages:
(1) the layout constraint conditions of the chip units near the power supply network can be evaluated and analyzed in an early stage, and compared with the mode of mainly referring to the layout conditions provided by suppliers in the related art, the layout constraint conditions of the chip units in the related art are considered to be very high, and the suppliers cannot exhaust all the constraint conditions aiming at different designs.
(2) Aiming at the problem that the layout constraint of a chip unit and a power supply network is not complete in chip back end design in the related technology, the embodiment of the invention provides an implementation process capable of quickly obtaining the layout constraint condition so as to determine whether the connection point of the chip unit is reasonable or not in the layout stage, provide more wiring resources in the wiring stage and obtain a better layout effect.
In practical application, after the at least one first chip unit is wired, at least one connection point of the pin of the at least one first chip unit can be made to avoid a power supply network. However, if the connection point may not be available for wiring due to other factors, the relative distance between the chip unit and the power supply network may be adjusted again to make the connection point of the pin of the chip unit available.
Based on this, in an embodiment, after the routing the at least one first chip unit, the method further includes:
selecting at least one second chip unit from the at least two chip units to be wired; at least one connection point of the second chip unit, which is a pin, is not covered by a power supply network and is in an unavailable state;
determining wiring constraint conditions between the at least one second chip unit and the corresponding power supply network to obtain at least one wiring constraint condition;
and according to the at least one wiring constraint condition, wiring the at least one second chip unit so as to enable the connection point of the pin of the at least one second chip unit to be in an available state.
Here, the reason why the connection point is in the unavailable state may be: there may be other metal devices around the connection point to cause no wiring or the like.
Here, a relative distance between the second chip unit and the respective power supply network may be determined; summing the determined relative distance and the fixed numerical value to obtain a numerical value; and taking the value as a wiring constraint condition between the second chip unit and the corresponding power supply network. Wherein the fixed value may be equal to an integer multiple of the minimum pitch length; the process of determining the relative distance between the second chip unit and the corresponding power supply network is the same as the process of determining the relative distance between the first chip unit and the corresponding power supply network, and details are not repeated here.
In practical application, after the at least one first chip unit is wired, the connection point of the pin of the at least one first chip unit can be kept away from the power supply network. However, whether the connection point is available for wiring needs to be wired, and the chip unit needs to be wired in detail, and whether the connection point of the pin of the chip unit is an available connection point is analyzed through a detailed wiring report.
Based on this, in an embodiment, the selecting at least one second chip unit from the at least two chip units to be wired includes:
carrying out detailed wiring on the at least two chip units to be wired and generating a detailed wiring report;
and regarding each chip unit in the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be in an unavailable state according to the detailed wiring report, using the corresponding chip unit as a second chip unit to obtain at least one second chip unit.
The detailed wiring may be referred to as detail wiring, and the detail wiring may refer to wiring a connection point of a pin between the chip units.
For example, assuming that at least two chip units to be wired are represented by a chip unit a, a chip unit b, a chip unit c and a chip unit d, after detailed wiring is performed, a detailed wiring report can be obtained; if the connection point of the pins of the chip unit b and the chip unit c is marked by a red cross symbol in the detailed wiring report, the connection point of the pins of the chip unit b and the chip unit c is in an unavailable state. The reason for the connection point being in the unavailable state may be: other metal devices may be present around the connection point, etc.
In an embodiment, as shown in fig. 7, taking a chip unit as a standard unit as an example, a process of routing the chip unit is described, which includes:
step 701: at least two standard cells are initially laid out.
Here, when at least two standard cells are first laid out, initial laying out may be performed using conditions of layout constraints provided by a vendor. The standard unit can comprise various basic units such as an inverter, an AND gate, a register, a selector, a full adder and the like.
Step 702: global routing is performed on at least two standard cells, and a global routing report is generated.
Step 703: for each standard unit in the at least two standard units, judging whether the connection point of the pin of the corresponding standard unit is covered by a power supply network or not according to the global wiring report; when it is determined that the connection point of the pin of the corresponding standard cell is covered by the power grid, executing step 704; otherwise, step 705 is performed.
Step 704: determining layout constraint conditions of the corresponding standard cells and the power supply network; and according to the determined layout constraint conditions, re-executing the step 701.
Here, when the power supply network is Vdd, the layout constraint of the corresponding standard cell and the power supply network Vdd is determined, and when the power supply network is Vss, the layout constraint of the corresponding standard cell and the power supply network Vss is determined.
Here, the layout constraint may refer to a relative distance of the power supply network with respect to a specific pin of the standard cell on a specific circuit layer.
For example, the name of the standard cell: r0uhd _ nn8_ sec _ oai22f00p50, when the standard cell is globally routed according to the determined layout constraint condition, the minimum distance between the connecting point on the left side of the standard cell and the left boundary of the power supply network is ensured to be 0.017, and the minimum distance between the connecting point on the right side of the standard cell and the right boundary of the power supply network is ensured to be 0.017, so that the standard cell is prevented from being covered by the power supply network.
Step 705: and carrying out detailed wiring on the at least two standard chips and generating a detailed wiring report.
Step 706: for each standard unit in the at least two standard units, judging whether a connection point of a pin of the corresponding standard unit is available according to the detailed wiring report; when it is determined that the connection point of the pin of the corresponding standard cell is not available, performing step 704; otherwise, go to step 707;
step 707: and recording layout constraints of the at least two standard cells and the power supply network.
Fig. 8 is a schematic diagram comparing global wiring performed with the added layout constraint condition with global wiring performed without the added layout constraint condition, and as shown in fig. 8, wiring performed with the added layout constraint condition can prevent the connection points of the pins of the chip unit from being covered by the power supply network, and when detailed wiring is performed subsequently, a larger number of connection points can be provided, thereby increasing the wiring resources.
Here, in the process of wiring the chip unit, the layout constraint condition between the chip unit and the power supply network is increased, and the following advantages are provided:
(1) the layout constraint conditions of the added chip units and the power network Vdd \ Vss are utilized to carry out wiring, so that the distance between the connection point of the pins of the chip units and the power network Vdd \ Vss is increased, and the connection point of the pins of the chip units cannot be blocked by the power network Vdd \ Vss. Meanwhile, the number of the connection points of the pins of the chip unit is increased from one to two, so that the wiring resources are increased.
(2) Aiming at a specific design, the layout constraint conditions of the chip unit and the power supply network Vdd \ Vss can be quickly determined, so that the connection points at the detailed wiring stage are increased by utilizing the determined layout constraint conditions, and the wiring congestion near the standard unit is reduced.
(3) The wiring result of the chip unit near the power supply network can be analyzed, the layout between the standard unit and the power supply network is adjusted according to the analysis structure, and the optimized layout is quickly obtained through one-time iterative wiring.
By adopting the technical scheme of the embodiment of the invention, the wiring constraint condition between the corresponding chip unit and the corresponding power network is determined for the chip unit of which the connection point of the pin is covered by the power network, and wiring is carried out according to the wiring constraint condition so as to ensure that the connection point of the pin of the chip unit avoids the power network.
In order to implement the wiring method according to the embodiment of the present invention, a wiring device is further provided in the embodiment of the present invention, and is disposed on the mobile terminal. FIG. 9 is a schematic diagram of a wiring device according to an embodiment of the present invention; as shown in fig. 9, the apparatus includes:
a first processing unit 91, configured to determine at least two chip units to be wired; selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network;
a second processing unit 92, configured to determine a routing constraint between the at least one first chip unit and a corresponding power supply network, so as to obtain at least one routing constraint; routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network.
In an embodiment, the first processing unit 91 is specifically configured to:
carrying out global wiring on the at least two chip units to be wired and generating a global wiring report;
and regarding each chip unit of the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be covered by the power network according to the global wiring report, using the corresponding chip unit as a first chip unit to obtain at least one first chip unit.
In an embodiment, the second processing unit 92 is specifically configured to:
for the at least one first chip unit, determining a relative distance between the respective first chip unit and the respective power supply network;
calculating the difference between the preset standard distance and the relative distance to obtain a difference value;
and the corresponding difference value of the at least one first chip unit is used as a wiring constraint condition between the at least one first chip unit and the power supply network.
In an embodiment, the second processing unit 92 is specifically configured to:
determining a first boundary position of a corresponding first chip unit;
determining a second boundary position of the power supply network corresponding to the corresponding first chip unit according to the first boundary position of the corresponding first chip unit;
calculating a first distance between the first boundary position and the second boundary position;
the first distance is taken as the relative distance between the respective first chip unit and the respective power supply network.
In an embodiment, the second processing unit 92 is specifically configured to:
determining a minimum number of spacings between the first boundary location and the second boundary location;
taking the product of the minimum spacing number and the preset spacing length to obtain a numerical value;
the value is taken as the first distance between the first boundary position and the second boundary position.
In an embodiment, the second processing unit 92 is further configured to:
selecting at least one second chip unit from the at least two chip units to be wired; at least one connection point of the second chip unit, which is a pin, is not covered by a power supply network and is in an unavailable state;
determining wiring constraint conditions between the at least one second chip unit and the corresponding power supply network to obtain at least one wiring constraint condition;
and according to the at least one wiring constraint condition, wiring the at least one second chip unit so as to enable the connection point of the pin of the at least one second chip unit to be in an available state.
In an embodiment, the second processing unit 92 is specifically configured to:
carrying out detailed wiring on the at least two chip units to be wired and generating a detailed wiring report;
and regarding each chip unit in the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be in an unavailable state according to the detailed wiring report, using the corresponding chip unit as a second chip unit to obtain at least one second chip unit.
In practical applications, the first processing unit 91 and the second processing unit 92 may be implemented by a processor in the apparatus; the Processor may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a Micro Control Unit (MCU), or a Programmable Gate Array (FPGA).
It should be noted that: the device provided in the above embodiment is only exemplified by the division of the above program modules when performing the wiring, and in practical applications, the above processing distribution may be completed by different program modules according to needs, that is, the internal structure of the terminal is divided into different program modules to complete all or part of the above described processing. In addition, the apparatus provided by the above embodiment and the wiring method embodiment belong to the same concept, and the specific implementation process thereof is described in the method embodiment, which is not described herein again.
Based on the hardware implementation of the above devices, an embodiment of the present invention further provides an electronic device, fig. 10 is a schematic diagram of a hardware structure of a mobile terminal according to an embodiment of the present invention, as shown in fig. 10, an electronic device 100 includes a memory 103, a processor 102, and a computer program stored in the memory 103 and capable of running on the processor 102; the processor 102 implements the method provided by one or more of the above technical solutions when executing the program.
It should be noted that, the specific steps implemented when the processor 102 executes the program have been described in detail above, and are not described herein again.
It is understood that the electronic device 100 further includes a communication interface 101, and the communication interface 101 is used for information interaction with other devices; meanwhile, various components in the electronic device 100 are coupled together by a bus system 104. It will be appreciated that the bus system 104 is configured to enable connected communication between these components. The bus system 104 includes a power bus, a control bus, a status signal bus, and the like, in addition to the data bus.
It will be appreciated that the memory 103 in this embodiment may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. Among them, the nonvolatile Memory may be a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), a magnetic random access Memory (FRAM), a Flash Memory (Flash Memory), a magnetic surface Memory, an optical disk, or a Compact Disc Read-Only Memory (CD-ROM); the magnetic surface storage may be disk storage or tape storage. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced DRAM), Synchronous Dynamic Random Access Memory (SLDRAM), Direct Memory (DRmb Access), and Random Access Memory (DRAM). The described memory for embodiments of the present invention is intended to comprise, without being limited to, these and any other suitable types of memory.
The method disclosed in the above embodiments of the present invention may be applied to the processor 102, or implemented by the processor 102. The processor 102 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 102. The processor 102 described above may be a general purpose processor, a DSP, or other programmable logic device, discrete gate or transistor logic device, discrete hardware components, or the like. Processor 102 may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present invention. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed by the embodiment of the invention can be directly implemented by a hardware decoding processor, or can be implemented by combining hardware and software modules in the decoding processor. The software modules may be located in a storage medium that is located in a memory where the processor 102 reads information to perform the steps of the aforementioned methods in conjunction with its hardware.
The embodiment of the invention also provides a storage medium, in particular a computer storage medium, and more particularly a computer readable storage medium. Stored thereon are computer instructions, i.e. computer programs, which when executed by a processor perform the methods provided by one or more of the above-mentioned aspects.
In the embodiments provided in the present invention, it should be understood that the disclosed method and intelligent device may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.
Alternatively, the integrated unit of the present invention may be stored in a computer-readable storage medium if it is implemented in the form of a software functional module and sold or used as a separate product. Based on such understanding, the technical solutions of the embodiments of the present invention may be essentially implemented or a part contributing to the prior art may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, a ROM, a RAM, a magnetic or optical disk, or various other media that can store program code.
It should be noted that: "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In addition, the technical solutions described in the embodiments of the present invention may be arbitrarily combined without conflict.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.
Claims (10)
1. A wiring method, characterized in that the method comprises:
determining at least two chip units to be wired;
selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network;
determining a wiring constraint condition between the at least one first chip unit and a corresponding power supply network to obtain at least one wiring constraint condition;
routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network.
2. The method of claim 1, wherein selecting at least one first chip unit from the at least two chip units to be wired comprises:
carrying out global wiring on the at least two chip units to be wired and generating a global wiring report;
and regarding each chip unit of the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be covered by the power network according to the global wiring report, using the corresponding chip unit as a first chip unit to obtain at least one first chip unit.
3. The method of claim 1 or 2, wherein the determining routing constraints between the at least one first chip unit and the respective power supply network comprises:
for the at least one first chip unit, determining a relative distance between the respective first chip unit and the respective power supply network;
calculating the difference between the preset standard distance and the relative distance to obtain a difference value;
and the corresponding difference value of the at least one first chip unit is used as a wiring constraint condition between the at least one first chip unit and the power supply network.
4. The method of claim 3, wherein determining the relative distance between the respective first chip unit and the respective power supply network comprises:
determining a first boundary position of a corresponding first chip unit;
determining a second boundary position of the power supply network corresponding to the corresponding first chip unit according to the first boundary position of the corresponding first chip unit;
calculating a first distance between the first boundary position and the second boundary position;
the first distance is taken as the relative distance between the respective first chip unit and the respective power supply network.
5. The method of claim 4, wherein said calculating a first distance between the first boundary position and the second boundary position comprises:
determining a minimum number of spacings between the first boundary location and the second boundary location;
taking the product of the minimum spacing number and the preset spacing length to obtain a numerical value;
the value is taken as the first distance between the first boundary position and the second boundary position.
6. The method of any of claims 1 to 5, wherein after routing the at least one first chip unit, the method further comprises:
selecting at least one second chip unit from the at least two chip units to be wired; at least one connection point of the second chip unit, which is a pin, is not covered by a power supply network and is in an unavailable state;
determining wiring constraint conditions between the at least one second chip unit and the corresponding power supply network to obtain at least one wiring constraint condition;
and according to the at least one wiring constraint condition, wiring the at least one second chip unit so as to enable the connection point of the pin of the at least one second chip unit to be in an available state.
7. The method of claim 6, wherein said selecting at least one second chip unit from the at least two chip units to be wired comprises:
carrying out detailed wiring on the at least two chip units to be wired and generating a detailed wiring report;
and regarding each chip unit in the at least two chip units to be wired, when the connection point of the pin of the corresponding chip unit is determined to be in an unavailable state according to the detailed wiring report, using the corresponding chip unit as a second chip unit to obtain at least one second chip unit.
8. A wiring device, comprising:
the first processing unit is used for determining at least two chip units to be wired; selecting at least one first chip unit from the at least two chip units to be wired; the first chip unit is a chip unit with all connection points of pins covered by a power supply network;
the second processing unit is used for determining a wiring constraint condition between the at least one first chip unit and the corresponding power supply network to obtain at least one wiring constraint condition; routing the at least one first chip unit according to the at least one routing constraint condition so that at least one connection point of a pin of the at least one first chip unit is not covered by a power supply network.
9. An electronic device, comprising: a processor and a memory for storing a computer program capable of running on the processor,
wherein the processor is adapted to perform the steps of the method of any one of claims 1 to 7 when running the computer program.
10. A storage medium having a computer program stored thereon, the computer program, when being executed by a processor, performing the steps of the method of any one of claims 1 to 7.
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