CN116976272B - Integrated circuit design optimization wiring method, electronic equipment and storage medium - Google Patents

Integrated circuit design optimization wiring method, electronic equipment and storage medium Download PDF

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Publication number
CN116976272B
CN116976272B CN202311225171.XA CN202311225171A CN116976272B CN 116976272 B CN116976272 B CN 116976272B CN 202311225171 A CN202311225171 A CN 202311225171A CN 116976272 B CN116976272 B CN 116976272B
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pin
integrated circuit
access points
pins
access
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CN116976272A (en
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刘中原
王小虎
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Huaxin Giants Hangzhou Microelectronics Co ltd
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Huaxin Giants Hangzhou Microelectronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation

Abstract

The present invention relates to the field of integrated circuit design, and in particular, to an integrated circuit design optimization wiring method, an electronic device, and a storage medium. In the process of designing a very large scale integrated circuit chip, the wiring result must meet the constraint of the design rule, and in this way, the invention provides a pin access scheme which is applicable to the pins on the grid or not and meets the requirement of the design rule, and the wiring result is optimized through the pin access scheme. The invention solves the technical problems that the wiring in the design of the ultra-large scale integrated circuit is easy to lead to poor wiring result and even the surplus design rule violation cannot be processed because of unreasonable way of accessing pins. The invention also provides an electronic device and a computer readable storage medium, which have the same beneficial effects as the method.

Description

Integrated circuit design optimization wiring method, electronic equipment and storage medium
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to an integrated circuit design optimization wiring method, an electronic device, and a storage medium.
Background
Pins are electrical terminals for connecting a given component to its external environment, and in very large scale integrated circuit chip designs, the pins have various types of power supply, input and output, and the main functions are to implement information input and output of each component, and in very large scale integrated circuit chip designs, wiring plays a key role, and its task is to connect each pin of each network through wires and vias, thereby connecting each component.
Meanwhile, the wiring result must meet the constraint of design rules, which are summaries of graphic rules that are highly likely to fail in the lithography process by manufacturers of integrated circuit chips under different advanced process technology nodes. Therefore, the design party of the integrated circuit chip needs to observe the design rule, avoid the design rule violation in the design process, and solve the design rule violation in the design delivery process so as to ensure the manufacturability of the design.
In the process of designing the ultra-large scale integrated circuit chip, the wiring result is poor and even the surplus design rule violation cannot be processed because the way of accessing the pins is unreasonable.
Disclosure of Invention
The invention provides an integrated circuit design optimizing wiring method, electronic equipment and a storage medium, which are used for solving the technical problems that wiring in the ultra-large scale integrated circuit design is easy to cause poor wiring results and even surplus design rule violations cannot be processed because of unreasonable access pins.
The invention provides an integrated circuit design optimizing wiring method, which is applied to super-large scale integrated circuit design and comprises the following steps:
s1: providing a pin and obtaining pin information thereof, and selecting via hole information and stub parameters for pin access according to design rules;
s2: calculating the characteristic size of the pins according to the pin information, determining the number of access points according to the characteristic size, and defining the number of the access points as an expected value;
s3: selecting a priority access point from a wiring layer where a pin is positioned and a wiring layer above the pin, verifying the priority access point according to the via information and the stub parameters by using a design rule to obtain the number of available access points, executing a step S4 if the number of available access points is less than the expected value, otherwise executing a step S5;
s4: acquiring available access points by reducing the step length of the prior access points and/or increasing virtual tracks among tracks of a wiring layer above the pins, and executing step S5 when the number of the available access points is not less than the expected value;
S5: checking whether the pin access mode of each available access point and the adjacent pin access mode violate the design rule, leaving available access points which do not violate the design rule, ending the calculation of the pin if the number of the remaining available access points is not less than the expected value, otherwise executing step S4.
Preferably, after the calculation of the pins is finished in step S5, the following steps are performed:
s6: and if the number of the remaining available access points is not less than the expected value, continuing to return to the step S1 to execute the calculation of the next pin until the calculation of all pins is completed, and outputting the access points and the pin access modes which accord with the design rules.
Preferably, the selecting the priority access point in step S3 specifically includes the following steps:
s31a: acquiring pins and wiring layers above the pins, wherein the wiring layer where the pins are positioned is defined as M x The wiring layers above the pins are M in turn x+1 ，M x+2 ；
S31b: at the pins and M x+1 On the track intersection line of (1), taking the midpoint of the intersection line as a starting point, M x+2 Selecting a priority access point for the step size.
Preferably, in step S4, two actions of reducing the step size and increasing the virtual track are alternately performed, and after the step size is reduced or the virtual track is increased, the number of available access points is calculated.
Preferably, the available access points are acquired by adding virtual tracks, which requires the following steps:
when the virtual track is added for the first time, taking the sum M x+1 Is parallel to the adjacent actual track and has a distance M x+1 Layer track pitchIs a virtual track;
nth time%n > 1) increased virtual track, the distance between which and the actual track is reduced to the distance between the virtual track and the actual track increased for the n-1 th time。
Preferably, in step S5, a candidate set is added to the pin access mode corresponding to the available access point that does not violate the design rule, where the candidate set includes the access cost of each pin access mode.
Preferably, in step S2, the feature size includes a width and/or an area of the pin.
Preferably, the number of access points required per pin is at least 2.
The invention also provides an electronic device comprising a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor;
when the electronic equipment runs, the processor and the storage medium are communicated through the bus, and the processor executes the program instructions to realize the integrated circuit design optimization wiring method.
The present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the integrated circuit design optimization routing method described above.
Compared with the prior art, the integrated circuit design optimizing wiring method, the electronic equipment and the storage medium provided by the invention have the following advantages:
1. the integrated circuit design optimizing wiring method provided by the embodiment of the invention is applied to the design of a very large scale integrated circuit and comprises the following steps: s1: providing a pin and obtaining pin information thereof, and selecting via hole information and stub parameters for pin access according to design rules; s2: calculating the characteristic size of the pins according to the pin information, determining the number of access points according to the characteristic size, and defining the number of the access points as an expected value; s3: selecting a priority access point from the wiring layer where the pin is positioned and the wiring layer above the pin, verifying the priority access point according to the via information and the short-circuit parameters by using a design rule to obtain the number of available access points, executing the step S4 if the number of available access points is less than an expected value, otherwise executing the step S5; s4: acquiring available access points between tracks of a wiring layer above the pins by reducing the step length of the priority access points and/or increasing virtual tracks, and executing step S5 when the number of the available access points is not less than an expected value; s5: checking whether the pin access mode of each available access point and the adjacent pin access mode violate the design rule, leaving available access points which do not violate the design rule, ending the calculation of the pin if the number of the remaining available access points is not less than the expected value, otherwise executing the step S4.
It should be noted that, in the process of designing a very large scale integrated circuit chip, the routing result must meet the constraint of the design rule, so the invention provides a pin access scheme which is applicable to the pins on the grid or not and meets the requirement of the design rule, and the routing result is optimized through the pin access scheme.
It can be understood that the invention provides guidance for the access pins during detailed wiring by calculating the access points and access modes of the pins conforming to the design rules before wiring, and solves the technical problems that the wiring in the ultra-large scale integrated circuit design is easy to cause poor wiring results and even the surplus design rule violations cannot be processed because the access modes of the access pins are unreasonable.
It can be further understood that by the design, on the premise of following the design rule, a proper access scheme is provided for the pins on the grid or not, so that the convergence speed of the design rule violation in the detailed wiring is increased, and the wiring result is optimized.
2. After finishing the calculation of the pins in step S5, the integrated circuit design optimizing wiring method provided by the embodiment of the invention executes the following steps: s6: if the number of the remaining available access points is not less than the expected value, continuing to return to the step S1 to execute the calculation of the next pin until the calculation of all pins is completed, and outputting the access points and the pin access modes which accord with the design rules. It will be appreciated that when the number of available access points is sufficiently large, the calculation of that pin is terminated, and the calculation of the next pin is performed instead until the calculation of all pins is completed, and then the access points and pin access modes are output.
3. The integrated circuit design optimizing wiring method provided by the embodiment of the invention, wherein the step S3 of selecting the priority access point specifically comprises the following steps: s31a: acquiring pins and wiring layers above the pins, wherein the wiring layer where the pins are positioned is defined as M x The wiring layers above the pins are M in turn x+1 ，M x+2 The method comprises the steps of carrying out a first treatment on the surface of the S31b: at the pins and M x+1 On the track intersection line of (1), taking the midpoint of the intersection line as a starting point, M x+2 Selecting a priority access point for the step size.
In the design of the very large scale integrated circuit chip, the wiring layer M x And the upper wiring layer M x+1 Is perpendicular to each other, so that the wiring layer M x+1 Track and wiring layer M of (2) x When projected from top to bottom into the same plane, there are a plurality of intersections called wiring layers M x Is a grid of grid points.
It will be appreciated that the priority access point is selected only with M x+1 Is related to the intersection of the track and the pin, M x Is independent of the track of the pin, and is not affected by whether the pin is on the grid.
4. In the integrated circuit design optimization wiring method provided by the embodiment of the invention, in step S4, two actions of reducing the step length and increasing the virtual track are alternately executed, and after the step length is reduced or the virtual track is increased, the number of available access points is calculated.
It can be understood that, after any one of the operations of reducing the step size and increasing the virtual track is performed, the number of available access points is calculated, and when the number of available access points is greater than or equal to the expected value, step S5 is performed, otherwise, the two operations of reducing the step size and increasing the virtual track are performed alternately.
It should be noted that, the step size is reduced to half the original step size, and such operations are performed up to the step size of the first priority access point (i.e., M x+2 Inter-track of a layerDistance) of the base plateIf the available access points are not enough, an attempt is made to reduce the step size directly to the first +.>To make the last attempt.
5. The integrated circuit design optimizing wiring method provided by the embodiment of the invention obtains the available access point by adding the virtual track, and the method comprises the following steps: when the virtual track is added for the first time, taking the sum M x+1 Is parallel to the adjacent actual track and has a distance M x+1 Layer track pitchIs a virtual track; an n-th (n > 1) increased virtual track whose spacing from the actual track is reduced to +.1-th increased virtual track and the spacing between the actual tracks>。
It should be noted that such operations are performed at most to a virtual track pitch of M x+1 Layer track pitchIf the available access points are not enough, an attempt is made to reduce the pitch of the virtual tracks directly to the first +.>To make the last attempt.
6. In step S5, a candidate set is added to a pin access mode corresponding to an available access point that does not violate a design rule, where the candidate set includes an access cost of each pin access mode.
It will be appreciated that the checking of available access points is mainly whether there is a design rule violation between the via or stub of the access pin and the structure itself present in the standard cell, by which design the likelihood of the selected access mode violating the design rule can be reduced.
The access cost is an attribute manually calculated for each access mode of the pin, and is used for determining the sequence of trying each access mode when the pin is accessed in the subsequent wiring, and the access mode with lower access cost is preferentially selected when the pin is wired.
7. In the integrated circuit design optimization wiring method provided by the embodiment of the invention, in step S2, the characteristic dimension comprises the width and/or the area of the pins; the number of access points required per pin is at least 2. It should be noted that, by considering the width or the area of the pins, or the width and the area of the pins in combination, the number of access points required for each pin may be determined, and generally, at least two access points are required for each pin, and the number of access points required for the pins with larger area is relatively larger.
8. The embodiment of the invention also provides electronic equipment, which comprises a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor; when the electronic equipment runs, the processor and the storage medium are communicated through a bus, and the processor executes program instructions to realize the integrated circuit design optimization wiring method.
The electronic device has the same advantages as the integrated circuit design optimization wiring method, and the detailed description is omitted.
9. The embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, which when being run by a processor, realizes the integrated circuit design optimizing wiring method.
The computer readable storage medium has the same advantages as the above-mentioned integrated circuit design optimizing wiring method, and will not be described herein.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of an integrated circuit design optimizing wiring method according to a first embodiment of the present invention.
Fig. 2 is a second flowchart of an integrated circuit design optimizing wiring method according to the first embodiment of the present invention.
Fig. 3 is a schematic flow chart of performing step S6 after step S5 in an integrated circuit design optimization routing method according to a first embodiment of the present invention.
Fig. 4 is a second flowchart of the integrated circuit design optimization routing method according to the first embodiment of the present invention, in which step S6 (including steps S61, S62, and S63) is performed after step S5.
Fig. 5 is a flowchart illustrating a method for optimizing wiring of an integrated circuit design according to a first embodiment of the present invention in step S3.
Fig. 6 is a flowchart illustrating an integrated circuit design optimization routing method according to a first embodiment of the present invention, in which a virtual track is added to obtain available access points in step S4.
Fig. 7 is a schematic frame diagram of an electronic device according to a second embodiment of the present invention.
Fig. 8 is a schematic diagram of a frame of a computer-readable storage medium according to a third embodiment of the present invention.
Fig. 9 is a wiring result obtained before and after optimizing wiring by performing the optimized wiring method of the first embodiment provided by the fourth embodiment of the present invention.
Fig. 10 is a variation in wire length and number of vias obtained before and after optimizing wirings by performing the optimized wiring method of the first embodiment provided by the fourth embodiment of the present invention.
The attached drawings are used for identifying and describing:
1. an electronic device; 11. A processor; 12. A storage medium; 121. program instructions; 13. A bus;
2. a computer-readable storage medium; 21. Computer program.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples of implementation in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the embodiments provided herein, it should be understood that "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Those skilled in the art will also appreciate that the embodiments described in the specification are alternative embodiments and that the acts and modules referred to are not necessarily required for the present invention.
In various embodiments of the present invention, it should be understood that the sequence numbers of the foregoing processes do not imply that the execution sequences of the processes should be determined by the functions and internal logic of the processes, and should not be construed as limiting the implementation of the embodiments of the present invention.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In the design of very large scale integrated circuit chips, with the continuous progress of technology nodes, the feature size of transistors is continuously reduced, and each new technology is started to introduce increasingly complex design rules, so that the access of each pin is limited by the increasingly complex design rules, and different pins interfere with each other, and the problem of accessing pins becomes one of the most challenging problems faced by the physical design of the back end of the chip.
Existing pin access technologies lack consideration for design rules on the one hand and are typically grid-based on the other hand, and do not handle well for pins that are not on the grid, both of which can lead to routing difficulties and even excessive design rule violations that remain unhandled.
In this regard, the present invention provides a pin access scheme that meets design rule requirements for pins that are applicable to either or not on a grid, and by this scheme, the routing results in the very large scale integrated circuit chip design process are optimized.
Referring to fig. 1, a first embodiment of the present invention provides an optimized wiring method for an integrated circuit design, which is applied to a very large scale integrated circuit design, and includes the following steps:
S1: providing a pin, and selecting via hole information and stub parameters for pin access according to design rules;
s2: calculating the characteristic size of the pins, determining the number of access points according to the characteristic size, and defining the number of the access points as an expected value;
s3: selecting a priority access point from a wiring layer where a pin is positioned and a wiring layer above the pin, verifying the priority access point according to the via information and the stub parameters by using a design rule to obtain the number of available access points, executing a step S4 if the number of available access points is less than the expected value, otherwise executing a step S5;
s4: acquiring the available access points by reducing step sizes and/or increasing virtual tracks among tracks of a wiring layer above the pins, and executing step S5 when the number of the available access points is not less than the expected value;
s5: checking whether the pin access mode of each available access point and the adjacent pin access mode violate the design rule, leaving available access points which do not violate the design rule, ending the calculation of the pin if the number of the remaining available access points is not less than the expected value, otherwise executing step S4.
Further, referring to fig. 2, the method provided in the first embodiment specifically includes the following steps (wherein step S3 includes S31 and S32, step S4 includes S41 and S42, and step S5 includes S51, S52 and S53):
S1: providing a pin and obtaining pin information thereof, and selecting via hole information and stub parameters for pin access according to design rules;
s2: calculating the characteristic size of the pins according to the pin information, determining the number of access points according to the characteristic size, and defining the number of the access points as an expected value;
s31: selecting a priority access point from a wiring layer where the pin is positioned and a wiring layer above the pin, and verifying the priority access point according to the via information and the short-circuit parameters by using a design rule to obtain the number of available access points;
s32: judging whether the number of available access points is less than an expected value, if so, executing S41, and if not, executing S51;
s41: obtaining available access points by reducing the step size of the priority access points and/or increasing virtual tracks between tracks of a wiring layer above the pins;
s42: judging whether the number of available access points is not less than an expected value, if so, executing S51, and if not, continuing to execute S41;
s51: checking whether the pin access mode of each available access point and the adjacent pin access mode violate the design rule, and leaving the available access points which do not violate the design rule;
s52: judging whether the number of available access points is not less than an expected value, if yes, executing S53, and if not, continuing to execute S41;
S53: the calculation for this pin is ended.
It should be noted that, in the process of designing a very large scale integrated circuit chip, the routing result must meet the constraint of the design rule, so the invention provides a pin access scheme which is applicable to the pins on the grid or not and meets the requirement of the design rule, and the routing result is optimized through the pin access scheme.
It can be understood that the invention provides guidance for the access pins during detailed wiring by calculating the access points and access modes of the pins conforming to the design rules before wiring, and solves the technical problems that the wiring in the ultra-large scale integrated circuit design is easy to cause poor wiring results and even the surplus design rule violations cannot be processed because the access modes of the access pins are unreasonable.
It can be further understood that by the design, on the premise of following the design rule, a proper access scheme is provided for the pins on the grid or not, so that the convergence speed of the design rule violation in the detailed wiring is increased, and the wiring result is optimized.
For the step S1, the via hole information mainly comprises a pattern of a via hole layer and a shell positioned on a wiring layer, wherein the via hole is used for connecting metals of adjacent wiring layers, the shell is used for ensuring that the via hole can have enough contact area with the metals of the wiring layers during manufacturing so as to realize the connection, and the area of the shell needs to be larger than a certain value, and the width is preferentially selected to be consistent with the default width of the wiring layer; the determination of the parameters of the short wire is considered similar to the consideration of the through hole and the shell, the short wire is required to meet the design rule requirement of the minimum area, and the wire with the default line width is preferentially selected.
In step S31, simulation access is performed at each priority access point by using the selected via hole information and the stub parameters, and whether the design rule is violated after access is verified, mainly whether the design rule violation exists between the via hole or the stub of the access pin and the structure existing in the standard unit, for example, whether the space between the access pin and the via hole or other pins existing in the standard unit is larger than the minimum space; by the method, the possibility that the selected pin access mode violates the design rule can be reduced.
Further, for steps S31 and S41, in the design of the very large scale integrated circuit chip, there are a plurality of tracks of wiring on the plane of one wiring layer, these tracks may be uneven and may overlap each other, and there are obstacles (such as circuit components, power supply channels, etc.) in the wiring dispersed in some wiring layers, so that the wiring difficulty increases; the tracks of a certain wiring layer and the upper wiring layer of the wiring layer are perpendicular to each other, so that the tracks of the upper layer and the tracks of the wiring layer have a plurality of intersection points when projected into the same plane from top to bottom, and the intersection points are called grid points of the wiring layer.
In general, if the standard cell or macro cell is reasonably designed, the step S51 may be directly performed after the step S3 (including S31 and S32) is performed, without performing the step S41.
For step S41, the available access points are acquired by performing the step-down step size and/or the step-up of the virtual track until the available access points are sufficiently large, and the step is ended when the number thereof is not less than the expected value, and it is noted that the available access points obtained by performing step S41 are not affected by the grid points.
For steps S51 and S52, it is checked whether the pin access mode of each available access point and the adjacent pin access mode violate the design rule, for example, when one pin and its adjacent pin are accessed through the via holes at the same time, whether the two via holes meet the minimum pitch rule of the via holes, whether the minimum pitch rule is met between the shells of the two via holes, etc.; it should be noted that if there is a design rule violation between all access modes of an available access point and access modes of adjacent pins, then the available access point is considered to be unavailable, and the number of available access points remaining is compared with an expected value.
As an alternative embodiment, referring to fig. 3, after the calculation of the pins is finished in step S5, the following steps are performed:
s6: if the number of the remaining available access points is not less than the expected value, continuing to return to the step S1 to execute the calculation of the next pin until the calculation of all pins is completed, and outputting the access points and the pin access modes which accord with the design rules.
It should be noted that, when step S6 is performed, the number of available access points is not less than the expected value.
Further, referring to fig. 4, step S6 specifically includes the following steps (step S6 includes S61, S62 and S63):
s61: judging whether the calculation of all pins is finished, if yes, executing S63, if not, executing S62, and then entering into a step S1 for circulation;
s62: continuing to execute the calculation of the next pin;
s63: and (3) finishing calculation of all pins, and outputting an access point and a pin access mode which accord with the design rule.
It will be appreciated that when the number of available access points is sufficiently large, the calculation for that pin is ended, and the calculation for the next pin is continued; when step S62 is executed, the process returns to step S1 to perform calculation of the next pin.
Further, referring to fig. 5, the selecting a preferred access point in step S3 specifically includes the following steps:
S31a: acquiring pins and wiring layers above the pins, wherein the wiring layer where the pins are positioned is defined as M x The wiring layers above the pins are M in turn x+1 ，M x+2 ；
S31b: at the pins and M x+1 On the track crossing line of (a) by crossing lineIs the midpoint of the starting point, M x+2 Selecting a priority access point for the step size.
In the design of the very large scale integrated circuit chip, the wiring layer M x And the upper wiring layer M x+1 Is perpendicular to each other, so that the wiring layer M x+1 Track and wiring layer M of (2) x When projected from top to bottom into the same plane, there are a plurality of intersections called wiring layers M x Is a grid of grid points.
It will be appreciated that the priority access point is selected only with M x+1 Is related to the intersection of the track and the pin, M x Is independent of the track of the pin, and is not affected by whether the pin is on the grid.
Specifically, in step S41 of step S4, two actions of reducing the step size and increasing the virtual track are alternately performed, and after the step size is reduced or the virtual track is increased, the number of available access points is calculated.
It will be understood that, after any one of the operations of reducing the step size and increasing the virtual track is performed, the number of available access points is calculated, and step S5 is performed when the number of available access points is equal to or greater than the expected value (in this embodiment, step S51 is performed when the number of available access points is equal to or greater than the expected value), otherwise, the two operations of reducing the step size and increasing the virtual track are performed alternately.
It should be noted that, the step size is reduced to half the original step size, and such operations are performed up to the step size of the first priority access point (i.e., M x+2 Track pitch of layers)If the available access points are not enough, an attempt is made to reduce the step size directly to the first +.>To make the last attempt; if the number of available access points is insufficient, a warning message is given to indicate the condition of the pin, and the pin is preferentially accessed in the subsequent actual wiring process to avoid the circumferenceThe other pins of the edge have an effect on the access to this pin.
It can be understood that the step size reduction is tracked, for example, the step is firstly skipped from step S52 of step S5 to step S41, after enough available access points are obtained in step S4 (including S41 and S42), the step returns to step S51 of step S5, and finally the number of remaining available access points is still insufficient to execute step S4 again, and the step size reduction is performed on the basis of executing step S4 last time, so as to avoid that the calculated step size repetition results in repeated selection of available access points.
Further, referring to fig. 6, the following steps are required to obtain the available access point by adding a virtual track:
S41a: when the virtual track is added for the first time, taking the sum M x+1 Is parallel to the adjacent actual track and has a distance M x+1 Layer track pitchIs a virtual track;
s41b: the n-th (n > 1) increased virtual track whose spacing from the actual track is reduced to the n-1-th increased virtual track-to-actual track spacing。
It should be noted that such operations are performed at most to a virtual track pitch of M x+1 Layer track pitchIf the available access points are not enough, an attempt is made to reduce the pitch of the virtual tracks directly to the first +.>To make the last attempt; if the number of available access points is insufficient, a warning message is reported to indicate the condition of the pin, and the pin is preferentially accessed in the subsequent actual wiring process, so that the influence of other peripheral pins on the access of the pin is avoided.
It will be appreciated that the addition of virtual tracks will only take place within the scope of the standard cell being calculated and therefore will not be so numerous; in addition, the addition of the virtual track is also tracked, for example, the step S52 of the step S5 is firstly skipped to the step S41, after enough available access points are obtained in the step S4 (including the step S41 and the step S42), the step S51 of the step S5 is returned, and finally, the number of remaining available access points is still insufficient to execute the step S4 again, and the addition of the virtual track is performed on the basis of executing the step S4 last time, so as to avoid the repeated selection of the available access points caused by the repeated addition of the virtual track.
Specifically, in step S5, in step S51, a candidate set is added to the pin access mode corresponding to the available access point that does not violate the design rule, where the candidate set includes the access cost of each pin access mode.
It will be appreciated that the checking of available access points is mainly whether there is a design rule violation between the via or stub of the access pin and the structure itself present in the standard cell, by which design the likelihood of the selected access mode violating the design rule can be reduced.
The access cost is an attribute which is manually calculated and added to various access modes of the pin, and is used for determining the sequence of trying various access modes when the pin is accessed in subsequent wiring, and the access mode with lower access cost can be preferentially selected when the pin is wired.
The access cost is high or low, firstly, the available access point is positioned on the intersection line of the actual track and the pin, or on the intersection line of the virtual track and the pin, and the step length when the point is selected; secondly, the connection cost is also adjusted according to the magnitude of the connection influence of the pin connection mode on the peripheral pins when the design rule is considered later, for example, whether the direction of the pin connection mode is consistent with the subsequent wiring mode or not.
It should be noted that, in step S41 of step S4, the available access points are obtained by performing a step-down or a step-up of the virtual track, and when the number of available access points reaches the expected value, step S51 is performed to check the available access points, and an access cost is given to the pin access mode that does not violate the design rule, wherein the access cost of the access mode added in step S41 increases with the step-down, thereby affecting the sequence when selecting in the detailed wiring.
As another alternative embodiment, in step S2, the feature size includes a width and/or an area of the pin.
Further, the number of access points required per pin is at least 2.
It should be noted that, by considering the width or the area of the pins, or the width and the area of the pins in combination, at least the number of access points required for each pin may be determined. Generally, at least two access points are required for each pin, and the number of access points required for pins with larger area is correspondingly larger.
Referring to fig. 7, a second embodiment of the present invention provides an electronic device 1, including a processor 11, a storage medium 12, and a bus 13, where the storage medium 12 stores program instructions 121 executable by the processor 11;
When the electronic device 1 is in operation, the processor 11 communicates with the storage medium 12 via the bus 13, and the processor 11 executes the program instructions 121 to implement the integrated circuit design optimization routing method described above.
It will be appreciated that when the electronic device 1 of the second embodiment of the present invention is running, the processor 11, when executing the program instructions 121, may implement an integrated circuit design optimization routing method as described in the first embodiment above.
Specifically, the electronic device 1 may be a computing device having a data processing function, the storage medium 12 is used for storing a program, and the processor 11 calls the program stored in the storage medium 12 to execute the above-described integrated circuit design optimization wiring method; it should be noted that the electronic device 1 has the same advantages as the above-mentioned integrated circuit design optimizing wiring method, and will not be described herein.
The processor 11 may be a general purpose processor such as a Central Processing Unit (CPU), digital Signal Processor (DSP), application Specific Integrated Circuit (ASIC), field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or may implement or perform the methods, steps, and logic blocks disclosed in embodiments of the present application. The general purpose processor may be a microprocessor or any conventional processor or the like.
The steps of a method disclosed in connection with the embodiments of the present application may be embodied as being performed by a hardware processor, or as being performed by a combination of hardware and software modules within a processor.
Referring to fig. 8, a third embodiment of the present invention provides a computer readable storage medium 2 having a computer program 21 stored thereon, the computer program 21 implementing the above-described integrated circuit design optimization routing method when executed by a processor.
It will be appreciated that the computer program 21 is stored in the computer readable storage medium 2 in the third embodiment of the present invention, and the computer program 21 is called by the processor to perform an integrated circuit design optimizing wiring method described in the first embodiment.
It should be noted that the computer-readable storage medium 2 has the same advantages as the above-mentioned method for optimizing the wiring of the integrated circuit design, and will not be described herein.
In particular, the computer-readable storage medium 2 may include at least one type of storage medium, which may include, for example, flash memory, hard disk, multimedia card, card memory, random Access Memory (RAM), static Random Access Memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, and so forth; alternatively, the computer-readable storage medium 2 includes a nonvolatile computer-readable storage medium that can be used to store nonvolatile software programs, nonvolatile computer-executable programs, and modules.
In particular, the computer-readable storage medium 2 has a storage space for a computer program 21 for performing any of the method steps described above, which programs can be read from or written to one or more computer program products; alternatively, the computer program 21 can be compressed in a suitable form.
Referring to fig. 9 and fig. 10, in a fourth embodiment of the present invention, the pin access and routing result obtained by executing the method for optimizing the routing of the integrated circuit design according to the first embodiment is compared with the pin access and routing result obtained by not executing the optimization, so as to further explain the objects, technical schemes and technical effects of the present invention.
It should be noted that the fourth embodiment of the present invention adopts a 14nm integrated circuit design, and the exemplary embodiments described herein are only for explaining the present invention, and are not intended to limit the application scope of the present invention, and any modification, equivalent replacement, improvement, etc. made within the principles of the present invention should be included in the protection scope of the present invention.
As can be seen from fig. 7 and 8, the technical scheme of the present invention can significantly optimize the wiring result of the same integrated circuit design, so that the wiring time is greatly shortened, the supporting condition of the design rule is greatly optimized, and the wire length and the number of vias are also slightly optimized.
Compared with the prior art, the integrated circuit design optimizing wiring method, the electronic equipment and the storage medium provided by the invention have the following advantages:
1. the integrated circuit design optimizing wiring method provided by the embodiment of the invention is applied to the design of a very large scale integrated circuit and comprises the following steps: s1: providing a pin and obtaining pin information thereof, and selecting via hole information and stub parameters for pin access according to design rules; s2: calculating the characteristic size of the pins according to the pin information, determining the number of access points according to the characteristic size, and defining the number of the access points as an expected value; s3: selecting a priority access point from the wiring layer where the pin is positioned and the wiring layer above the pin, verifying the priority access point according to the via information and the short-circuit parameters by using a design rule to obtain the number of available access points, executing the step S4 if the number of available access points is less than an expected value, otherwise executing the step S5; s4: acquiring available access points between tracks of a wiring layer above the pins by reducing the step length of the priority access points and/or increasing virtual tracks, and executing step S5 when the number of the available access points is not less than an expected value; s5: checking whether the pin access mode of each available access point and the adjacent pin access mode violate the design rule, leaving available access points which do not violate the design rule, ending the calculation of the pin if the number of the remaining available access points is not less than the expected value, otherwise executing the step S4.
It should be noted that, in the process of designing a very large scale integrated circuit chip, the routing result must meet the constraint of the design rule, so the invention provides a pin access scheme which is applicable to the pins on the grid or not and meets the requirement of the design rule, and the routing result is optimized through the pin access scheme.
It can be understood that the invention provides guidance for the access pins during detailed wiring by calculating the access points and access modes of the pins conforming to the design rules before wiring, and solves the technical problems that the wiring in the ultra-large scale integrated circuit design is easy to cause poor wiring results and even the surplus design rule violations cannot be processed because the access modes of the access pins are unreasonable.
It can be further understood that by the design, on the premise of following the design rule, a proper access scheme is provided for the pins on the grid or not, so that the convergence speed of the design rule violation in the detailed wiring is increased, and the wiring result is optimized.
2. After finishing the calculation of the pins in step S5, the integrated circuit design optimizing wiring method provided by the embodiment of the invention executes the following steps: s6: if the number of the remaining available access points is not less than the expected value, continuing to return to the step S1 to execute the calculation of the next pin until the calculation of all pins is completed, and outputting the access points and the pin access modes which accord with the design rules. It will be appreciated that when the number of available access points is sufficiently large, the calculation of that pin is terminated, and the calculation of the next pin is performed instead until the calculation of all pins is completed, and then the access points and pin access modes are output.
3. The invention is thatIn the integrated circuit design optimization wiring method provided in the embodiment, the step S3 of selecting the priority access point specifically includes the following steps: s31a: acquiring pins and wiring layers above the pins, wherein the wiring layer where the pins are positioned is defined as M x The wiring layers above the pins are M in turn x+1 ，M x+2 The method comprises the steps of carrying out a first treatment on the surface of the S31b: at the pins and M x+1 On the track intersection line of (1), taking the midpoint of the intersection line as a starting point, M x+2 Selecting a priority access point for the step size.
In the design of the very large scale integrated circuit chip, the wiring layer M x And the upper wiring layer M x+1 Is perpendicular to each other, so that the wiring layer M x+1 Track and wiring layer M of (2) x When projected from top to bottom into the same plane, there are a plurality of intersections called wiring layers M x Is a grid of grid points.
It will be appreciated that the priority access point is selected only with M x+1 Is related to the intersection of the track and the pin, M x Is independent of the track of the pin, and is not affected by whether the pin is on the grid.
4. In the integrated circuit design optimization wiring method provided by the embodiment of the invention, in step S4, two actions of reducing the step length and increasing the virtual track are alternately executed, and after the step length is reduced or the virtual track is increased, the number of available access points is calculated.
It can be understood that, after any one of the operations of reducing the step size and increasing the virtual track is performed, the number of available access points is calculated, and when the number of available access points is greater than or equal to the expected value, step S5 is performed, otherwise, the two operations of reducing the step size and increasing the virtual track are performed alternately.
It should be noted that, the step size is reduced to half the original step size, and such operations are performed up to the step size of the first priority access point (i.e., M x+2 Track pitch of layers)If the available access points are not enough, an attempt is made to reduce the step size directly to the first +.>To make the last attempt.
5. The integrated circuit design optimizing wiring method provided by the embodiment of the invention obtains the available access point by adding the virtual track, and the method comprises the following steps: when the virtual track is added for the first time, taking the sum M x+1 Is parallel to the adjacent actual track and has a distance M x+1 Layer track pitchIs a virtual track; an n-th (n > 1) increased virtual track whose spacing from the actual track is reduced to +.1-th increased virtual track and the spacing between the actual tracks>。
It should be noted that such operations are performed at most to a virtual track pitch of M x+1 Layer track pitchIf the available access points are not enough, an attempt is made to reduce the pitch of the virtual tracks directly to the first +.>To make the last attempt.
6. In step S5, a candidate set is added to a pin access mode corresponding to an available access point that does not violate a design rule, where the candidate set includes an access cost of each pin access mode.
It will be appreciated that the checking of available access points is mainly whether there is a design rule violation between the via or stub of the access pin and the structure itself present in the standard cell, by which design the likelihood of the selected access mode violating the design rule can be reduced.
The access cost is an attribute manually calculated for each access mode of the pin, and is used for determining the sequence of trying each access mode when the pin is accessed in the subsequent wiring, and the access mode with lower access cost is preferentially selected when the pin is wired.
7. In the integrated circuit design optimization wiring method provided by the embodiment of the invention, in step S2, the characteristic dimension comprises the width and/or the area of the pins; the number of access points required per pin is at least 2. It should be noted that, by considering the width or the area of the pins, or the width and the area of the pins in combination, the number of access points required for each pin may be determined, and generally, at least two access points are required for each pin, and the number of access points required for the pins with larger area is relatively larger.
8. The embodiment of the invention also provides electronic equipment, which comprises a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor; when the electronic equipment runs, the processor and the storage medium are communicated through a bus, and the processor executes program instructions to realize the integrated circuit design optimization wiring method.
The electronic device has the same advantages as the integrated circuit design optimization wiring method, and the detailed description is omitted.
9. The embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, which when being run by a processor, realizes the integrated circuit design optimizing wiring method.
The computer readable storage medium has the same advantages as the above-mentioned integrated circuit design optimizing wiring method, and will not be described herein.
The above describes in detail an integrated circuit design optimizing wiring method, an electronic device and a storage medium disclosed in the embodiments of the present invention, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above description of the embodiments is only used to help understand the method and core idea of the present invention; meanwhile, as for those skilled in the art, according to the idea of the present invention, there are changes in the specific embodiments and the application scope, and in summary, the present disclosure should not be construed as limiting the present invention, and any modifications, equivalent substitutions and improvements made within the principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. An integrated circuit design optimizing wiring method applied to ultra-large scale integrated circuit design is characterized by comprising the following steps:
s1: providing a pin and obtaining pin information thereof, and selecting via hole information and stub parameters for pin access according to design rules;
s2: calculating the characteristic size of the pins according to the pin information, determining the number of access points according to the characteristic size, and defining the number of the access points as an expected value;
s3: selecting a priority access point from a wiring layer where a pin is and a wiring layer above the pin, performing analog access at the priority access point according to via information and a stub parameter, verifying according to a design rule to obtain the number of available access points, and executing a step S4 if the number of available access points is less than the expected value, otherwise executing a step S5;
s4: acquiring available access points by reducing the step length of the prior access points and/or increasing virtual tracks among tracks of a wiring layer above the pins, and executing step S5 when the number of the available access points is not less than the expected value;
s5: checking whether the pin access mode of each available access point and the adjacent pin access mode violate the design rule, leaving available access points which do not violate the design rule, ending the calculation of the pin if the number of the remaining available access points is not less than the expected value, otherwise executing step S4.
2. The integrated circuit design optimization routing method of claim 1, wherein after finishing the calculation of pins in step S5, the following steps are performed:
s6: and if the number of the remaining available access points is not less than the expected value, continuing to return to the step S1 to execute the calculation of the next pin until the calculation of all pins is completed, and outputting the access points and the pin access modes which accord with the design rules.
3. The method for optimizing routing of an integrated circuit design of claim 2, wherein selecting a preferred access point in step S3 comprises the steps of:
s31a: acquiring pins and wiring layers above the pins, wherein the wiring layer where the pins are positioned is defined as M x The wiring layers above the pins are M in turn x+1 ，M x+2 ；
S31b: at the pins and M x+1 On the track intersection line of (1), taking the midpoint of the intersection line as a starting point, M x+2 Selecting a priority access point for the step size.
4. The integrated circuit design optimization routing method of claim 3, wherein:
in step S4, two actions of reducing the step size and increasing the virtual track are alternately executed, and after the step size is reduced or the virtual track is increased, the number of available access points is calculated.
5. The integrated circuit design optimization routing method of claim 4, wherein the available access points are acquired by adding virtual tracks by:
When the virtual track is added for the first time, taking the sum M x+1 Is parallel to the adjacent actual track and has a distance M x+1 Layer track pitchIs a virtual track;
the n-th (n > 1) increased virtual track whose spacing from the actual track is reduced to the n-1-th increased virtual track-to-actual track spacing。
6. The integrated circuit design optimization routing method of claim 5, wherein:
in step S5, adding a pin access mode corresponding to the available access point that does not violate the design rule into an alternative set, where the alternative set includes an access cost of each pin access mode.
7. The integrated circuit design optimization routing method of claim 1, wherein:
in step S2, the feature size includes a width and/or an area of the pin.
8. The integrated circuit design optimization routing method of claim 7, wherein:
the number of access points required per pin is at least 2.
9. An electronic device, characterized in that:
comprising a processor, a storage medium, and a bus, the storage medium storing program instructions executable by the processor;
when the electronic device is in operation, the processor communicates with the storage medium via the bus, and execution of the program instructions by the processor implements the integrated circuit design optimization routing method of any one of claims 1-8.
10. A computer-readable storage medium having stored thereon a computer program, characterized by:
the computer program, when executed by a processor, implements the integrated circuit design optimization routing method of any one of claims 1-8.
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