KR20220130547A - Integrated circuit providing increased pin access points and method for designing the same - Google Patents

Abstract

An integrated circuit may comprise: a first cell comprising a first sub-pattern extending in a first direction along a first track in a first wiring layer; and a second cell comprising a second sub-pattern extending from the first wiring layer in the first direction along a first track and spaced apart from the first sub-pattern at least a minimum separation distance of the first wiring layer, wherein the first sub-pattern may correspond to a pin of the first cell, and the second sub-pattern may be farther apart from the boundary of the first cell and the second cell than that of the first sub-pattern. Therefore, the present invention is capable of reducing a routing congestion.

Description

INTEGRATED CIRCUIT PROVIDING INCREASED PIN ACCESS POINTS AND METHOD FOR DESIGNING THE SAME

The technical idea of the present disclosure relates to an integrated circuit, and more particularly, to an integrated circuit providing increased pin access points and a method of designing the same.

Due to the development of the semiconductor process, the size of a device may decrease and the number of devices included in an integrated circuit may increase. The integrated circuit may include patterns for connecting elements, and the patterns may have a complex structure due to a high degree of integration and a reduced size of the elements. Accordingly, routing to interconnect devices can be critical to the performance and efficiency of integrated circuits.

The technical idea of the present disclosure provides an integrated circuit and a method of designing an integrated circuit having high performance and efficiency by providing increased pin access points.

An integrated circuit according to an aspect of the inventive concept includes a first cell including a first sub-pattern extending in a first direction along a first track in a first wiring layer, and along a first track in a first wiring layer and a second cell including a second sub-pattern extending in the first direction and spaced apart from the first sub-pattern by at least a minimum separation distance of the first wiring layer, wherein the first sub-pattern is connected to a pin of the first cell. may correspond, and the second sub-pattern may be spaced apart from the boundary of the first cell and the second cell further than the first sub-pattern.

An integrated circuit according to an aspect of the present disclosure includes a first cell including a first sub-pattern and a second sub-pattern respectively extending in a first direction along a first track and a second track in a first wiring layer; and a second cell including a third sub-pattern and a fourth sub-pattern extending in a first direction along the first track and the second track in the first wiring layer, wherein the first sub-pattern includes: The pattern and the first wiring layer may be spaced apart from each other by at least a minimum separation distance, and may be spaced apart from the boundary between the first cell and the second cell by a first distance or more, and the second sub-pattern may be spaced apart from the fourth sub-pattern by a minimum separation distance or more, A second distance or more may be spaced apart from the boundary, and the first distance and the second distance may be different.

A method for designing an integrated circuit according to an aspect of the inventive concept includes: obtaining input data defining a plurality of cells and connections between the plurality of cells; based on the input data, arranging the plurality of cells; The method may include, based on the input data, routing a plurality of pins of the disposed plurality of cells, and generating output data defining a layout of the integrated circuit, wherein routing the pins comprises: extending a first sub-pattern corresponding to a pin of one cell and extending in a first direction from the first wiring layer, one of a plurality of pin access points including a pin access point of an extended portion of the first sub-pattern The method may include disposing a via in the junction, and generating a first upper pattern connected to the via and extending in a second direction perpendicular to the first direction in the second wiring layer.

An integrated circuit according to an aspect of the inventive concept includes a plurality of sub-patterns extending in a first direction from a first wiring layer and at least a second direction extending in a second direction perpendicular to the first direction at a first pitch A first cell including one gate electrode, a filler cell disposed adjacent to the first cell and having a width of a first pitch, a second cell disposed adjacent to the filler cell, and a second pitch in the second wiring layer may include a plurality of upper patterns extending in a second direction along the plurality of tracks, the second pitch may be less than the first pitch, and the plurality of lower patterns may include a first one of the plurality of tracks on the pillar cell. and a first sub-pattern extending to intersect the track.

According to an integrated circuit and method according to an exemplary embodiment of the present disclosure, pin access points for routing may be increased, and thus routing congestion may be reduced in the integrated circuit.

Further, according to the integrated circuit and method according to the exemplary embodiment of the present disclosure, delay occurring in the interconnection due to reduced routing congestion may be reduced, and thus the performance of the integrated circuit may be increased.

Further, according to the integrated circuit and method according to the exemplary embodiment of the present disclosure, the area for routing may be reduced due to reduced routing congestion, and thus the efficiency of the integrated circuit may be increased.

In addition, according to the integrated circuit and method according to the exemplary embodiment of the present disclosure, routing can be easily performed in the design process of the integrated circuit, and thus the time-to-market of the integrated circuit is shortened. can be

Effects that can be obtained in the exemplary embodiments of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned are common knowledge in the art to which exemplary embodiments of the present disclosure pertain from the following description. It can be clearly derived and understood by those who have That is, unintended effects of carrying out the exemplary embodiments of the present disclosure may also be derived by those of ordinary skill in the art from the exemplary embodiments of the present disclosure.

1A to 1D are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure.
2 is a diagram illustrating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
3 is a plan view illustrating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
4A and 4B are cross-sectional views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure.
5A and 5B are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure.
6 is a plan view illustrating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
7A to 7C are plan views illustrating examples of layouts of integrated circuits according to exemplary embodiments of the present disclosure.
8A and 8B are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure.
9A and 9B are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure.
10 is a flowchart illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.
11 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure.
12 is a plan view illustrating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
13 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure.
14A and 14B are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure.
15 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure.
16 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure.
17 is a block diagram illustrating a system on chip (SoC) according to an exemplary embodiment of the present disclosure.
18 is a block diagram illustrating a computing system including a memory for storing a program according to an exemplary embodiment of the present disclosure.

1A to 1D are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure. Specifically, the top views of FIGS. 1A-1D show NAND2 cells C1a, C1b, C1c, C1d and NAND2 cells C1a, C1b, C1c, corresponding to a two-input NAND gate generating an output from two inputs. Layouts including wires extending on C1d) are schematically shown in a plane consisting of X and Y axes.

In this specification, the X-axis direction and the Y-axis direction may be referred to as a first direction and a second direction, respectively, and the Z-axis direction may be referred to as a third direction or a vertical direction. A plane made up of the X and Y axes may be referred to as a horizontal plane, and a component disposed in the +Z direction relative to other components may be referred to as being above other components, and a -Z component relative to other components. A component disposed in a direction may be referred to as being below another component. In addition, the area of the component may refer to a size occupied by the component in a plane parallel to the horizontal plane, and the width of the component may refer to a length in a direction perpendicular to the direction in which the component is extended. Also, when components are coupled or electrically connected, the components may be referred to as being connected. In the drawings of the present specification, only some layers may be shown for convenience of illustration, and vias are located above the upper patterns to indicate connections between upper and lower patterns of different wiring layers. Although it is located below the pattern, it can be displayed on the upper pattern. Also, a pattern made of a conductive material, such as a pattern of a wiring layer, may be referred to as a conductive pattern or simply a pattern.

An integrated circuit may include a plurality of cells. A cell is a unit of layout included in an integrated circuit, and may be designed to perform a predefined function and may be referred to as a standard cell. An integrated circuit may include a number of different cells, and the cells may be arranged and arranged according to a plurality of rows. For example, as shown in FIGS. 1A to 1D , the NAND2 cells C1a, C1b, C1c, and C1d may have a length H in the Y-axis direction, have a width H, and are arranged in a row extending in the X-axis direction. can be placed. A cell arranged in one row, such as NAND2 cells C1a, C1b, C1c, C1d, may be referred to as a single height cell, while two or more adjacent to each other, such as cell C08 in FIG. 6 , Cells arranged consecutively in rows may be referred to as multiple height cells.

As shown in FIGS. 1C-1D , the patterns for supplying a positive supply voltage (VDD) and a negative supply voltage (VSS) (or ground potential) to the NAND2 cells (C1a, C1b, C1c, C1d) are row may extend in the X-axis direction along the boundaries of , and corresponding patterns may be referred to as power rails. In addition, in the row, an active region in which the P-type transistor is formed and an active region in which the N-type transistor is formed may extend in the X-axis direction parallel to each other. 1 , at least one active pattern may extend in the X-axis direction in the active region, and the active pattern may cross the gate electrode extending in the Y-axis direction to form a transistor.

In some embodiments, when the active pattern in the form of a fin extends in the X-axis direction, the active pattern and the gate electrode may form a fin field effect transistor (FinFET). Exemplary embodiments of the present disclosure will be mainly described with reference to structures including a FinFET, but it will be appreciated that structures including a transistor having a structure different from that of the FinFET may also be applied. For example, the active pattern may include a plurality of nanowires that are spaced apart from each other in the Z-axis direction and extend in the X-axis direction, and the cell is a GAAFET (gate) formed by the plurality of nanowires with the gate electrode all around FET). In addition, the active pattern may include a plurality of nanosheets that are spaced apart from each other in the Z-axis direction and extend in the X-axis direction, and the cell is a multi-bridge (MBCFET) in which the plurality of nanosheets are formed with a gate electrode. channel FET). In addition, since the nanosheets for the P-type transistor and the nanosheets for the N-type transistor are separated by a dielectric wall, the N-type transistor and the P-type transistor may include a ForkFET having a closer structure. In addition, the cell may include a vertical FET (VFET) having a structure in which source/drain regions are spaced apart from each other in the Z-axis direction with a channel region interposed therebetween, and a gate electrode surrounds the channel region. Cells may also include field effect transistors (FETs), such as complementary FETs (CFETs), negative FETs (NCFETs), carbon nanotube (CNT) FETs, and the like, and include bipolar junction transistors and other three-dimensional transistors. You may.

In an integrated circuit, a cell may have a pin connected to the outside of the cell. For example, the NAND2 cells C1a, C1b, C1c, and C1d may include patterns extending in the X-axis direction from the M1 layer as a wiring layer, and the patterns are input for receiving the inputs A and B. It may include pins and an output pin for outputting an output Y. The pin may be connected to a pattern extending in the Y-axis direction from the M2 layer, which is an upper wiring layer of the M1 layer, through a via (ie, a via of the V1 layer) disposed on the pin. In some embodiments, patterns extending from one wiring layer may have directionality. For example, as shown in FIGS. 1A to 1D , the patterns in the M1 layer may extend in the X-axis direction along the first to fifth tracks T11 to T15, and the patterns in the M2 layer may extend in the Y-axis direction. can be extended to In this specification, the M1 layer may be referred to as a lower wiring layer, and patterns extending in the X-axis direction from the M1 layer may be referred to as lower patterns. Also, the M2 layer may be referred to as an upper wiring layer, and patterns extending in the Y-axis direction in the M2 layer may be referred to as upper patterns.

In some embodiments, the patterns in the wiring layer may extend in the Y-axis direction at a pitch different from a pitch of gate electrodes extending in the Y-axis direction, that is, a contacted poly pitch (CPP). For example, as shown in FIGS. 1A to 1D , the gate electrodes may extend in the Y-axis direction with a first pitch P1 , while patterns in the M2 layer may have a second pitch smaller than the first pitch P1 . The pitch P2 may extend in the Y-axis direction. Accordingly, upper patterns may be arranged in various ways even on the same cell, that is, tracks along which upper patterns extend may be arranged in various ways on the same cell. 1A-1D illustrate upper patterns that are differently arranged on the same NAND2 cells C1a, C1b, C1c, and C1d, but exemplary embodiments of the present disclosure are limited to the upper patterns shown in FIGS. 1A-1D . It is noted that it does not In addition, examples in which the ratio of the first pitch P1 (or CPP) and the second pitch P2 is 3:2 will be described herein, but exemplary embodiments of the present disclosure provide other ratios (eg, 4: 3, etc.) is also applicable.

1A and 1B , the upper patterns may include upper patterns aligned with the gate electrode. In this specification, the aligned components may have central axes overlapping in the Z-axis direction. For example, two of the five patterns of the M2 layer shown in FIG. 1A may be each aligned with the gate electrodes at points marked with two stars, and the remaining three patterns may not be aligned with the gate electrodes. it can't be Also, two of the five patterns of the M2 layer shown in FIG. 1B may be respectively aligned with the gate electrodes at points marked with two stars, and the remaining three patterns may not be aligned with the gate electrodes. have.

1C and 1D , upper patterns may include upper patterns aligned with source/drain contacts. The source/drain contacts may be disposed between the gate electrodes, and accordingly, as shown in FIGS. 1C and 1D , the source/drain contacts may extend in the second direction at a first pitch P1 . For example, two of the four patterns of the M2 layer shown in FIG. 1C may each be aligned with the source/drain contacts at the points marked with two stars, and the remaining two patterns are the source/drain contacts. It may not be aligned with the fields. Also, one of the five patterns of the M2 layer shown in FIG. 1D may be source/drain aligned at a point indicated by one star, and the remaining four patterns may not be aligned with the source/drain contacts.

As described above, the lower pattern corresponding to the pin of the cell may be connected to the upper pattern through a via disposed on the lower pattern. The location of the via placed on the pin may depend on the location from which the upper pattern extends. For example, as shown in FIGS. 1A to 1C , when upper patterns are arranged differently, the vias of the V1 layer may also be arranged differently. Accordingly, positions where vias can be placed on the pin, ie, pin access points, may vary according to the arrangement of upper patterns. A decrease in pin access points may cause routing congestion when connecting pins of a cell, and routing congestion may result in an increase in area as well as delay of a signal.

As will be described below with reference to the drawings, according to an exemplary embodiment of the present disclosure, pin access points for routing may increase, and thus routing congestion may decrease in an integrated circuit. In addition, delay of a signal due to reduced routing congestion may be reduced, and thus the performance of the integrated circuit may be increased. Also, the area for routing may be reduced due to reduced routing congestion, and thus the efficiency of the integrated circuit may be increased. In addition, routing may be easily performed in the design process of the integrated circuit, and accordingly, the time to market of the integrated circuit may be shortened.

2 is a diagram illustrating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the upper part of FIG. 2 shows the layout around the boundary E between cells included in the integrated circuit in a plane consisting of X and Y axes, and the lower part of FIG. 2 shows a cross-section taken along X-X'.

Referring to FIG. 2 , the first and second sub-patterns M11 and M12 may extend in the X-axis direction along the same track in the M1 layer. The first and second sub-patterns M11 and M12 may be pins included in different cells, respectively. As illustrated in FIG. 2 , the first and second sub-patterns M11 and M12 may be spaced apart from each other in the X-axis direction. In some embodiments, the first and second sub-patterns M11 and M12 may be formed by separating one sub-pattern extending in the X-axis direction through an M1 cut, and the same track in the M1 layer. They can be spaced apart from each other by my minimum separation distance. Also, the first and second sub-patterns M11 and M12 may be spaced apart from the boundary E by the same distance.

The first to fourth upper patterns M21 to M24 may extend in the Y-axis direction along the first to fourth tracks T21 to T24 in the M2 layer. In order to connect the first lower pattern M11 and the second upper pattern M22 , a first via V11 may be disposed at a point where the first lower pattern M11 and the second track T22 intersect. . In addition, in order to connect the second lower pattern M12 and the fourth upper pattern M24, the second via V12 may be disposed at a point where the second lower pattern M12 and the fourth track T24 intersect. can

The pattern of the wiring layer may be required to extend more than a certain length on both sides of the via for stable connection with the via, and the extended portion of the pattern may be referred to as a via overlap. If the via overlap is not secured, the pattern and/or via may not be formed in the same way as designed in the semiconductor process, and thus the connection between the pattern and the via may become unstable. Referring to FIG. 2 , the second via V12 may be disposed on the fourth track T24 spaced apart from the boundary E, and thus the second sub-pattern M12 is a via overlap (ie, M1 ). -V1 overlap) can be provided. On the other hand, the first via V11 may be disposed on the second track T22 adjacent to the boundary E, and the via overlap may occur due to the first sub-pattern M11 spaced apart from the boundary E. may not be secured. Accordingly, a point at which the first sub-pattern M11 and the second track T22 intersect may not be used as a pin access point, and a point at which the second sub-pattern M12 and the third track T23 intersect. Also, it may not be usable as a pin access point.

As will be described below with reference to the drawings below, according to an exemplary embodiment of the present disclosure, the second sub-pattern M12 may be shortened in the X-axis direction, and the first sub-pattern M11 may be shortened in the X-axis direction. can be extended Accordingly, a via overlap for the first via V11 may be secured, and a point where the extended first sub-pattern M11 and the second track T22 intersect may be used as a pin access point.

3 is a plan view illustrating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the plan view of FIG. 3 shows a layout including first and second AOI22 cells C31 and C32 adjacent to each other. As shown in FIG. 3 , the first and second AOI22 cells C31 and C32 may be disposed adjacent to each other in the same row, and may have mutually flipped structures. As shown in FIG. 3 , the lower patterns may extend in the X-axis direction along the first to fifth tracks T11 to T15 of the M1 layer, and the upper patterns may include the first to 36th tracks T21 of the M2 layer. to T36) in the Y-axis direction.

The first AOI22 cell C31 may include four input pins A0, A1, B0, and B1 and one output pin Y. As shown in FIG. 3 , the two input pins A1 and B0 may extend in the X-axis direction along the third track T13 of the M1 layer, and the other two input pins A0 and B1 are M1 . It may extend in the X-axis direction along the fifth track T15 of the layer, and the output pin Y may extend in the Y-axis direction along the fifth track T25 of the M2 layer. In addition, the second AOI22 cell C32 may include four input pins A0', A1', B0', and B1' and one output pin Y'. As shown in FIG. 3 , the two input pins A1 ′ and B0 ′ may extend in the X-axis direction along the third track T13 of the M1 layer, and the other two input pins A0 ′, B1 . ') may extend in the X-axis direction along the fifth track T15 of the M1 layer, and the output pin Y' may extend in the Y-axis direction along the twelfth track T32 of the M2 layer.

The number of pin access points may be important for routing a cell comprising a large number of pins in a limited area, such as the first and second AOI22 cells 31 , 32 . As indicated by a solid circle (●) in FIG. 3 , the input pin A0 in the first AOI22 cell C31 may have three pin access points, and other input pins A1, B0, B1 ) each may have two pin access points each. Similarly, in the second AOI22 cell C32, the input pin A0' may have three pin access points, and each of the other input pins A1, B0, B1 may have two pin access points.

The input pin B0 of the first AOI22 cell C31 and the input pin B0' of the second AOI22 cell C32 extending from the third track T13 of the M1 layer are connected to the first and second AOI22 cells C31 , C32 may be spaced apart from each other by a distance D around the boundary E of the C32. In addition, the input pin B1 of the first AOI22 cell C31 and the input pin B1' of the second AOI22 cell C32 extending from the fifth track T15 of the M1 layer are also centered on the boundary E. They may be spaced apart from each other by a distance (D). In some embodiments, the distance D may be greater than or equal to the minimum separation distance within the same track of the M1 layer.

As described above with reference to FIG. 2 , a point in a pin that does not provide sufficient via overlap may not be used as a pin access point. For example, as indicated by an empty circle (○) in FIG. 3 , the input pins B0 and B1 of the first AOI22 cell C31 intersect the eighth track T28 of the M2 layer. They may not be usable as pin access points. Also, points where the input pins B0 ′ and B1 ′ of the second AOI22 cell C32 intersect the ninth track T29 of the M2 layer may not be used as pin access points. Accordingly, upper patterns extending along the eighth and ninth tracks T28 and T29 of the M2 layer may not be used for routing pins of the first and second AOI22 cells C31 and C32, and routing freedom is reduced. may be limited.

In some embodiments, the sub-patterns of the M1 layer may be formed by multi-patterning, and thus the pitch of the sub-patterns may be reduced. For example, the first group of sub-patterns extending along the first track T11, the third track T13, and the fifth track T15 of the M1 layer may be simultaneously formed, and the second track of the M1 layer The second group of sub-patterns extending along the ( T12 ) and the fourth track ( T14 ) may be simultaneously formed.

In some embodiments, the M1 cut may be used to separate sub-patterns of some of a plurality of groups of sub-patterns, thereby simplifying a process for manufacturing an integrated circuit. For example, the input pins B0 of the first AOI22 cell C31 and the input pins B0' of the second AOI22 cell C32, which are sub-patterns of the first group, are formed as one sub-pattern and then in the M1 cut. can be separated from each other, and thus can be separated from each other by a distance D as shown in FIG. 3 . On the other hand, each of the sub-patterns M12 and M13 of the first AOI22 cell C31 and the sub-patterns M15 and M16 of the second AOI22 cell C32, which are sub-patterns of the second group, includes at least one sub-pattern They may be simultaneously formed by the process, and thus may be spaced apart from each other further than the distance D as shown in FIG. 3 .

In some embodiments, two or more sub-patterns of the same group may be separated from each other by the same M1 cut, ie, an M1 cut having a shape extending in the Y-axis direction. For example, the input pins B0 and B1 and the lower pattern M11 of the first AOI22 cell C31 and the input pins B0' and B1' of the second AOI22 cell C32 included in the first group And for the lower pattern M14, one M1 cut extending in the Y-axis direction along the boundary E may be used.

4A and 4B are cross-sectional views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure. Specifically, the cross-sectional views of FIGS. 4A and 4B show examples of another cross-section of the integrated circuit of FIG. 3 along Y1-Y1'. Although not shown in FIGS. 4A and 4B , a gate spacer may be formed on a side surface of the gate electrode, and a gate dielectric layer may be formed between the gate electrode and the gate spacer and on the lower surface of the gate electrode. In addition, a barrier film may be formed on the surface of the contact and/or via. Hereinafter, content overlapping with each other with respect to FIGS. 4A and 4B will be omitted.

In some embodiments, the integrated circuit may include a FinFET. Referring to Figure 4a, the substrate 10 may be bulk silicon or silicon-on-insulator (SOI), as non-limiting examples, SiGe, silicon germanium on insulator (SGOI), InSb, PbTe compound, InAs, phosphide, GaAs or GaSb may be included. A field insulating layer 20 may be formed on the substrate 10 . The field insulating layer 20 may include, as a non-limiting example, SiO ₂ , SiN, SiON, SiOCN, or a combination of two or more thereof. In some embodiments, the field insulating layer 20 may surround some of the side surfaces of the active pattern, that is, the fin, as shown in FIG. 4A . First to fourth interlayer insulating layers 31 to 34 may be formed on the field insulating layer 20 .

The first to fourth fins F1 to F4 may extend in the X-axis direction from the field insulating layer 20 . A device isolation layer ISO may extend in the X-axis direction between the first and second fins F1 and F2 and the third and fourth fins F3 and F4, and the device isolation layer ISO allows the first and second active regions RX1 and RX2 may be separated. The first to fourth fins F1 to F4 may pass through the field insulating layer 20 and cross the gate electrode G extending in the Y-axis direction. In some embodiments, the integrated circuit may include a different number of pins than shown in FIG. 4A .

As a non-limiting example, the gate electrode G may include Ti, Ta, W, Al, Co, or a combination of two or more thereof, and may include Si or SiGe other than metal. In addition, the gate electrode G may be formed by stacking two or more conductive materials, for example, a work function control film including TiN, TaN, TiC, TaC, TiAlC, or a combination of two or more thereof, and W or Al. It may include a peeling conductive film including. The gate contact CB may pass through the second interlayer insulating layer 32 to be connected to the gate electrode G, and the gate via VB may pass through the third interlayer insulating layer 33 to provide the gate contact CB and the input pin. (A1) can be connected. Accordingly, the input pin A1 may be electrically connected to the gate electrode G through the gate via VB and the gate contact CB. In some embodiments, differently as shown in FIG. 4A , the gate contact CB may be omitted, and the input pin A1 may be connected through a gate via penetrating the second and third interlayer insulating layers 32 and 33 . It may be electrically connected to the gate electrode G.

In some embodiments, the integrated circuit may include a transistor in a gate all around (GAA) structure in which nanowires and/or nanosheets are surrounded by a gate electrode. For example, as shown in FIG. 4B , the first nanosheet stack NS1 including three nanosheets NS11 , NS12 , and NS13 in the first active region RX1 connects the gate electrode G to the first nanosheet stack NS1 . It may pass through and extend in the X-axis direction. The first nanosheet stack NS1 may be doped with an N-type impurity to form a PFET. In addition, in the second active region RX2 , a second nanosheet stack NS2 including three nanosheets NS21 , NS22 , and NS23 may extend through the gate electrode G in the X-axis direction. . The second nanosheet stack NS2 may be doped with a P-type impurity to form an NFET. In some embodiments, the nanosheet stack may include a different number of nanosheets as shown in FIG. 4B .

5A and 5B are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure. Specifically, the plan view of FIG. 5A shows a layout including first and second AOI22 cells C41 and C42 adjacent to each other, and the plan view of FIG. 5B shows the first and second AOI22 cells C41 and C42 of FIG. 5A It shows the layout in which the upper patterns are arranged. 5A and 5B , the lower patterns may extend in the X-axis direction along the first to fifth tracks T11 to T15 of the M1 layer, and the upper patterns include first to 36th tracks of the M2 layer. It may extend in the Y-axis direction along the tracks T21 to T36. Hereinafter, content that overlaps with the description of FIG. 3 among the descriptions of FIGS. 5A and 5B will be omitted.

In some embodiments, a pin of the cell may extend, and the extended portion of the pin may have a pin access point. For example, as shown in FIG. 5A , the input pin B0 of the first AOI22 cell C41 may be shortened in the X-axis direction, and thus the input pin B0 of FIG. 3 from the boundary E may be further apart. The input pin B0' of the second AOI22 cell C42 may extend in the X-axis direction to be spaced apart from the input pin B0 of the first AOI22 cell C41 by a first distance D1, and thus Accordingly, the boundary E may be closer than the input pin B0' of FIG. 3 . In some embodiments, the first distance D1 may be greater than or equal to the minimum separation distance within the same track of the M1 layer. As a result, the input pin B0 of the first AOI22 cell C41 may be farther apart from the boundary E than the input pin B0' of the second AOI22 cell C42. In some embodiments, the input pin B0' of the second AOI22 cell C42 may not intersect the boundary E, differently as illustrated in FIG. 5A . Due to the extension of the input pin B0' of the second AOI22 cell C42, the intersection of the input pin B0' of the second AOI22 cell C42 and the ninth track T29 of the M2 layer is the pin may be used as an access point, and thus the input pin B0' of the second AOI22 cell C42 may have three pin access points, and different from the example of FIG. 3 , the ninth of the M2 layer in FIG. 5A . An upper pattern extending along track T29 may be used to route input pin B0' of second AOI22 cell C42. Also, the input pin B0 of the first AOI22 cell C41 may have two pin access points despite a shorter length than the input pin B0 of FIG. 3 .

Referring to FIG. 5A , the input pin B1' of the second AOI22 cell C42 may be shortened in the X-axis direction, and thus the input pin B1' of FIG. 3 may be spaced apart from the boundary E. can The input pin B1 of the first AOI22 cell C41 may extend in the X-axis direction to be spaced apart from the input pin B1' of the second AOI22 cell C42 by a second distance D2, and thus Accordingly, the boundary E may be closer than the input pin B1 of FIG. 3 . In some embodiments, the second distance D2 may be greater than or equal to the minimum separation distance within the same track of the M1 layer. As a result, the input pin B1 ′ of the second AOI22 cell C42 may be farther apart from the boundary E than the input pin B1 of the first AOI22 cell C41 . In some embodiments, the input pin B1 of the first AOI22 cell C41 may not intersect the boundary E, differently as illustrated in FIG. 5A . Due to the extension of the input pin B1 of the first AOI22 cell C41, the point where the input pin B1 of the first AOI22 cell C41 and the eighth track T28 of the M2 layer intersect is a pin access point can be used as , and thus the input pin B1 of the first AOI22 cell C41 may have three pin access points, and different from the example of FIG. 3 , the eighth track T28 of the M2 layer in FIG. 5A . ) may be used to route the input pin B1 of the first AOI22 cell C41. In addition, the input pin B1 ′ of the second AOI22 cell C42 may have two pin access points despite a shorter length than the input pin B1 ′ of FIG. 3 .

Referring to FIG. 5B , upper patterns may extend in the Y-axis direction along the first to sixth tracks T21 to T36 of the M2 layer. In some embodiments, at least some of the upper patterns of FIG. 5B may have a different length than that shown in FIG. 5B . As described above, a point where the input pin B0' of the second AOI22 cell C42 and the ninth track T29 of the M2 layer intersect may be used as a pin access point, and thus the second AOI22 cell C42 ), a via of the V1 layer connecting the input pin B0 ′ and the first upper pattern M21 may be disposed. Also, a point where the input pin B1 of the first AOI22 cell C41 and the eighth track T28 of the M2 layer intersect may be used as a pin access point, and accordingly, the input pin of the first AOI22 cell C41 may be used as a pin access point. A via of the V1 layer connecting ( B1 ) and the second upper pattern M22 may be disposed.

6 is a plan view illustrating a layout of an integrated circuit 50 according to an exemplary embodiment of the present disclosure. As shown in FIG. 6 , the integrated circuit 50 may include a plurality of cells C01 to C12 arranged in first to third rows R1 to R3, and not only the single height cell of FIG. 6 , It may include a multi-height cell (ie, C08). Power rails may extend along the boundaries of the first to third rows R1 to R3 in the X-axis direction. The first to third rows R1 to R3 may have first to third heights H1 to H3 . In some embodiments, the first to third heights H1 to H3 may be the same, and at least two heights of the first to third heights H1 to H3 may be different.

In some embodiments, the integrated circuit 50 may include a cell that includes a pin and performs a predefined function, ie, a function cell as well as a filler cell. As described above with reference to FIG. 3 and the like, when cells having a large number of pins, that is, cells having a high pin density, are disposed adjacent to each other in a limited area, a filler cell may be disposed to secure an additional pin access point. . For example, as shown in FIG. 6 , a filler cell may be disposed between the two cells C02 and C03 in the first row R1 , and a filler cell may be disposed between the two cells C04 and C05 , in the first row R1 . can be placed. In addition, a filler cell may be disposed between the two cells C08 and C09 in the second row R2 , and a filler cell may be disposed between the two cells C11 and C08 in the third row R3 . have. In some embodiments, the filler cell may have a first pitch P1 of the gate electrodes, that is, a width (ie, a length in the X-axis direction) of 1 CPP.

In some embodiments, a pin of a functional cell adjacent to the filler cell may extend into the interior of the filler cell, and the extended portion may have a pin access point. As described above with reference to FIGS. 1A to 1D , the first pitch P1 between the gate electrodes and the second pitch P2 between the upper patterns may be different, and accordingly, referring to FIGS. 7A and 7B , As described below, a filler cell may be deployed to provide more pin access points.

7A to 7C are plan views illustrating examples of layouts of integrated circuits according to exemplary embodiments of the present disclosure. Specifically, the plan view of FIG. 7A shows a layout including the filler cell C61 and the AOI22 cell C62, and the plan view of FIG. 7B shows the layout including the AOI22 cell C63 and the filler cell C64, and FIG. A plan view of 7c shows a layout in which upper patterns are disposed on the AOI22 cell C63 and the filler cell C64 of FIG. 7b . The AOI22 cell C62 of FIG. 7A and the AOI22 cell C63 of FIG. 7B may each have structures including fins extending from the first AOI22 cell C31 of FIG. 3 . Hereinafter, FIGS. 7A to 7C will be described with reference to FIG. 3 .

Referring to FIG. 7A , the lower patterns may extend in the X-axis direction along the first to fifth tracks T11 to T15 of the M1 layer, and the upper patterns include the first to ninth tracks T21 to T29 of the M2 layer. ) along the Y-axis direction. As shown in FIG. 7A , the filler cell C61 may be disposed on the left side of the AOI22 cell C62 . The input pins A0 and A1 of the AOI22 cell C62 may extend into the filler cell C61 across the boundary E, thus extending, as indicated by a solid circle ? in FIG. 7A . Two pin access points may additionally occur at points where the input pins A0 and A1 and the second track T22 (or boundary E) of the M2 layer intersect. However, the points where the extended input pins A0 and A1 and the first track T21 of the M2 layer intersect may lack via overlap, and thus, as indicated by a hollow circle (○) in FIG. 7A , the extended Points at which the input pins A0 and A1 and the second track T22 of the M2 layer intersect may not be used as pin access points.

Referring to FIG. 7B , the lower patterns may extend in the X-axis direction along the first to fifth tracks T11 to T15 of the M1 layer, and the upper patterns may include the second to eleventh tracks T22 to T31 of the M2 layer. ) along the Y-axis direction. As shown in FIG. 7B , the filler cell C64 may be disposed on the right side of the AOI22 cell C63 . The input pins B0, B1 of the AOI22 cell C63 may extend into the interior of the filler cell C64 across the boundary E, thus, as indicated by a solid circle ? in FIG. 7B , Four pin access points may be additionally generated at points where the extended input pins B0 and B1 and the ninth and tenth tracks T29 and T30 of the M2 layer intersect. Accordingly, the AOI22 cell C63 of FIG. 7B may have more pin access points than the AOI22 cell C62 of FIG. 7A , and may provide a higher degree of routing freedom.

Like the filler cell C64 of FIG. 7B , among the two filler cells that can be disposed on both sides of the functional cell, a filler cell that provides more additional pin access points may be selected during the design process of the integrated circuit, and the selected filler cell It may be disposed on one side of the functional cell. For example, among the two filler cells, a filler cell in which additional pin access points are generated may be disposed adjacent to the functional cell.

Referring to FIG. 7C , upper patterns may extend in the Y-axis direction along second to eleventh tracks T22 to T31 of the M2 layer. In some embodiments, at least some of the upper patterns of FIG. 7C may have a different length than that shown in FIG. 7C . As described above, the intersection of the input pin B1 of the AOI22 cell C63 and the ninth track T29 of the M2 layer can be used as a pin access point, and accordingly, the input pin B1 of the AOI22 cell C63 A via of the layer V1 connecting the first upper pattern M21 of the layer B1) and the layer M2 may be disposed. In addition, a point where the input pin B0 of the AOI22 cell C63 and the tenth track T30 of the M2 layer intersect may be used as a pin access point, and accordingly, the input pin B0 of the AOI22 cell C63 and A via of the V1 layer connecting the second upper pattern M22 of the M2 layer may be disposed.

8A and 8B are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure. Specifically, FIG. 8A shows a layout including the AOI22 cell C7, and the plan view of FIG. 8B shows a layout in which upper patterns are disposed on the AOI22 cell C7 of FIG. 8A. 8A and 8B , the lower patterns may extend in the X-axis direction along the first to fifth tracks T11 to T15 of the M1 layer, and the upper patterns may include the first to eighth tracks of the M2 layer. It may extend in the Y-axis direction along the tracks T21 to T28.

Referring to FIG. 8A , the AOI22 cell C7 may include four input pins A0, A1, B0, B1 and one output pin Y. Referring to FIG. As shown in FIG. 8A , the input pin A0 may extend in the X-axis direction along the third track T13 of the M1 layer, and may have three pin access points. The input pin B1 may extend in the X-axis direction along the third track T13 of the M1 layer, and may have two pin access points. The input pin B0 may extend in the X-axis direction along the fourth track T14 of the M1 layer, and may have two pin access points. The input pin A1 may extend in the X-axis direction along the fifth track T15 and may have two pin access points. Also, the output pin Y may extend in the Y-axis direction along the fifth track T25 of the M2 layer. A first sub-pattern M11 for an internal signal that is different from the input signals and output signals of the AOI22 cell C7 may extend in the X-axis direction along the first track T11 of the M1 layer.

Referring to FIG. 8B , upper patterns may extend in the Y-axis direction along the first to eighth tracks T21 to T28 of the M2 layer. In some embodiments, at least some of the upper patterns of FIG. 8B may have a different length than that shown in FIG. 8B . As shown in FIG. 8B , vias may be disposed in some of the pin access points of FIG. 8A , and the pins may be connected to upper patterns through vias. For example, the input pin A1 may be connected to the first upper pattern M21 through a via disposed at a point intersecting the second track T22 of the M2 layer, and the input pin A0 may be connected to the M2 layer. It may be connected to the second upper pattern M22 through a via disposed at a point intersecting the third track T23 .

When the pin access points are clustered in mutually adjacent tracks of the M1 layer (eg, the third to fifth tracks (T13 to T15) of the M1 layer), as shown in FIG. 8A , it intersects with one track of the M2 layer A via may be disposed in only one of the pin access points. On the other hand, as described below with reference to FIGS. 9A and 9B , when the pin access points are spread on mutually spaced tracks, two or more of the pin access points intersect one track in the M2 layer. Vias may be placed in the fields.

9A and 9B are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure. Specifically, FIG. 9A shows a layout including the AOI22 cell C8, and the plan view of FIG. 9B shows a layout in which upper patterns are disposed on the AOI22 cell C8 of FIG. 9A. 9A and 9B , the lower patterns may extend in the X-axis direction along the first to fifth tracks T11 to T15 of the M1 layer, and the upper patterns include the first to eighth tracks of the M2 layer. It may extend in the Y-axis direction along the tracks T21 to T28.

Referring to FIG. 9A , the AOI22 cell C8 may include four input pins A0, A1, B0, and B1 and one output pin Y. As shown in FIG. 9A , the input pin A0 may extend in the X-axis direction along the first track T11 of the M1 layer, and may have three pin access points. The input pin B1 may extend in the X-axis direction along the third track T13 of the M1 layer, and may have two pin access points. The input pin B0 may extend in the X-axis direction along the fourth track T14 of the M1 layer, and may have two pin access points. The input pin A1 may extend in the X-axis direction along the fifth track T15 of the M1 layer, and may have two pin access points.

In the AOI22 cell C8 of FIG. 9A , the first sub-pattern M11 for the internal signal may extend in the X-axis direction along the second track T12 of the M1 layer, and the input pin A0 is the M1 layer It may extend in the X-axis direction along the first track T11. Accordingly, the input pins A0 and A1 having pin access points at the points intersecting the second and third tracks T22 and T23 of the M2 layer have a higher Y axis than the input pins A0 and A1 of FIG. 8A . direction may be spaced apart.

Referring to FIG. 9B , upper patterns may extend in the Y-axis direction along the first to eighth tracks T21 to T28 of the M2 layer. In some embodiments, at least some of the upper patterns of FIG. 9B may have a different length than that shown in FIG. 9B . As shown in FIG. 9B , vias may be disposed in some of the pin access points of FIG. 9A , and the pins may be connected to upper patterns through vias. For example, the input pin A0 may be connected to the third upper pattern M23 through a via disposed at a point intersecting the second track T22 of the M2 layer, and the input pin A1 of the M2 layer It may be connected to the fourth upper pattern M24 through a via disposed at a point crossing the second track T22 . The third and fourth upper patterns M23 and M24 on the same track of the M2 layer, that is, on the second track T22 may be spaced apart by a third distance D3 in the Y-axis direction, and the third distance D3 ) may be greater than or equal to the minimum separation distance within the same track of the M2 layer. In some embodiments, the third and fourth upper patterns M23 and M24 may be formed by separating one oblique pattern extending along the second track T22 of the M2 layer through an M2 cut, and , may be spaced apart from each other by the minimum separation distance within the same track of the M2 layer.

As shown in FIG. 9B , the vias for the two input pins A0 and A1 may be on the second track T22 of the M2 layer, so that the upper pattern extending along the other track of the M2 layer is different. It can be used for signal routing. For example, the second upper pattern M22 extending along the second track T22 of the M2 layer in FIG. 7B may be used for routing of the input pin A0 of the AOI22 cell C7, while FIG. 9B . The fifth upper pattern M25 extending along the second track T22 of the M2 layer may be used for signal routing independently of the AOI22 cell C8. Accordingly, routing freedom may be improved, and routing congestion may be reduced.

10 is a flowchart illustrating a method for manufacturing an integrated circuit (IC) in accordance with an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 10 represents an example of a method for manufacturing an integrated circuit (IC) that provides increased pin access points. As shown in FIG. 10 , a method for manufacturing an integrated circuit (IC) may include a plurality of steps S10 , S30 , S50 , S70 , and S90 .

The cell library (or standard cell library) D12 may include information about cells, for example, function information, characteristic information, layout information, and the like. In some embodiments, the cell library D12 may define cells including fins extending along the outermost one of the tracks of the lower layer, as described above with reference to FIG. 9A . In some embodiments, the cell library D12 may define cells including a sub-pattern having a shortened length, as described below with reference to FIG. 12 . The design rule D14 may include requirements that the layout of the integrated circuit (IC) must comply with. For example, the design rule D14 may include requirements for a space between patterns, a minimum width of a pattern, a routing direction of a wiring layer, and the like. In some embodiments, design rule D14 may define a minimum separation distance within the same track of an interconnect layer.

In step S10 , a logic synthesis operation for generating a netlist D13 from the RTL data D11 may be performed. For example, a semiconductor design tool (eg, a logic synthesis tool) performs logic synthesis with reference to the cell library D12 from RTL data D11 created as VHDL (VHSIC Hardware Description Language) and HDL (Hardware Description Language) such as Verilog. By performing , it is possible to generate a bitstream or a netlist D13 including a netlist. The netlist D13 may correspond to an input of place and routing, which will be described later, and may be referred to herein as input data.

In step S30, cells may be deployed. For example, a semiconductor design tool (eg, a P&R tool) may arrange cells used in the netlist D13 with reference to the cell library D12. In some embodiments, the semiconductor design tool may place additional cells (eg, pillar cells) in addition to the cells used in netlist D13 . An example of step S30 will be described later with reference to FIG. 15 .

In step S50, the pins of the cells may be routed. For example, the semiconductor design tool may generate interconnections that electrically connect the output pins and input pins of the disposed cells, and generate layout data D15 defining the disposed cells and the generated interconnections. can create The interconnects may include vias in a via layer and/or a pattern in an interconnect layer. The layout data D15 may have a format such as, for example, GDSII, and may include geometric information of cells and interconnections. The semiconductor design tool may refer to the design rule D14 while routing the pins of the cells. The layout data D15 may correspond to the output of placement and routing, and may be referred to herein as output data. Step S40 alone, or steps S20 and S40 collectively, may be referred to as a method of designing an integrated circuit, and examples of step S50 will be described below with reference to FIGS. 11 and 15 .

In step S70, an operation of manufacturing a mask may be performed. For example, in photolithography, optical proximity correction (OPC) for correcting distortion such as refraction caused by characteristics of light may be applied to the layout data D15. Patterns on the mask may be defined to form patterns disposed on a plurality of layers based on the data to which OPC is applied, and at least one mask (or photomask) for forming patterns of each of the plurality of layers may be manufactured. can In some embodiments, the layout of the integrated circuit (IC) may be limitedly modified in step S60, and the limited modification of the integrated circuit (IC) in step S70 is performed after optimizing the structure of the integrated circuit (IC). As a process, it may be referred to as design polishing.

In step S90, an operation of fabricating an integrated circuit (IC) may be performed. For example, an integrated circuit (IC) may be manufactured by patterning a plurality of layers using the at least one mask manufactured in operation S70 . FEOL (front-end-of-line) includes, for example, planarization and cleaning of a wafer, forming trenches, forming wells, gate electrodes and forming a source and a drain, and by FEOL, individual devices, such as transistors, capacitors, resistors, and the like, can be formed on a substrate. Also, back-end-of-line (BEOL) can include, for example, silicidation of the gate, source and drain regions, adding a dielectric, planarizing, forming holes, adding a metal layer. , forming a via, forming a passivation layer, and the like, and by BEOL, individual devices such as transistors, capacitors, resistors, etc. may be interconnected. In some embodiments, a middle-of line (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed on the individual devices. The integrated circuit (IC) can then be packaged in a semiconductor package and used as a component in various applications.

11 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 11 shows an example of step S50 of FIG. 10 . As described above with reference to FIG. 10 , pins of cells may be routed in step S50 ′ of FIG. 11 . 11 , step S50 ′ may include a plurality of steps S52 , S54 , and S56 .

Referring to FIG. 11 , the lower pattern may be extended in step S52. In some embodiments, as described above with reference to FIGS. 5A , 7A and 7B , a fin of a cell may extend in the X-axis direction to proximate a boundary with an adjacent cell. In some embodiments, the fin may extend to be spaced apart from a sub-pattern of an adjacent cell extending in the same track by at least a minimum distance according to a design rule. In some embodiments, the fin may extend into the interior of an adjacent cell and may intersect a boundary between cells. An example of step S52 will be described later with reference to FIG. 13 .

In operation S54, a via may be disposed in one of the plurality of pin access points. Pins included in the cell may have at least one pin access point. In addition, the extended pin in step S52 may additionally have at least one pin access point in the extended portion. Accordingly, the via may be disposed in one of the plurality of pin access points including the extended portion. Then, in step S56, a higher-order pattern may be generated. For example, an upper pattern connected to the via disposed in step S54 and extending in the Y-axis direction may be generated.

12 is a plan view illustrating a layout of an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the plan view of FIG. 12 shows a layout including first and second AOI22 cells C111 and C112 adjacent to each other. 12 , the first and second AOI22 cells C111 and C112 may be disposed adjacent to each other in the same row. 12 , the lower patterns may extend in the X-axis direction along the first to fifth tracks T11 to T15 of the M1 layer, and the upper patterns may include the first to 36th tracks T21 of the M2 layer. to T36) in the Y-axis direction.

The first and second AOI22 cells C111 and C112 may include shortened pins. For example, the first AOI22 cell C111 may include an input pin B0 shorter than the input pin B0 of FIG. 3 , and two pin access points are maintained at the input pin B0 of FIG. 12 . can be In addition, the second AOI22 cell C112 may include an input pin B0' shorter than the input pin B0' of FIG. 3, and two pin access points at the input pin B0' of FIG. can be maintained Accordingly, the input pin B0 may be spaced apart from the boundary E by a fourth distance D4, and the input pin B0' may also be spaced apart from the boundary E by a fourth distance D4.

As described above with reference to FIG. 11 , the pin may be extended to secure an additional pin access point, and the cell may include a shortened pin so as not to interfere with the extension of the pin of an adjacent cell. For example, as shown in FIG. 12 in step S30 of FIG. 10 , the first and second AOI22 cells C111 and C112 may be disposed, and the first and second AOI22 cells C111 and C112 are illustrated in FIG. By extending the input pins B0 ′ and B1 of FIG. 12 in step S52 of FIG. 11 , they may be modified like the first and second AOI22 cells C41 and C42 of FIG. 5A .

13 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 13 shows an example of step S52 of FIG. 11 . As described above with reference to FIG. 11 , the sub-pattern may be extended in step S52 ′ of FIG. 13 . 13 , step S52' may include steps S52_2 and S52_4.

Referring to FIG. 13 , sub-patterns may be merged in step S52_2. For example, sub-patterns each included in cells arranged adjacently and extending on the same track may be merged by extending.

In step S52_4, a cut may be arranged in the merged sub-pattern. The cut may separate the merged sub-patterns, and the sub-patterns separated by the cut may be spaced apart from each other by a minimum separation distance within the same track of the lower wiring layer, that is, the M1 layer.

14A and 14B are plan views illustrating examples of a layout of an integrated circuit according to exemplary embodiments of the present disclosure. Specifically, the plan view of FIG. 14A shows the operation in which step S52' of FIG. 13 is performed in first and second AOI22 cells C131 and C132 adjacent to each other, and the plan view of FIG. 14B shows first and second AOI22 cells C131 and C132 adjacent to each other. In steps C133 and C134, operation S52' of FIG. 13 is performed. Hereinafter, content overlapping with each other in the description of FIGS. 14A and 14B will be omitted.

Referring to FIG. 14A , the first and second AOI22 cells C131 and C132 may be disposed adjacent to each other in the same row. As shown in FIG. 14A , the lower patterns may extend in the X-axis direction along the first to fifth tracks T11 to T15 of the M1 layer, and the upper patterns may include the first to 36th tracks T21 of the M2 layer. to T36) in the Y-axis direction.

After the first and second AOI22 cells C131 and C132 are disposed, the semiconductor design tool may merge sub-patterns of the first and second AOI22 cells C131 and C132 by extending them. For example, as shown in FIG. 14A , the input pin B0 of the first AOI22 cell C131 and/or the input pin B0' of the second AOI22 cell C132 may extend, and the first The input pin B0 of the AOI22 cell C131 and the input pin B0' of the second AOI22 cell C132 may be merged. Also, the input pin B1 of the first AOI22 cell C131 and/or the input pin B1′ of the second AOI22 cell C132 may extend, and the input pin B1 of the first AOI22 cell C131 may be extended. ) and the input pin B1' of the second AOI22 cell C132 may be merged.

In some embodiments, a cut of the lower wiring layer may be disposed in the merged lower pattern. For example, as shown in FIG. 14A , the first cut ( X1) may be disposed, and a second cut X2 is disposed in a lower pattern in which the input pin B1 of the first AOI22 cell C131 and the input pin B1' of the second AOI22 cell C132 are merged. can be In some embodiments, the cut may not be aligned with the boundary E. For example, as shown in FIG. 14A , the first cut X1 may be disposed such that the center point is to the left of the boundary E, and accordingly, the input pin B0' of the second AOI22 cell C132. may have an additional pin access point at a point that intersects the ninth track T29 of the M2 layer. In addition, the second cut X2 may be disposed so that the center point is on the right side of the boundary E. Accordingly, the input pin B1 of the first AOI22 cell C131 may have an additional pin access point at a point crossing the eighth track T28 of the M2 layer. As shown in FIG. 14A , the sub-patterns separated by the first and second cuts X1 and X2 may be spaced apart from each other by a fifth distance D5, and the fifth distance is the minimum spaced apart within the same track of the M1 layer. It can respond to distance.

Referring to FIG. 14B , the first and second AOI22 cells C133 and C134 may be disposed adjacent to each other in the same row. In some embodiments, the cut of the lower wiring layer may be disposed in two or more merged lower patterns. For example, as shown in FIG. 14B , a sub-pattern in which the input pin B0 of the first AOI22 cell C133 and the input pin B0' of the second AOI22 cell C134 are merged, and the first AOI22 A third cut X3 may be disposed in a lower pattern in which the input pin B1 of the cell C133 and the input pin B1 ′ of the second AOI22 cell C134 are merged. As shown in FIG. 14B , the third cut X3 may extend in the Y-axis direction, and may separate sub-patterns extending from the third and fifth tracks T13 and T15 of the M1 layer. As shown in FIG. 14A , the sub-patterns separated by the third cut X3 may be spaced apart from each other by a sixth distance D6, and in some embodiments, the sixth distance D6 may be the sixth distance D6 of FIG. 14A . 5 may be equal to the distance D5. In some embodiments, the semiconductor design tool is configured to facilitate routing of the input pins B0, B1 of the first AOI22 cell C133, while routing the input pins B0', B1' of the second AOI22 cell C134 When routing is not easy, as shown in FIG. 14B , pin access points of the input pins B0' and B1' of the second AOI22 cell C134 may be increased through the third cut X3.

15 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 15 shows examples of steps S30 and S50 of FIG. 10 . As described above with reference to Fig. 10, the cells may be placed in step S30' of Fig. 15, and the pins of the cells may be routed at step S50'' of Fig. 15. As shown in Fig. 15, the cells may be routed at step S30 ' may include steps S32 and S34, and step S50" may include steps S52', S54' and S56'.

Referring to FIG. 15 , in step S32, a function cell may be disposed. The functional cell may refer to a cell used in the netlist D13 of FIG. 10 . A semiconductor design tool may place a single height cell in one of a series of rows and a multi-height cell in two or more consecutive rows.

In step S34, a filler cell may be disposed adjacent to the functional cell. As described above with reference to FIG. 6 and the like, a filler cell may be inserted between the functional cells to route the pins of the functional cell. As described above with reference to FIGS. 7A to 7C , a filler cell more advantageous for routing may be disposed among the deployable filler cells on both sides of the functional cell. An example of step S34 will be described later with reference to FIG. 16 .

In step S52', the sub-pattern may extend into the filler cell. For example, the semiconductor design tool may extend at least one fin of the functional cell into the interior of the filler cell, and the extended fin may pass through a boundary between the functional cell and the filler cell.

In step S54', a via may be disposed in one of the plurality of pin access points. Pins included in the cell may have at least one pin access point. In addition, the extended pin in step S52' may additionally have at least one pin access point in the extended portion. Accordingly, the via may be disposed in one of the plurality of pin access points including the extended portion. Then, in step S56', a higher-order pattern can be generated. For example, an upper pattern connected to the via disposed in step S54' may be generated.

16 is a flowchart illustrating a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure. Specifically, the flowchart of FIG. 16 shows an example of step S34 of FIG. 15 . As described above with reference to FIG. 15 , a filler cell may be disposed adjacent to the functional cell in step S34 ′ of FIG. 16 . As shown in FIG. 16 , step S34' may include steps S34_2 and S34_4. In some embodiments, step S34' may include only one of steps S34_2 and S34_4.

Referring to FIG. 16 , in step S34_2, a filler cell providing more pin access points may be disposed. For example, as described above with reference to FIGS. 7A-7C , two pillar cells deployable on either side of a functional cell may provide a different number of additional pin access points. The semiconductor design tool may determine which of the two pillar cells provides more pin access points, and may place the determined pillar cell adjacent to the functional cell. In some embodiments, the semiconductor design tool may determine and place a pillar cell that generates an additional pin access point therein upon placement.

In step S34_4, a filler cell may be arranged based on the attribute of the functional cell. For example, as described above with reference to FIGS. 7A-7C , a filler cell that provides more pin access points is a function cell (or gate electrodes included in a function cell) and a relative between the tracks of the upper wiring layer. It may be determined according to the location, and thus a condition for a filler cell that provides more pin access points may be predefined. For example, as shown in FIGS. 7A and 7B , a filler cell disposed adjacent to a boundary that does not intersect a track of an upper wiring layer among both boundaries of the functional cell may be advantageous, and the semiconductor design tool may be pre-defined Filler cells can be arranged with reference to the condition.

In some embodiments, such as AOI22 cell C62 of FIG. 7A , the functional cell may include an upper pattern. Accordingly, the relative position between the tracks of the functional cell and the upper wiring layer can be fixed, and the position of the more advantageous filler cell can also be fixed. In some embodiments, the cell library D12 of FIG. 10 may include information indicating the location of the filler cell in a property (eg, name, etc.) of the cell, and the semiconductor design tool may refer to this to place the filler cell. can Also, in some embodiments, the file referenced by the semiconductor design tool when arranging cells may include information on grouping functional cells according to the positions of the filler cells.

17 is a block diagram illustrating a system on chip (SoC) 160 according to an exemplary embodiment of the present disclosure. The system-on-chip 160 is a semiconductor device and may include an integrated circuit according to an exemplary embodiment of the present disclosure. The system-on-chip 160 implements complex functional blocks such as intellectual property (IP) that perform various functions in one chip, and is a method of designing an integrated circuit according to exemplary embodiments of the present disclosure. Thus, the system-on-chip 160 can be designed, and thus the system-on-chip 160 providing high performance and efficiency due to reduced routing congestion can be achieved. Referring to FIG. 17 , the system-on-chip 160 includes a modem 162 , a display controller 163 , a memory 164 , an external memory controller 165 , a central processing unit (CPU) 166 , and a transaction unit. 167 , a PMIC 168 , and a graphic processing unit (GPU) 169 , and respective functional blocks of the system-on-chip 160 may communicate with each other through a system bus 161 .

The CPU 166 capable of controlling the operation of the system-on-chip 160 in the uppermost layer may control the operation of other functional blocks 162 to 169 . The modem 162 may demodulate a signal received from the outside of the system-on-chip 160 or modulate a signal generated inside the system-on-chip 160 and transmit it to the outside. . The external memory controller 165 may control an operation of transmitting and receiving data from an external memory device connected to the system-on-chip 160 . For example, programs and/or data stored in the external memory device may be provided to the CPU 166 or the GPU 169 under the control of the external memory controller 165 . The GPU 169 may execute program instructions related to graphics processing. The GPU 169 may receive graphic data through the external memory controller 165 , and transfer graphic data processed by the GPU 169 to the outside of the system-on-chip 160 through the external memory controller 165 . can also be transmitted. The transaction unit 167 may monitor data transactions of each functional block, and the PMIC 168 may control power supplied to each functional block according to the control of the transaction unit 167 . The display controller 163 may transmit data generated inside the system-on-chip 160 to the display by controlling a display (or a display device) external to the system-on-chip 160 . The memory 164 may include a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, and the like, a dynamic random access memory (DRAM), a static random access memory (SRAM), and the like. It may include the same volatile memory.

18 is a block diagram illustrating a computing system 170 including a memory for storing a program according to an exemplary embodiment of the present disclosure. At least some of the steps included in the method of designing an integrated circuit, for example, the method of FIG. 10 according to example embodiments of the present disclosure, may be performed in the computing system (or computer) 170 .

Computing system 170 may be a stationary computing system, such as a desktop computer, workstation, server, or the like, or a portable computing system, such as a laptop computer. 18 , the computing system 170 includes a processor 171 , input/output devices 172 , a network interface 173 , a random access memory (RAM) 174 , and a read only memory (ROM) 175 . ) and a storage device 176 . The processor 171 , the input/output devices 172 , the network interface 173 , the RAM 174 , the ROM 175 , and the storage device 176 may be coupled to the bus 177 and each other via the bus 177 . can communicate.

The processor 171 may be referred to as a processing unit, and may be any instruction set (eg, a micro-processor), an application processor (AP), a digital signal processor (DSP), or a graphic processing unit (GPU). at least one core capable of running IA-32 (Intel Architecture-32), 64-bit extended IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, processor 171 may access memory, ie, RAM 174 or ROM 175 , via bus 177 , and execute instructions stored in RAM 174 or ROM 175 .

The RAM 174 may store a program 174_1 or at least a portion thereof for a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure, and the program 174_1 causes the processor 171 to: At least some of the steps included in the method of designing, for example, the method of FIG. 10 may be performed. That is, the program 174_1 may include a plurality of instructions executable by the processor 171 , and the plurality of instructions included in the program 174_1 causes the processor 171 to, for example, be included in the flowchart of FIG. 10 . at least some of the steps may be performed.

The storage device 176 may not lose stored data even if the power supplied to the computing system 170 is cut off. For example, the storage device 176 may include a non-volatile memory device, and may include a storage medium such as a magnetic tape, an optical disk, or a magnetic disk. Also, the storage device 176 may be removable from the computing system 170 . The storage device 176 may store the program 174_1 according to an exemplary embodiment of the present disclosure, and the program 174_1 or the program 174_1 from the storage device 176 before the program 174_1 is executed by the processor 171 . At least a portion of it may be loaded into RAM 174 . Alternatively, the storage device 176 may store a file written in a programming language, and the program 174_1 generated from the file by a compiler or the like or at least a part thereof may be loaded into the RAM 174 . Also, as shown in FIG. 18 , the storage device 176 may store a database 176_1 , and the database 176_1 includes information necessary for designing an integrated circuit, such as the cell library D12 and/or the cell library D12 of FIG. 10 . It may include a design rule (D14).

The storage device 176 may store data to be processed by the processor 171 or data processed by the processor 171 . That is, the processor 171 may generate data by processing data stored in the storage device 176 according to the program 174_1 , and may store the generated data in the storage device 176 . For example, the storage device 176 may store the RTL data D11, the netlist D13, and/or the layout data D15 of FIG. 10 .

The input/output devices 172 may include an input device such as a keyboard and a pointing device, and may include an output device such as a display device and a printer. For example, the user may trigger the execution of the program 174_1 by the processor 171 through the input/output devices 172 , and read the RTL data D11 and/or the netlist D13 of FIG. 10 . It may be input or the layout data D15 of FIG. 10 may be checked.

Network interface 173 may provide access to a network external to computing system 170 . For example, a network may include a number of computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other type of links.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical idea of the present disclosure and not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom.

Claims (20)

a first cell including a first sub-pattern extending in a first direction along a first track in the first wiring layer; and
a second cell including a second sub-pattern extending from the first wiring layer in the first direction along the first track and spaced apart from the first sub-pattern by at least a minimum separation distance of the first wiring layer;
The first sub-pattern corresponds to a pin of the first cell,
The second sub-pattern is spaced apart from a boundary between the first cell and the second cell further than the first sub-pattern. The method according to claim 1,
The second sub-pattern corresponds to a pin of the second cell. The method according to claim 1,
The first sub-pattern is in contact with the boundary. The method according to claim 1,
The first cell further includes a third sub-pattern extending in the first direction along a second track in the first wiring layer;
The second cell further includes a fourth sub-pattern extending from the first wiring layer in the first direction along the second track and spaced apart from the third sub-pattern by at least the minimum separation distance,
The fourth lower pattern corresponds to the fin of the second cell,
The third sub-pattern is spaced apart from the boundary further than the fourth sub-pattern. 5. The method according to claim 4,
and at least one of the first track and the second track is an outermost track among the tracks of the first wiring layer. The method according to claim 1,
The first cell further includes at least one gate electrode extending in a second direction perpendicular to the first direction at a first pitch,
the integrated circuit includes a plurality of upper patterns extending on the first cell in the second direction at a second pitch in a second wiring layer;
The second pitch is smaller than the first pitch. 7. The method of claim 6,
The plurality of upper patterns includes a first upper pattern aligned with a first gate electrode of the at least one gate electrode. 8. The method of claim 7,
The plurality of upper patterns includes a second upper pattern adjacent to the first gate electrode,
The integrated circuit further comprising a first via connecting the first lower pattern and the second upper pattern. 7. The method of claim 6,
The first cell further includes at least one contact extending in the second direction between the at least one gate electrode,
and the plurality of upper patterns includes a third upper pattern aligned with one of the at least one contact. 10. The method of claim 9,
The plurality of upper lower patterns include a fourth upper pattern adjacent to the third upper pattern and a fifth upper pattern adjacent to the fourth upper pattern,
The integrated circuit further comprising a second via connecting the first lower pattern and the fifth upper pattern. a first cell including a first sub-pattern and a second sub-pattern respectively extending in a first direction along the first track and the second track in the first wiring layer; and
a second cell including a third sub-pattern and a fourth sub-pattern extending in the first direction along the first track and the second track in the first wiring layer;
The first sub-pattern is spaced apart by at least a minimum separation distance between the third sub-pattern and the first wiring layer, and is spaced apart by a first distance or more from a boundary between the first cell and the second cell,
The second sub-pattern is spaced apart from the fourth sub-pattern by the minimum separation distance or more, and is spaced apart from the boundary by a second distance or more,
and the first distance and the second distance are different. 12. The method of claim 11,
The first distance is shorter than the second distance,
The first sub-pattern corresponds to a pin of the first cell,
The fourth sub-pattern corresponds to a pin of the second cell. 13. The method of claim 12,
The first sub-pattern and the fourth sub-pattern are in contact with the boundary. 13. The method of claim 12,
The second lower pattern corresponds to the pin of the first cell,
The third sub-pattern corresponds to a pin of the second cell. A method for designing an integrated circuit comprising:
obtaining input data defining a plurality of cells and connections between the plurality of cells;
arranging the plurality of cells based on the input data;
routing a plurality of pins of the disposed plurality of cells based on the input data; and
generating output data defining a layout of the integrated circuit;
Routing the pins comprises:
extending a first sub-pattern corresponding to the fin of the first cell and extending in a first direction in the first wiring layer;
disposing a via in one of a plurality of pin access points including a pin access point of the extended portion of the first sub-pattern; and
and generating a first upper pattern connected to the via and extending in a second direction perpendicular to the first direction in a second wiring layer. 16. The method of claim 15,
The step of extending the first sub-pattern,
merging the first sub-pattern with a second sub-pattern included in a second cell adjacent to the first cell and extending in the first direction along the same track as the first sub-pattern in the first wiring layer; and
and disposing a cut of the first wiring layer in the merged first sub-pattern and the second sub-pattern. 16. The method of claim 15,
The step of disposing the plurality of cells comprises:
disposing the first cell; and
disposing a filler cell adjacent the first cell;
The method of claim 1 , wherein extending the first sub-pattern comprises extending the first sub-pattern into the interior of the filler cell. 18. The method of claim 17,
The first cell includes at least one gate electrode extending in the second direction at a first pitch,
the plurality of upper patterns extend in the second direction from the second wiring layer at a second pitch smaller than the first pitch;
The disposing of the pillar cell may include disposing a pillar cell providing more pin access points in an extended portion of the first sub-pattern, among two pillar cells, each of which can be disposed on both sides of the first cell. A method comprising: 18. The method of claim 17,
The first cell includes a second upper pattern extending in the second direction from the second wiring layer,
The method of claim 1, wherein disposing the filler cell includes identifying a property of the first cell and placing the filler cell on one of both sides of the first cell based on the identified property. . 16. The method of claim 15,
generating output data defining a layout of the integrated circuit;
manufacturing a mask based on the output data; and
and fabricating the integrated circuit based on the mask.

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