KR20240073729A - Integrated circuit including standard cells and method of designing the same - Google Patents

Abstract

The integrated circuit includes first cells and second cells extending in a first horizontal direction and disposed in mutually adjacent first rows and second rows, respectively, and a first cell along a first boundary between the first row and the second row in the power line layer. 1 a first power line extending in the horizontal direction and configured to apply a first supply voltage, a first contact extending from the first cell to the second cell in a second horizontal direction intersecting the first horizontal direction, and a first contact in the vertical direction 1 It may include a first downward via extending from the lower surface of the contact to the upper surface of the first power line.

Description

Integrated circuit including standard cells and method of designing the same {INTEGRATED CIRCUIT INCLUDING STANDARD CELLS AND METHOD OF DESIGNING THE SAME}

The technical idea of the present disclosure relates to integrated circuits, and more specifically, to an integrated circuit including a standard cell and a method of designing the same.

An integrated circuit that processes digital signals may include standard cells, and each of the standard cells may have unique functions and structures. Due to advancements in semiconductor processes, the size of standard cells may decrease, and accordingly, routing to supply power to standard cells may not be easy.

The technical idea of the present disclosure provides an integrated circuit that provides a reduced area and an improved power delivery network and a method of designing the same.

An integrated circuit according to one aspect of the technical idea of the present disclosure includes first cells and second cells extending in a first horizontal direction and arranged respectively in first and second rows adjacent to each other, a first row and a second cell in a power line layer. A first power line extending in a first horizontal direction along a first border between the second rows and configured to be applied with a first supply voltage, extending from the first cell to the second cell in a second horizontal direction intersecting the first horizontal direction. It may include a first contact, and a first downward via extending from the lower surface of the first contact to the upper surface of the first power line in a vertical direction.

An integrated circuit according to one aspect of the technical idea of the present disclosure includes a first power line extending in a first horizontal direction from a power line layer and configured to apply a first supply voltage, each of which intersects the first horizontal direction. 2 a plurality of first contacts extending in a horizontal direction and connected to adjacent source/drain regions in a second horizontal direction, and each extending in a vertical direction from the lower surfaces of the plurality of first contacts to the upper surface of the first power line It may include a plurality of first downward vias, and the plurality of first contacts may be arranged at equal intervals in the first horizontal direction.

A method for manufacturing an integrated circuit according to an aspect of the technical idea of the present disclosure includes obtaining first input data defining an integrated circuit including a plurality of standard cells, extending in a first horizontal direction in a power line layer. arranging a plurality of power lines, each of which extends in a second horizontal direction intersecting the first horizontal direction and overlaps one of the plurality of power lines, arranging a plurality of virtual contacts, each of which extends in a second horizontal direction intersecting the first horizontal direction and overlaps one of the plurality of power lines, Based on the contacts, the step may include placing a plurality of standard cells, and generating output data defining a layout including the placed plurality of standard cells, wherein the step of placing the plurality of standard cells includes: , may include arranging the standard cell so that the source region of the transistor overlaps the virtual contact.

According to integrated circuits and methods according to example embodiments of the present disclosure, the area of the structure including the backside power delivery network may be reduced, and thus the integrated circuit may have a reduced area and/or a higher degree of integration.

Additionally, according to the integrated circuit and method according to the exemplary embodiment of the present disclosure, power supply to devices can be strengthened, and thus the performance and reliability of the integrated circuit can be increased.

The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the technical field to which the exemplary embodiments of the present disclosure belong from the following description. It can be clearly derived and understood by those who have it. That is, unintended effects resulting from implementing the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1A and 1B are diagrams showing layouts of integrated circuits according to example embodiments of the present disclosure.
2A to 2D are diagrams showing examples of devices according to example embodiments of the present disclosure.
Figure 3 is a plan view showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
4A and 4B are cross-sectional views showing examples of cross-sections of integrated circuits according to example embodiments of the present disclosure.
5A and 5B are diagrams showing layouts of integrated circuits according to example embodiments of the present disclosure.
6A and 6B are diagrams showing layouts of integrated circuits according to example embodiments of the present disclosure.
7A and 7B are cross-sectional views showing examples of cross-sections of integrated circuits according to example embodiments of the present disclosure.
8 is a flow chart illustrating a method for manufacturing an integrated circuit according to an example embodiment of the present disclosure.
9 is a flow chart illustrating a method for manufacturing an integrated circuit according to an example embodiment of the present disclosure.
Figure 10 is a flowchart illustrating a method for manufacturing an integrated circuit according to an example embodiment of the present disclosure.
11 is a flow chart illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 12 is a diagram showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 13 is a diagram showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 14 is a diagram showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
15 is a diagram illustrating examples of a flowchart and layout illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure.
Figure 16 is a block diagram showing a system-on-chip according to an exemplary embodiment of the present disclosure.
Figure 17 is a block diagram showing a computing system including a memory for storing a program according to an exemplary embodiment of the present disclosure.

1A and 1B are diagrams showing layouts of integrated circuits according to example embodiments of the present disclosure. 1A and 1B each show a plan view of the integrated circuit and a cross-sectional view of the integrated circuit taken along the line Y1-Y1'. Hereinafter, overlapping content in the description of FIGS. 1A and 1B will be omitted.

In this specification, the can be referred to. A plane consisting of the Orientally placed components may be referred to as being below other components. Additionally, the area of a component may refer to the size occupied by the component in a plane parallel to the horizontal plane, and the width of the component may refer to the length in a direction perpendicular to the direction in which the component extends. The surface exposed in the +Z direction may be referred to as the top surface, the surface exposed in the -Z direction may be referred to as the bottom surface, and the surface exposed in the ±X or ±Y direction may be referred to as the top surface. It can be referred to as a side. A pattern made of a conductive material, such as a pattern of a wiring layer, may be referred to as a conductive pattern, or may simply be referred to as a pattern. Additionally, a pattern extending in one direction may be referred to as a line.

In the drawings of this specification, only some layers may be shown for convenience of illustration, and a via connecting an upper pattern and a lower pattern may be displayed for understanding even though it is located below the upper pattern. Additionally, for convenience of illustration, the gate electrodes are shown as continuously extending in the Y-axis direction, but it is important to note that each of the gate electrodes may be divided into two or more gate electrodes, for example, by a gate cut.

The integrated circuit may include a power line that provides a positive or negative supply voltage to the device, such as a transistor. For example, as shown in FIG. 1A, the first power line PL11 has a positive effect on the PFETs formed in the first p-channel field effect transistor (PFET) region P1 and the second PFET region P2. It can provide a supply voltage and can extend in the X-axis direction. Additionally, the second power line PL12 may provide a negative supply voltage to NFETs formed in the first n-channel field effect transistor (NFET) region N1 and the second NFET region N2, and the X-axis can be extended in any direction. In this specification, the layer on which the power line is formed may be referred to as a power line layer. The power line may be composed of any conductive material and may be referred to as a backside power rail (BSPR) when used to supply power to a standard cell, as described below with reference to the drawings. there is. As shown in FIG. 1A, a backside interlayer dielectric (BILD) may be disposed between the first power line PL1 and the second power line PL2.

Referring to FIG. 1A, the integrated circuit 10a includes a first PFET region (P1), a second PFET region (P2), a first NFET region (N1), and a second NFET region (N2) extending in the X-axis direction. It may include gate electrodes extending in the Y-axis direction. Sources/drains may be formed on both sides of the gate electrode, and contacts may be formed on the source/drain. A channel may be formed between the source/drain under the gate electrode, and examples of the channel will be described later with reference to FIGS. 2A to 2D.

In some embodiments, the integrated circuit may include a power line extending underneath a transistor, and the transistor may be formed on top of the power line layer. For example, the integrated circuit may include a backside power rail (BSPR) as shown in FIGS. 1A and 1B. The first power line PL11 may extend in the X-axis direction under the first PFET area P1 and the second PFET area P2, and the second power line PL12 may extend in the It may extend in the X-axis direction under the second NFET area (N2). In some embodiments, a positive supply voltage may be applied to the first power line PL11 and a negative supply voltage may be applied to the second power line PL12.

Integrated circuit 10a may include vias connected to power lines and contacts. For example, as shown in FIG. 1A, the first via VD1 may extend from the lower surface of the first contact CA1 to the upper surface of the first power line PL11, and the second source/drain region ( It may be closer to the first source/drain area (SD1) than SD2). Accordingly, the positive supply voltage may be provided from the first power line PL11 to the first source/drain region SD1 through the first via VD1 and the first contact CA1. The first source/drain region SD1 may be the source of the PFET formed in the first PFET region P1, and the second source/drain region SD2 may be the drain of the PFET formed in the second PFET region P2. there is. The second via VD2 may extend from the lower surface of the fourth contact CA4 to the upper surface of the second power line PL12, and is located closer to the fourth source/drain region SD4 than the third source/drain region SD3. It may be closer to . Accordingly, the negative supply voltage may be provided from the second power line PL12 to the fourth source/drain region SD4 through the second via VD2 and the fourth contact CA4. The third source/drain region SD3 may be the drain of the NFET formed in the first NFET region N1, and the fourth source/drain region SD4 may be the source of the NFET formed in the second NFET region N2. there is. In this specification, vias that extend downward from the contact to connect to the power line, such as the first via VD1 and the second via VD2, may be referred to as downward vias. On the other hand, a via that extends upward from a contact to connect to the pattern of the wiring layer may be referred to as an upward via.

Transistor regions (or source/drain regions) may be spaced apart from each other by a certain distance or more for connection of downward vias and contacts. For example, as shown in FIG. 1A, the first PFET region (P1) and the second PFET region (P2) may be spaced apart from each other in the Y-axis direction by a first distance (D1a), and the first NFET region ( N1) and the second NFET area N2 may be spaced apart from each other in the Y-axis direction by a second distance D2a. The first contact CA1 may extend in the Y-axis direction for connection to the first via VD1, and the first distance D1a is required for insulation between the first contact CA1 and the second contact CA2. It can correspond to any length. Additionally, the fourth contact CA4 may extend in the Y-axis direction for connection to the second via VD2, and the second distance D2a may be insulated between the third contact CA3 and the fourth contact CA4. It can correspond to the required length. In some embodiments, the first distance D1a and the second distance D2a may be the same.

Referring to FIG. 1B, the integrated circuit 10b includes a third PFET region (P3), a fourth PFET region (P4), a third NFET region (N3), and a fourth NFET region (N4) extending in the X-axis direction. It may include gate electrodes extending in the Y-axis direction. The third power line PL13 may extend in the It may extend in the X-axis direction under the fourth NFET area N4. In some embodiments, a positive supply voltage may be applied to the third power line PL13 and a negative supply voltage may be applied to the fourth power line PL14.

In some embodiments, the transistors may be arranged so that their sources are adjacent to each other in the Y-axis direction, and a contact connecting the sources may extend in the Y-axis direction. For example, the fifth source/drain region SD5 may be a source of a PFET formed in the third PFET region P3, and the sixth source/drain region SD6 may be a PFET formed in the fourth PFET region P4. It may be a source of . The fifth contact CA5 may extend in the Y-axis direction and be connected to the fifth source/drain area SD5 and the sixth source/drain area SD6. The third via VD3 may extend from the bottom of the fifth contact CA5 to the top of the third power line PL13. Accordingly, the positive supply voltage is supplied from the third power line PL13 through the third via VD3 and the fifth contact CA5 to the fifth source/drain region SD5 and the sixth source/drain region SD6. can be provided.

In the integrated circuit 10a of FIG. 1A, the first source/drain region SD1 and the second source/drain region SD2 have a first contact CA1 and a second contact CA2 connected to the first via VD1. While they may be relatively far apart from each other for insulation, the fifth source/drain region SD5 and sixth source/drain region SD6 in the integrated circuit 10b of FIG. 1B may be relatively close to each other. there is. Accordingly, the first distance D1b in FIG. 1B may be smaller than the first distance D1a in FIG. 1 (D1b < D1a), and the second distance D2b in FIG. 1B may also be smaller than the first distance D1a in FIG. 1. ) can be smaller than (D2b < D2a). As a result, the integrated circuit 10b of FIG. 1B may have a smaller area than the integrated circuit 10a of FIG. 1A. In some embodiments, the third via VD3 is connected to the fifth source/drain region SD5 (or third PFET region P3) and the sixth source/drain region SD6 (or 54th PFET region P4). )) can be placed in the exact center between. For example, the distance between the third via VD3 and the fifth source/drain region SD5 may be the same as the distance between the third via VD3 and the sixth source/drain region SD6.

2A to 2D are diagrams showing examples of devices according to example embodiments of the present disclosure. For example, Figure 2a shows a FinFET (20a), Figure 2b shows a gate-all-around field effect transistor (GAAFET) 20b, and Figure 2c shows a multi-bridge channel field effect transistor (MBCFET) 20c. 2d shows a vertical field effect transistor (VFET) 20d. For ease of illustration, FIGS. 2A to 2C show one of the two source/drain regions removed, and FIG. 2D shows a view parallel to the plane consisting of the Y and Z axes and the channel of the VFET 20d ( Shows a cross section of the VFET (20d) cut through a plane passing through CH).

Referring to FIG. 2A, the FinFET 20a is formed by a fin-shaped active pattern extending in the X-axis direction between shallow trench isolations (STIs) and a gate electrode (G) extending in the Y-axis direction. It can be. Source/drain regions (S/D) may be formed on both sides of the gate electrode (G), and accordingly, the source and drain may be spaced apart from each other in the X-axis direction. An insulating film may be formed between the channel (CH) and the gate electrode (G). In some embodiments, FinFET 20a may be formed by a plurality of active patterns and a gate electrode G that are spaced apart from each other in the Y-axis direction.

Referring to FIG. 2b, the GAAFET (20b) is formed by active patterns, that is, nanowires, extending in the X-axis direction and spaced apart from each other in the Z-axis direction, and a gate electrode (G) extending in the Y-axis direction. can be formed. Source/drain regions (S/D) may be formed on both sides of the gate electrode (G), and accordingly, the source and drain may be spaced apart from each other in the X-axis direction. An insulating film may be formed between the channel (CH) and the gate electrode (G). Note that the number of nanowires included in GAAFET 20b is not limited to that shown in FIG. 2b.

Referring to FIG. 2C, the MBCFET 20c is formed by active patterns, that is, nanosheets, extending in the X-axis direction and spaced apart from each other in the Z-axis direction, and a gate electrode (G) extending in the Y-axis direction. can be formed. Source/drain regions (S/D) may be formed on both sides of the gate electrode (G), and accordingly, the source and drain may be spaced apart from each other in the Y-axis direction. An insulating film may be formed between the channel (CH) and the gate electrode (G). Note that the number of nanosheets included in the MBCFET 20c is not limited to that shown in FIG. 2c.

Referring to FIG. 2D, the VFET 20d has a top source/drain (T_S/D) and a bottom source/drain (B_S/) spaced apart from each other in the Z-axis direction with a channel (CH) in between. D) may be included. The VFET (20d) may include a gate electrode (G) surrounding the circumference of the channel (CH) between the upper source/drain (T_S/D) and the lower source/drain (B_S/D). An insulating film may be formed between the channel (CH) and the gate electrode (G).

Hereinafter, the integrated circuit including the FinFET 20a or the MBCFET 20c will be mainly described, but it is noted that the elements included in the integrated circuit are not limited to the examples of FIGS. 2A to 2D. For example, the integrated circuit includes a ForkFET in which the nanosheets for the P-type transistor and the nanosheets for the N-type transistor have a structure in which the N-type transistor and the P-type transistor are closer together by being separated by a dielectric wall. can do. Additionally, the integrated circuit may include bipolar junction transistors as well as FETs such as complementary FETs (CFETs), negative CFETs (NCFETs), and carbon nanotube (CNTs) FETs.

Figure 3 is a plan view showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 3, the integrated circuit 30 may include a first cell C31, a second cell C32, and first to third power lines PL31 to PL33.

An integrated circuit may include a plurality of standard cells. A standard cell is a unit of layout included in an integrated circuit and may simply be referred to as a cell. Cells may contain transistors and may be designed to perform predefined functions. For example, as shown in FIG. 3, the first cell C31 may be placed in the first row R1 extending in the X-axis direction, and the second cell C32 may extend in the X-axis direction. It may be placed in the second row (R2) adjacent to the first row (R1). The height (i.e., the length in the Y-axis direction) of the first cell C31 may be the same as the first height H1 of the first row R1, and the height of the second cell C32 may be the same as the first height H1 of the first row R1. ) may be the same as the second height (H2). The first height H1 and the second height H2 may be the same or different. Standard cells arranged in one row, such as the first cell C31 and the second cell C32, may be referred to as a single height cell, and the second cell C122 of FIG. 12, which will be described later, As such, cells arranged consecutively in two or more rows may be referred to as multi-height cells.

The gate electrodes may extend parallel to each other in the Y-axis direction at a constant pitch. For example, as shown in FIG. 3, the pitch of the gate electrodes may be referred to as contact poly pitch (CPP). Accordingly, contacts disposed between the gate electrodes may also extend in the Y-axis direction through CPP.

Power lines may extend in the X-axis direction along boundaries of rows (or overlapping boundaries of rows) in the power line layer. For example, as shown in FIG. 3, a positive supply voltage (VDD) may be applied to the first power line (PL31), and the first power line (PL31) borders the first row (R1). It may extend in the X-axis direction. A negative supply voltage (VSS) may be applied to the second power line (PL32), and the second power line (PL32) extends in the X-axis direction along the boundary between the first row (R1) and the second row (R2). It may be extended. The positive supply voltage VDD may be applied to the third power line PL33, and the third power line PL33 may extend in the X-axis direction along the boundary of the second row R2.

As described above with reference to FIGS. 1A and 1B , sources of transistors may be adjacent to each other in the Y-axis direction, and the sources may be commonly connected to a contact extending in the Y-axis direction. For example, as shown in FIG. 3, the first contact CA31 may extend from the first cell C1 to the second cell C32 in the Y-axis direction and is included in the first cell C31. It may be connected to the source of the NFET (eg, SD31 in FIG. 4A) and the source of the NFET included in the second cell C32 (eg, SD32 in Figure 4A). A downward via (eg, VD31 in FIG. 4A) may be disposed under the first contact CA31, and the downward via may be connected to the second power line PL32. In some embodiments, the downward via may be aligned at the boundary between the first row R1 and the second row R2. For example, the center of the downward via may overlap the boundary between the first row R1 and the second row R2 in the Z-axis direction. In some embodiments, an upward via may be disposed on the first contact CA31, and the upward via may be connected to a pattern extending in the X-axis direction in the wiring layer (eg, M31 in FIG. 4A). An example of a cross-section of the integrated circuit 30 along the line Y2-Y2' will be described later with reference to FIG. 4A.

Contacts respectively connected to source/drain regions corresponding to different nodes may be spaced apart from each other in the Y-axis direction. For example, the second contact CA32 may be connected to the drain of the NFET included in the first cell C31 (e.g., SD33 in FIG. 4B), and the third contact CA33 may be connected to the second cell C32. It may be connected to the source of the included NFET (e.g., SD34 in FIG. 4B). As shown in FIG. 3, the second contact CA32 and the third contact CA33 may be spaced apart from each other in the Y-axis direction. An upward via may be disposed on the third contact CA33, and the upward via may be connected to a pattern extending in the X-axis direction in the wiring layer (eg, M31 in FIG. 4B). A cross section of the integrated circuit 30 along the line Y3-Y3' will be described later with reference to FIG. 4B.

As shown in FIG. 3, when the first cell C31 and the second cell C32 are arranged so that the sources are adjacent to each other in the Y-axis direction, the first height H1 and the first cell C31 2 The second height H2 of the cell C2 may be reduced, and the integrated circuit 30 may have a reduced area and/or a higher degree of integration.

4A and 4B are cross-sectional views showing examples of cross-sections of integrated circuits according to example embodiments of the present disclosure. For example, the cross-sectional view of FIG. 4A shows an example of a cross-section of the integrated circuit 30 along the line Y2-Y2' of FIG. 3, and the cross-sectional view of FIG. 4B shows an example of the integrated circuit (30) along the line Y3-Y3' of FIG. 3. 30) shows an example of a cross section. Hereinafter, FIGS. 4A and 4B will be explained with reference to FIG. 3 .

Referring to FIG. 4A , a negative supply voltage VSS may be applied to the second power line PL32, and the second power line PL32 may extend in the X-axis direction from the power line layer. The first contact CA31 may extend in the Y-axis direction and is connected to the first source/drain area SD31 of the first cell C31 and the second source/drain area SD32 of the second cell C32. can be connected As described above with reference to FIG. 3, the first source/drain region SD31 may correspond to the source of the NFET included in the first cell C31, and the second source/drain region SD32 may correspond to the source of the NFET included in the first cell C31. It can correspond to the source of the NFET included in (C32). The first downward via VD31 may extend vertically from the bottom of the first contact CA31 to the top of the second power line PL32. Accordingly, the negative supply voltage (VSS) is transmitted from the second power line (PL32) to the first source/drain region (SD31) and the second source/drain through the first downward via (VD31) and the first contact (CA31). It can be provided as an area (SD32). In some embodiments, the first downward via VD31 may be disposed at the exact center between the first source/drain region SD31 and the second source/drain region SD32. For example, the distance between the first downward via VD31 and the first source/drain region SD31 may be equal to the distance between the first downward via VD31 and the second source/drain region SD32.

The pattern M31 may extend in the X-axis direction in the first wiring layer M1. In some embodiments, the first wiring layer M1 may refer to the wiring layer (eg, metal layer) closest to the device in the +Z-axis direction. The first upward via (VU31) may extend from the top surface of the first contact (CA31) to the bottom surface of the pattern (M31) of the first wiring layer (M1). Accordingly, a negative supply voltage (VSS) may be provided to the pattern (M31) of the first wiring layer (M1). In some embodiments, the first upward via (VU31) may be aligned with the first downward via (VD31) in the Z-axis direction.

Referring to FIG. 4B, a negative supply voltage VSS may be applied to the second power line PL32, and the second power line PL32 may extend in the X-axis direction from the power line layer. The second contact CA32 may be connected to the third source/drain area SD33 in the first cell C31, and the third contact CA33 may be connected to the fourth source/drain area SD34 in the second cell C32. ) can be connected to. As described above with reference to FIG. 3, the third source/drain region SD33 may correspond to the drain of the NFET included in the first cell C31, and the fourth source/drain region SD34 may correspond to the drain of the NFET included in the first cell C31. It can correspond to the source of the NFET included in (C32). In order to supply a negative supply voltage to the fourth source/drain region SD23, the second upward via VU32 extends from the top surface of the third contact CA33 to the bottom surface of the pattern M31 of the first wiring layer M1. It may be extended. As described above with reference to FIG. 4A, a negative supply voltage (VSS) may be applied to the pattern (M31) of the first wiring layer (M1), and accordingly, the negative supply voltage (VSS) may be applied to the pattern (M31) of the first wiring layer (M1). ) may be provided from the pattern M31 to the fourth source/drain region SD34 through the second upward via (VU32) and the third contact (CA33). In some embodiments, the third contact CA33 may extend in the Y-axis direction for connection to the second upward via VU32 and may have a length in the Y-axis direction that is longer than the second contact CA32. .

5A and 5B are diagrams showing layouts of integrated circuits according to example embodiments of the present disclosure. For example, FIGS. 5A and 5B show first to fourth power lines (PL51 to PL54) and first to fourth power lines extending in the X-axis direction along the boundaries of the first to third rows (R1 to R3). It shows contacts connected through lines (PL51 to PL54) and downward vias. In some embodiments, downward vias connected to the power lines may be arranged regularly, and contacts connected to the downward vias may also be placed regularly. Due to the regularly placed downward vias and contacts, a low IR-drop, i.e. an improved power delivery network, can be achieved, whereby the surge voltage of the device contained in standard cells can be provided stably to the public.

Referring to FIG. 5A, downward vias connected to the first power line (PL51) and the third power line (PL53) to which the positive supply voltage (VDD) is applied have a first pitch (PT51) in the X-axis direction. may be arranged, and accordingly, the contacts may also extend in the Y-axis direction at the first pitch PT51. Additionally, downward vias connected to the second power line PL52 and the fourth power line PL54 to which the negative supply voltage VSS is applied may be arranged to have a second pitch PT52, and thus the contact They may also extend in the Y-axis direction with a second pitch (PT52). In some embodiments, the first pitch PT51 and the second pitch PT52 may be the same.

As shown in FIG. 5A, the contacts connected to the first power line PL51 to which the positive supply voltage (VDD) is applied and the downward vias are connected to the third power line (PL51) to which the positive supply voltage (VDD) is applied. The contacts connected through PL53) and the downward vias may be aligned in the Y-axis direction, while the second power line (PL52) or fourth power line (PL54) to which the negative supply voltage (VSS) is applied and the downward vias Contacts connected through it may not be aligned in the Y-axis direction. Additionally, contacts connected to the second power line PL52 through downward vias may be aligned in the Y-axis direction with contacts connected to the fourth power line PL54 through downward vias.

Referring to FIG. 5B, downward vias connected to the first to fourth power lines PL51 to PL54 may be arranged to have a third pitch PT53 in the X-axis direction, and accordingly, the contacts may also have a third pitch. (PT53) and can be extended in the Y-axis direction. Downward vias and contacts may be aligned in the Y-axis direction. Hereinafter, as described above with reference to FIG. 5A, the structure in which the contacts to which the positive supply voltage (VDD) is applied and the contacts to which the negative supply voltage (VSS) is applied are not aligned in the Y-axis direction will be mainly referred to. However, it is noted that the exemplary embodiments of the present disclosure are not limited thereto.

6A and 6B are diagrams showing layouts of integrated circuits according to example embodiments of the present disclosure. For example, FIGS. 6A and 6B show first to fourth power lines (PL61 to PL64) and first to fourth power lines extending in the X-axis direction along the boundaries of the first to third rows (R1 to R3). It represents contacts connected through lines (PL61 to PL64) and downward vias. As described above with reference to FIGS. 5A and 5B, downward vias connected to power lines may be arranged regularly, and contacts connected to the downward vias may also be arranged regularly. Hereinafter, overlapping content in the description of FIGS. 6A and 6B will be omitted.

Referring to FIG. 6A, similar to the example of FIG. 5A, the contacts connected to the first power line PL51 to which the positive supply voltage (VDD) is applied and the downward vias are to which the positive supply voltage (VDD) is applied. It can be aligned in the Y-axis direction with the third power line (PL63) and contacts connected through downward vias, while the second or fourth power line (PL62) to which a negative supply voltage (VSS) is applied. The contacts connected through (PL64) and downward vias may not be aligned in the Y-axis direction. Additionally, contacts connected to the second power line PL562 through downward vias may be aligned in the Y-axis direction with contacts connected to the fourth power line PL64 through downward vias.

As shown in FIG. 6A, contacts connected to the first power line PL61 or the third power line PL63 through downward vias may include contact pairs each composed of two mutually adjacent contacts, Contact pairs may be spaced apart from each other at a first pitch (PT61) in the X-axis direction. Additionally, contacts connected to the second power line PL62 or the fourth power line PL64 through downward vias may include contact pairs each composed of two mutually adjacent contacts, and the contact pairs may be oriented in the X-axis direction. They can be spaced apart from each other by the second pitch (PT62). In some embodiments, the first pitch PT61 and the second pitch PT62 may be the same. The integrated circuit of FIG. 6A may provide reduced IR-drop than the integrated circuit of FIG. 5A.

Referring to FIG. 6B, contacts may be added locally to regularly placed contacts. For example, in the same layout as in FIG. 5A, a region R60 in which a large amount of current is consumed may be identified, and a first contact CA61 and a second contact CA62 may be added to the region R60. Accordingly, the contact pairs in FIG. 6A may be placed globally, while the contact pairs in FIG. 6B may be placed locally.

7A and 7B are cross-sectional views showing examples of cross-sections of integrated circuits according to example embodiments of the present disclosure. For example, the cross-sectional views of FIGS. 7A and 7B represent examples of cross-sections of a structure including a contact pair comprised of mutually adjacent contacts, as described above with reference to FIGS. 6A and 6B. As discussed above with reference to FIGS. 6A and 6B, lower IR-drop can be provided by contact pairs.

Referring to FIG. 7A, the first contact CA71 and the second contact CA72 may be adjacent to each other in the X-axis direction and may form one contact pair. The first downward via VD71 may have an upper surface connected to the first contact CA71 as well as the second contact CA72 and a lower surface connected to the first power line PL71. Like the first downward via VD71, a via having a shape extending in the horizontal direction (eg, X-axis direction) may be referred to as a bar-type via. As a bar-type via, the first downward via (VD71) can provide lower IR-drop. The first pattern M71 of the first wiring layer M1 may extend in the X-axis direction on the first contact CA71 and the second contact CA72. The first upward via (VU71) may be connected to the first contact (CA71) and the first pattern (M71), and the second upward via (VU72) may be connected to the second contact (CA72) and the first pattern (M71). there is.

Referring to FIG. 7B, the third contact CA73 and the fourth contact CA74 may be adjacent to each other in the X-axis direction and may form one contact pair. The second downward via VD72 may have a top surface connected to the fourth contact CA74 as well as the third contact CA73, and a bottom surface connected to the second power line PL72. The second downward via (VD72) as a bar-type via may provide lower IR-drop. The second pattern M72 of the first wiring layer M1 may extend in the X-axis direction on the third contact CA73 and the fourth contact CA74. The third upward via (VU73) may have a lower surface connected to the fourth contact (CA74) as well as the third contact (CA73), and may have an upper surface connected to the second pattern (M72). The third upward via (VU73) as a bar-type via can provide lower IR-drop.

8 is a flow chart illustrating a method for manufacturing an integrated circuit (IC) according to an example embodiment of the present disclosure. For example, the flowchart of Figure 8 shows an example of a method for manufacturing an integrated circuit (IC) containing standard cells. As shown in FIG. 8, a method for manufacturing an integrated circuit (IC) may include a plurality of steps S10, S30, S50, S70, and S90.

The cell library (or standard cell library) D12 may include information about standard cells, such as information about functions, characteristics, layout, etc. In some embodiments, the cell library D12 may define a plurality of standard cells, each corresponding to different layouts and corresponding to the same function. In some embodiments, cell library D12 may define standard cells of various heights.

Design rules (D14) may include requirements that the layout of an integrated circuit (IC) must comply with. For example, the design rule D14 may include requirements for the distance (space) between patterns in the same layer, the minimum width of the pattern, the routing direction of the wiring layer, etc. In some embodiments, design rule D14 may define a minimum separation distance within the same track of the wiring layer.

In step S10, a logical synthesis operation may be performed to generate netlist data (D13) from RTL data (D11). For example, a semiconductor design tool (e.g., a logic synthesis tool) refers to the cell library D12 from RTL data D11 created as a Hardware Description Language (HDL) such as VHDL (VHSIC Hardware Description Language) or Verilog. Logical synthesis can be performed and netlist data D13 including a bitstream or netlist can be generated. Netlist data D13 may correspond to input of place and routing, which will be described later.

In step S30, cells may be deployed. For example, a semiconductor design tool (eg, P&R tool) may place standard cells used in the netlist data D13 with reference to the cell library D12. In some embodiments, the semiconductor design tool may place standard cells in a row extending in the X-axis direction, and the placed standard cells may be electrically connected to a power line extending in the X-axis direction under the transistor. An example of step S30 will be described with reference to FIG. 9 .

In step S50, pins of cells may be routed. For example, a semiconductor design tool can generate interconnections that electrically connect the output pins and input pins of placed standard cells, and layout data (D15) defining the placed standard cells and the created interconnections. ) can be created. The interconnections may include a pattern of vias and/or interconnection layers of vias. The layout data D15 may have a format such as GDSII, for example, and may include geometric information of cells and interconnections. The semiconductor design tool can refer to the design rule (D14) while routing the pins of the cells. Layout data D15 may correspond to the output of placement and routing. Step S50 alone, or steps S30 and S50 collectively, may be referred to as a method for designing an integrated circuit. In this specification, layout data D15 may be referred to as output data.

In step S70, the operation of fabricating a mask may be performed. For example, in photolithography, optical proximity correction (OPC) to correct distortions such as refraction caused by the characteristics of light may be applied to the layout data D15. Patterns on a mask may be defined to form patterns arranged in a plurality of layers based on OPC applied data, and at least one mask (or photomask) may be manufactured to form patterns in each of the plurality of layers. You can. In some embodiments, the layout of the integrated circuit (IC) may be limitedly modified in step S70, and the limited modification of the integrated circuit (IC) in step S70 may be performed after optimizing the structure of the integrated circuit (IC). As a treatment, it may be referred to as design polishing.

In step S90, an operation of manufacturing an integrated circuit (IC) may be performed. For example, an integrated circuit (IC) may be manufactured by patterning a plurality of layers using at least one mask fabricated in step S70. Front-end-of-line (FEOL) includes, for example, planarizing and cleaning the wafer, forming a trench, forming a well, and forming a gate electrode. It may include forming a source and a drain. By FEOL, individual elements such as transistors, capacitors, resistors, etc. can be formed on the substrate. Additionally, back-end-of-line (BEOL) may include, for example, siliciding the gate, source, and drain regions, adding a dielectric, planarizing, forming holes, and adding a metal layer. , forming a via, forming a passivation layer, etc. By BEOL, individual elements such as transistors, capacitors, resistors, etc. can be interconnected. In some embodiments, middle-of-line (MOL) may be performed between FEOL and BEOL and contacts may be formed on the individual devices. The integrated circuit (IC) can then be packaged in a semiconductor package and used as a component in a variety of applications.

9 is a flow chart illustrating a method for manufacturing an integrated circuit according to an example embodiment of the present disclosure. For example, the flow chart in FIG. 9 shows an example of step S30 in FIG. 8. As described above with reference to FIG. 8, cells may be deployed in step S30' of FIG. 9. As shown in FIG. 9, step S30' may include a plurality of steps (S31 to S36).

Referring to FIG. 9, netlist data can be obtained in step S31. For example, as described above with reference to FIG. 8, netlist data may be generated as a result of logical composition. Netlist data can define standard cells included in an integrated circuit and can define connection relationships between standard cells. In this specification, netlist data may be referred to as input data.

In step S32, power lines may be placed. As described above with reference to the drawings, power lines may extend in the It can be. In some embodiments, power lines may extend along the boundaries of rows in which standard cells are aligned.

In step S33, virtual contacts may be placed. Each of the virtual contacts may extend in the Y-axis direction and overlap one of the power lines arranged in step S32 in the Z-axis direction. For example, virtual contacts may be arranged in advance in the same way as the contacts in FIG. 5A. Virtual contacts can indicate points where downward vias will be placed and can be used to place standard cells, as described below. An example of step S33 will be described below with reference to FIG. 10.

In step S34, standard cells may be placed. For example, standard cells may be placed based on the virtual contacts placed in step S33. Standard cells can be placed such that the transistor's source overlaps the virtual contact. Accordingly, standard cells of reduced area (or height) may be placed, and the integrated circuit may have reduced area and/or high integration. An example of step S34 will be described below with reference to FIG. 11.

In step S35, downward vias may be placed. For example, downward vias may be placed to overlap the virtual contacts placed in step S33, and each of the downward vias may be connected to one of the power lines placed in step S32. In some embodiments, downward vias may be placed to align with the boundaries of rows.

In step S36, virtual contacts may be replaced with contacts. By means of replaced contacts, the sources of different standard cells can be electrically connected. For example, the contact may extend from the first standard cell to the second standard cell, and may be connected to the source of the transistor included in the first standard cell and the source of the transistor included in the second standard cell. Additionally, the replaced contact may be connected to the downward via placed in step S35, thereby electrically connecting the sources to the power line.

Figure 10 is a flow chart illustrating a method for manufacturing an integrated circuit according to an example embodiment of the present disclosure. For example, the flow chart in Figure 10 shows an example of step S33 in Figure 9. As described above with reference to FIG. 9, virtual contacts may be placed in step S33' of FIG. 10. Virtual contacts can be replaced with contacts after standard cells are deployed. As shown in FIG. 10, step S33' may include a plurality of steps (S33_1 to S33_3). Below, Figure 10 will be described with reference to Figures 5A and 5B, and the contacts in Figures 5A and 5B are considered to be virtual contacts.

Referring to FIG. 10 , first virtual contacts may be arranged to overlap the first power line PL51 in step S33_1. For example, the first virtual contacts may be arranged at regular intervals to overlap the first power line PL51 configured to apply the positive supply voltage VDD. The spacing (or pitch) of the first virtual contacts may be predefined, may be defined by the design rule D14 of FIG. 8, or may be defined by additional input data defining the integrated circuit.

In step S33_2, second virtual contacts may be arranged to overlap the second power line PL52. For example, the second virtual contacts may be arranged at regular intervals to overlap the second power line PL52 configured to apply the negative supply voltage VSS. In some embodiments, as described above with reference to FIG. 5A , the second virtual contacts may not be aligned in the Y-axis direction with the first virtual contacts placed in step S33_1. In some embodiments, as described above with reference to FIG. 5B, the second virtual contacts may be aligned in the Y-axis direction with the first virtual contacts placed in step S33_1.

In step S33_3, third virtual contacts may be placed to overlap the third power line. For example, the third virtual contacts may be arranged at regular intervals to overlap the third power line PL53 configured to apply the positive supply voltage VDD. In some embodiments, as described above with reference to FIGS. 5A and 5B, the third virtual contacts may be aligned in the Y-axis direction with the first virtual contacts placed in step S33_1.

11 is a flow chart illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure. For example, the flow chart in Figure 11 shows an example of step S34 in Figure 9. As described above with reference to FIG. 9, standard cells may be placed in step S34' of FIG. 11. As shown in FIG. 11, step S34' may include step S34_1 and step S34_2.

Referring to FIG. 11, a second standard cell providing the same function as the first standard cell may be identified in step S34_1. In the process of sequentially placing standard cells defined in netlist data, when it is desired to place the next first standard cell adjacent to an already placed standard cell, the source of the transistor included in the first standard cell overlaps the virtual contact. It may not work. In some embodiments, the cell library D12 may define a plurality of standard cells that provide the same function but each have different layouts. For example, the cell library D12 may define a plurality of standard cells that provide the same function but have different locations of transistor sources. Accordingly, a second standard cell may be identified, which may provide the same function as the first standard cell and includes a source of a transistor that overlaps a virtual contact when placed adjacent to an already placed standard cell.

In step S34_2, a second standard cell may be deployed. For example, a second standard cell may be placed adjacent to an already placed standard cell, and the source of a transistor included in the second standard cell may overlap a virtual contact.

FIG. 12 is a diagram showing the layout of an integrated circuit 120 according to an exemplary embodiment of the present disclosure. For example, Figure 8 shows first to fourth power lines (PL81 to PL84) and first to fourth power lines (PL81) extending in the X-axis direction along the boundaries of the first to third rows (R1 to R3). to PL84) and contacts connected through downward vias. As shown in FIG. 12, the integrated circuit 120 may include a first cell C121 and a third cell C123 arranged in the second row R2, and in the third row R3. It may include a fourth cell C124 and a fifth cell C125, and may include a second cell C122 sequentially placed in the second row R2 and the third row R3. .

As described above with reference to FIG. 9 , when standard cells are arranged so that sources overlap a virtual contact, a space may occur between the standard cells. For example, a first area R121 in which standard cells are not placed may occur in the third row R3 between the fourth cell C1245 and the second cell C122. In addition, the second area (R122) in which the standard cells are not placed between the second cell (C122), the third cell (C123), and the fifth cell (C125) is located in the second row (R2) and the third row (R3). can occur continuously. As will be described later with reference to FIGS. 13 and 14, filler cells may be provided to strengthen the power delivery network, and step S34 of FIG. 8 is arranged such that the source/drain region overlaps the virtual contact. It may include placing filler cells between standard cells. Accordingly, pillar cells may be disposed in the first region R121 and the second region R122.

FIG. 13 is a diagram showing the layout of an integrated circuit 130 according to an exemplary embodiment of the present disclosure. As shown in FIG. 13, the integrated circuit 130 may include first to third cells C131 to C133 and first to third power lines PL131 to PL133. The first cell C131 may be placed in the first row R1 of the first height H1, and the second cell C132 and the third cell C133 may be placed in the second row R1 of the second height H2. It can be placed in (R2). The first to third power lines (PL91 to PL93) may extend in the X-axis direction and are configured to receive a positive supply voltage (VDD), a negative supply voltage (VSS), and a positive supply voltage (VDD), respectively. It can be.

The first cell C131 and the second cell C132 are functional cells and may be defined by netlist data. The third cell C133 is a pillar cell and may be defined by a cell library and may be placed adjacent to the first cell C131 and the second cell C132. The third cell C133 is a single height cell and may have a second height H2 and may overlap with the virtual contact. For example, as shown in FIG. 13, the first contact CA131 corresponding to the virtual contact may extend from the first cell C131 to the third cell C133. A downward via connected to the lower surface of the first contact C131 and the upper surface of the second power line 132 may be disposed. Additionally, an upward via connected to the top surface of the first contact C131 and the bottom surface of the pattern of the first wiring layer may be disposed. Accordingly, IR-drop may be reduced in the path where the transistor (i.e., NFET) included in the first cell C131 receives the negative supply voltage (VSS).

FIG. 14 is a diagram showing the layout of an integrated circuit 140 according to an exemplary embodiment of the present disclosure. As shown in FIG. 14 , the integrated circuit 140 may include a first cell C141 and first to third power lines PL141 to PL143. The first cell C141 is a multi-height cell and can be continuously arranged in the first row R1 and the second row R2, and has the height of the first row R1 and the height of the second row R2. It may have a third height (H3) that is the sum. The first to third power lines (PL91 to PL93) may extend in the X-axis direction and are configured to receive a positive supply voltage (VDD), a negative supply voltage (VSS), and a positive supply voltage (VDD), respectively. It can be.

The first cell C141 may be a pillar cell and may be placed between standard cells defined by a netlist. The first cell C141 may overlap the virtual contact. For example, as shown in FIG. 14, the first contact CA141 corresponding to the virtual contact may extend from the first cell C141. A downward via connected to the lower surface of the first contact C141 and the upper surface of the second power line 142 may be disposed. Additionally, an upward via connected to the top surface of the first contact C141 and the bottom surface of the pattern of the first wiring layer may be disposed. Accordingly, the connection between the second power line PL142 and the pattern of the first wiring layer can be further strengthened.

In some embodiments, a pillar cell that is a multi-height cell may be comprised of two pillar cells that are single height cells. For example, the first cell C141 in FIG. 14 may be composed of the third cell C133 in FIG. 13 and the third cell C133 is flipped about the X-axis. Accordingly, only single-height cells may be provided as filler cells, and a multi-height cell such as the first cell C141 of FIG. 14 may be provided by combining two or more filler cells.

15 is a diagram illustrating examples of a flowchart and layout illustrating a method for manufacturing an integrated circuit according to an exemplary embodiment of the present disclosure. For example, the flowchart of FIG. 15 shows a method of adding a virtual blockage layer to the layout of a standard cell to place a standard cell based on a virtual contact, and the first to fourth layouts 151 to 151 of FIG. 15 154) shows examples of layouts corresponding to data generated in the process of performing a method of adding a virtual prevention layer. As shown in FIG. 15, the method of adding a virtual prevention layer may include a plurality of steps (S110 to S140).

Referring to FIG. 15, the contact layer may be identified in step S10. For example, as indicated by a thick line in the first layout 151, a contact layer where contacts are formed may be identified. In step S120, a contact cut layer may be applied to the contact layer. In semiconductor processing, contacts may be formed parallel to the Y axis and then divided by contact cuts. The contact cut layer may include contact cuts, and the contact cut layer may be applied to the contact layer identified in step S110. For example, as indicated by a thick line in the second layout 152, each of the contacts in the first layout 151 may be divided into two contacts by a contact cut.

In step S130, contacts excluding source contacts may be extracted. For example, a contact may be connected to a via to provide a supply voltage to the source of a transistor and may have an extended length for connection to the via. Accordingly, as indicated by a thick line in the third layout 153, a contact connected to the source of the transistor, that is, a source contact, can be extracted.

In step S140, a virtual prevention layer may be created and added. For example, prevention patterns corresponding to the contacts extracted in step S130 may be created, and a virtual prevention layer including the prevention patterns may be created. Accordingly, a virtual prevention layer including prevention patterns may be created, as indicated by a thick line in the fourth layout 154. The standard cell can be placed so that the prevention pattern does not overlap the virtual contact, and thus the source of the transistor can overlap the virtual contact.

In some embodiments, different from the example of FIG. 15, a virtual layer including virtual patterns corresponding to source contacts may be created and added. In this case, the standard cell can be placed so that the virtual pattern overlaps the virtual contact.

Figure 16 is a block diagram illustrating a system on chip (SoC) 160 according to an example embodiment of the present disclosure. The system-on-chip 160 is a semiconductor device and may include an integrated circuit according to an example embodiment of the present disclosure. The system-on-chip 160 implements complex blocks such as IP (intellectual property) that perform various functions on a single chip, and is used in the method of designing an integrated circuit according to example embodiments of the present disclosure. Thus, the system-on-chip 160 may be designed, and thus the system-on-chip 160 may have a reduced area and/or a high degree of integration. Referring to FIG. 16, the system-on-chip 160 includes a modem 162, a display controller 163, a memory 164, an external memory controller 165, a central processing unit (CPU) 166, and a transaction unit. It may include a 167, a PMIC 168, and a graphic processing unit (GPU) 169, and each functional block of the system-on-chip 160 may communicate with each other through the system bus 161.

The CPU 166, which can control the operation of the system-on-chip 160 at the top layer, can control the operation of other functional blocks 162 to 169. The modem 162 can demodulate a signal received from outside the system-on-chip 160 or modulate a signal generated inside the system-on-chip 160 and transmit it to the outside. . The external memory controller 165 may control the operation of transmitting and receiving data from an external memory device connected to the system-on-chip 160. For example, programs and/or data stored in an external memory device may be provided to the CPU 166 or GPU 169 under the control of the external memory controller 165. GPU 169 can execute program instructions related to graphics processing. The GPU 169 may receive graphics data through the external memory controller 165, and may send graphics data processed by the GPU 169 to the outside of the system-on-chip 160 through the external memory controller 165. You can also send it. The transaction unit 167 can monitor data transactions of each functional block, and the PMIC 168 can control power supplied to each functional block according to the control of the transaction unit 167. The display controller 163 can transmit data generated inside the system-on-chip 160 to the display by controlling a display (or display device) outside the system-on-chip 160. The memory 164 may include non-volatile memory such as Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, etc., Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. It may also contain the same volatile memory.

FIG. 17 is a block diagram illustrating a computing system 170 including a memory for storing a program according to an exemplary embodiment of the present disclosure. A method of designing an integrated circuit, according to example embodiments of the present disclosure, such as at least some of the steps in the flowchart described above, may be performed on a computing system (or computer) 170.

Computing system 170 may be a stationary computing system, such as a desktop computer, workstation, server, etc., or a portable computing system, such as a laptop computer. As shown in FIG. 17, the computing system 170 includes a processor 171, input/output devices 172, a network interface 173, random access memory (RAM) 174, and read only memory (ROM) 175. ) and a storage device 176. The processor 171, input/output devices 172, network interface 173, RAM 174, ROM 175, and storage device 176 may be connected to the bus 177 and communicate with each other through the bus 177. Can communicate.

The processor 171 may be referred to as a processing unit, for example, a microprocessor (micro-processor), an application processor (AP), a digital signal processor (DSP), or a graphic processing unit (GPU), such as any instruction set (e.g., It may include at least one core capable of executing IA-32 (Intel Architecture-32), 64-bit extensions IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, the processor 171 can access memory, that is, RAM 174 or ROM 175, through the bus 177 and execute instructions stored in RAM 174 or ROM 175.

The RAM 174 may store a program 174_1 or at least a portion thereof for a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure, and the program 174_1 may cause the processor 171 to It is possible to perform at least some of the steps included in the method of designing, for example, the methods of FIG. 8. That is, the program 174_1 may include a plurality of instructions executable by the processor 171, and the plurality of instructions included in the program 174_1 allow the processor 171 to execute, for example, the instructions included in the above-described flowcharts. You can have at least some of the steps performed.

The storage device 176 may not lose stored data even if power supplied to the computing system 170 is cut off. For example, storage device 176 may include a non-volatile memory device or may include a storage medium such as magnetic tape, optical disk, or magnetic disk. Additionally, storage device 176 may be removable from computing system 170. The storage device 176 may store the program 174_1 according to an exemplary embodiment of the present disclosure, and the program 174_1 or At least part of it may be loaded into RAM 174. Alternatively, the storage device 176 may store a file written in a program language, and the program 174_1 or at least a portion thereof generated by a compiler or the like from the file may be loaded into the RAM 174. Additionally, as shown in FIG. 17, the storage device 176 may store a database 176_1, which may store information necessary for designing an integrated circuit, such as information on designed blocks, the cell of FIG. 8 It may include a library (D12) and/or design rules (D14).

The storage device 176 may store data to be processed by the processor 171 or data processed by the processor 171. That is, the processor 171 may generate data by processing data stored in the storage device 176 according to the program 174_1, and may store the generated data in the storage device 176. For example, the storage device 176 may store RTL data D17, netlist data D13, and/or layout data D15 of FIG. 8.

The input/output devices 172 may include an input device such as a keyboard, a pointing device, etc., and may include an output device such as a display device, a printer, etc. For example, a user may trigger execution of program 174_1 by processor 171, through input/output devices 172, RTL data D17 and/or netlist data D13 of FIG. 8. You can also input and check the layout data (D15) of FIG. 8.

Network interface 173 may provide access to a network external to computing system 170. For example, a network may include multiple computing systems and communication links, which may include wired links, optical links, wireless links, or any other type of links.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom.

Claims (20)

first cells and second cells extending in a first horizontal direction and arranged respectively in first and second rows adjacent to each other;
a first power line extending in the first horizontal direction along a first boundary between the first row and the second row in a power line layer, and configured to be applied with a first supply voltage;
a first contact extending from the first cell to the second cell in a second horizontal direction intersecting the first horizontal direction; and
An integrated circuit comprising a first downward via extending from a bottom surface of the first contact to a top surface of the first power line in a vertical direction. In claim 1,
The first downward via is aligned with the first boundary. In claim 1,
The first cell and the second cell include a first source/drain region and a second source/drain region, respectively,
The first contact is connected to the first source/drain region and the second source/drain region,
The first downward via extends in the vertical direction between the first source/drain region and the second source/drain region. In claim 3,
The integrated circuit wherein the distance between the first downward via and the first source/drain region is equal to the distance between the first downward via and the second source/drain region. In claim 1,
a first pattern extending in a first horizontal direction along the first boundary in a first wiring layer; and
The integrated circuit further includes a first upward via extending from a top surface of the first contact to a bottom surface of the first pattern in the vertical direction. In claim 5,
a second contact extending from the first cell in the second horizontal direction; and
The integrated circuit further includes a second upward via extending from a top surface of the second contact to a bottom surface of the first pattern in the vertical direction. In claim 1,
The first cell includes at least two gate electrodes extending in the second horizontal direction at a first pitch,
The integrated circuit, wherein the second cell has a length of the first pitch in the first horizontal direction. In claim 1,
Further comprising a plurality of gate electrodes extending in the second horizontal direction at a first pitch,
The first cell and the second cell have a length of the first pitch in the first horizontal direction. In claim 1,
Further comprising a third contact extending in the second horizontal direction parallel to the first contact,
The first downward via is connected to a lower surface of the third contact. In claim 1,
a plurality of contacts extending in the second horizontal direction parallel to the first contact;
Further comprising a plurality of downward vias each extending in the vertical direction from lower surfaces of the plurality of contacts to an upper surface of the first power line,
The integrated circuit is characterized in that the plurality of contacts are arranged at equal intervals in the first horizontal direction. In claim 1,
a third cell arranged in the second row;
a fourth cell extending in the first horizontal direction and disposed in a third row adjacent to the second row;
a second power line extending in the first horizontal direction along a second boundary between the second row and the third row in the power line layer and configured to be applied with a second supply voltage;
a fourth contact extending from the third cell to the fourth cell in a second horizontal direction intersecting the first horizontal direction; and
The integrated circuit further includes a second downward via extending from a lower surface of the fourth contact to an upper surface of the second power line in the vertical direction. In claim 11,
The second downward via is aligned with the second boundary. In claim 11,
The third cell and the fourth cell include a third source/drain region and a fourth source/drain region, respectively,
The fourth contact is connected to the third source/drain region and the fourth source/drain region,
The second downward via extends in the vertical direction between the third source/drain region and the fourth source/drain region. In claim 13,
The integrated circuit wherein the distance between the second downward via and the third source/drain region is equal to the distance between the second downward via and the fourth source/drain region. a first power line extending in a first horizontal direction in the power line layer and configured to be applied with a first supply voltage;
a plurality of first contacts, each extending in a second horizontal direction intersecting the first horizontal direction and connected to source/drain regions adjacent to the second horizontal direction; and
A plurality of first downward vias each extend in a vertical direction from lower surfaces of the plurality of first contacts to an upper surface of the first power line,
An integrated circuit, wherein the plurality of first contacts are arranged at equal intervals in the first horizontal direction. In claim 15,
a second power line extending from the power line layer in the first horizontal direction and configured to apply a second supply voltage;
a plurality of second contacts, each extending in the second horizontal direction and connected to source/drain regions adjacent to the second horizontal direction; and
a plurality of second downward vias extending from lower surfaces of the plurality of second contacts to an upper surface of the second power line in the vertical direction;
An integrated circuit, wherein the plurality of second contacts are arranged at equal intervals in the first horizontal direction. In claim 16,
The integrated circuit, wherein the plurality of second contacts are respectively aligned with the plurality of first contacts in the second horizontal direction. In claim 15,
a third power line extending from the power line layer in the first horizontal direction and configured to apply the first supply voltage;
a plurality of third contacts, each extending in the second horizontal direction and connected to source/drain regions adjacent to the second horizontal direction; and
and a plurality of third downward vias extending from the lower surfaces of the plurality of third contacts to the upper surface of the third power line in the vertical direction,
The integrated circuit, wherein the plurality of third contacts are respectively aligned with the plurality of first contacts in the second horizontal direction. In claim 15,
a plurality of fourth contacts, each extending in the second horizontal direction, connected to adjacent source/drain regions in the second horizontal direction, and alternately disposed with the plurality of first contacts in the first horizontal direction. Includes more contacts,
Each of the plurality of first downward vias is connected to lower surfaces of adjacent first and fourth contacts among the plurality of first contacts and the plurality of fourth contacts. A method for manufacturing an integrated circuit, comprising:
Obtaining first input data defining the integrated circuit including a plurality of standard cells;
Arranging a plurality of power lines extending in a first horizontal direction in a power line layer;
placing a plurality of virtual contacts, each extending in a second horizontal direction intersecting the first horizontal direction and overlapping one of the plurality of power lines;
deploying the plurality of standard cells based on the plurality of virtual contacts; and
Generating output data defining a layout including the plurality of arranged standard cells,
The method of arranging the plurality of standard cells includes arranging the standard cells such that the source region of the transistor overlaps the virtual contact.

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