KR20230133163A - Integrated circuit including active pattern having variable width and method for designing the same - Google Patents

Abstract

An integrated circuit includes: a first active pattern group including a plurality of active patterns extended in a first direction in a first row extended in a first direction and overlapping each other in the first direction; and a plurality of gate electrodes extended in the first row in a second direction perpendicular to the first direction. Two active patterns adjacent to each other in the first direction in the first active pattern group may have the same width, or may have widths different from each other by a first offset or a second offset in the second direction.

Description

Integrated circuit including active pattern having variable width and method of designing same

The technical idea of the present disclosure relates to integrated circuits, and more specifically, to an integrated circuit including an active pattern having a variable width and a method of designing the same.

Due to the development of semiconductor processes, devices of various structures are being developed, and each device may have unique characteristics. New devices may be formed by new sub-processes, and thus new design rules may be required to design integrated circuits including new devices.

The technical idea of the present disclosure provides an integrated circuit including an active pattern with a variable width and a method of designing the same.

An integrated circuit according to one aspect of the technical idea of the present disclosure includes a first active pattern group including a plurality of active patterns extending in a first direction and overlapping each other in the first direction in a first row extending in a first direction; and a plurality of gate electrodes extending in a second direction perpendicular to the first direction in the first row, wherein two active patterns adjacent to each other in the first direction in the first active pattern group are the same in the second direction. width, or may have widths that differ by a first offset or a second offset in the second direction.

An integrated circuit according to one aspect of the technical idea of the present disclosure may include a plurality of functional cells arranged in a first row extending in a first direction, and each of the plurality of functional cells arranged in the first row includes: It may include an active pattern extending in one direction, and at least one gate electrode extending in a second direction perpendicular to the first direction, each included in two functional cells adjacent to each other in the first row, and extending in the first direction. The two overlapping active patterns may have the same width in the second direction, or may have widths different from each other by the first offset or the second offset in the second direction.

According to one aspect of the technical idea of the present disclosure, an integrated circuit including a plurality of cells includes a first pattern and a second pattern extending in a first direction and adjacent to each other to supply power to the first cells among the plurality of cells, A plurality of first active patterns extending in a first direction between the first pattern and the second pattern and overlapping each other in the first direction, and in a second direction perpendicular to the first direction between the first pattern and the second pattern. It may include a plurality of extending first gate electrodes, and among the plurality of first active patterns, two first active patterns adjacent to each other in the first direction have the same width in the second direction or have the same width in the second direction. It may have different widths by either the first offset or the second offset.

According to the integrated circuit and method according to an exemplary embodiment of the present disclosure, the integrated circuit can be designed in consideration of the semiconductor process, thereby reducing the time and cost required to design the integrated circuit, and Yield can be improved.

Additionally, according to the integrated circuit and method according to the exemplary embodiment of the present disclosure, the integrated circuit may have high reliability, and accordingly, the reliability of applications including the integrated circuit may be improved.

In addition, according to the integrated circuit and method according to example embodiments of the present disclosure, an integrated circuit with high reliability can be easily designed, and thus the time-to-market of the integrated circuit is significantly reduced. It can be shortened.

The effects that can be obtained from the exemplary embodiments of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are common knowledge in the technical field to which the exemplary embodiments of the present disclosure belong from the following description. It can be clearly derived and understood by those who have it. That is, unintended effects resulting from implementing the exemplary embodiments of the present disclosure may also be derived by those skilled in the art from the exemplary embodiments of the present disclosure.

1A and 1B are diagrams showing examples of devices according to example embodiments of the present disclosure.
2A and 2B are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure.
3A and 3B are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure.
Figure 4 is a plan view showing the layout of a cell according to an exemplary embodiment of the present disclosure.
Figure 5 is a plan view showing the layout of an integrated circuit according to an exemplary embodiment of the present disclosure.
6A to 6F are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure.
7 is a flow chart illustrating a method for manufacturing an integrated circuit according to an example embodiment of the present disclosure.
Figure 8 is a block diagram showing a system-on-chip according to an exemplary embodiment of the present disclosure.
Figure 9 is a block diagram showing a computing system including a memory for storing a program according to an exemplary embodiment of the present disclosure.

1A and 1B are diagrams showing examples of devices according to example embodiments of the present disclosure. Specifically, FIG. 1A shows a fin field effect transistor (FinFET) 10a, and FIG. 1B shows a gate-all-around field effect transistor (GAAFET) 10b. For ease of illustration, FIGS. 1A and 1B show one of the two source/drain regions removed.

In this specification, the X-axis direction and the Y-axis direction may be referred to as a first direction and a second direction, respectively, and the Z-axis direction may be referred to as a vertical direction or a third direction. A plane consisting of the Orientally placed components may be referred to as being below other components. Additionally, the area of a component may refer to the size occupied by the component in a plane parallel to the horizontal plane, and the width of the component may refer to the length in a direction perpendicular to the direction in which the component extends. The surface exposed in the +Z direction may be referred to as the top surface, the surface exposed in the -Z direction may be referred to as the bottom surface, and the surface exposed in the ±X or ±Y direction may be referred to as the top surface. It can be referred to as a side. In the drawings, only some layers may be shown for convenience of illustration, and a via may be displayed even though it is located below the pattern of the wiring layer to indicate a connection between the pattern of the wiring layer and the sub-pattern. Additionally, a pattern made of a conductive material, such as a pattern of a wiring layer, may be referred to as a conductive pattern, or may simply be referred to as a pattern.

An integrated circuit may be manufactured by a semiconductor process and may include a plurality of elements. For example, an integrated circuit may include active elements such as transistors, or passive elements such as capacitors. A semiconductor process may include a series of sub-processes to form a transistor with a predefined structure. For example, FinFET (10a) and GAAFET (10b) may be formed through a semiconductor process. In some embodiments, the semiconductor process may include sub-processes for forming a transistor with a structure different from FinFET 10a and GAAFET 10b. For example, the nanosheets for the P-type transistor and the nanosheets for the N-type transistor are separated by a dielectric wall, thereby forming a ForkFET in which the N-type transistor and the P-type transistor have a closer structure through a semiconductor process. It can be. Additionally, field effect transistors (FETs) such as complementary FETs (CFETs), negative FETs (NCFETs), and carbon nanotube (CNTs) FETs, as well as bipolar junction transistors can be formed through semiconductor processes.

Referring to FIG. 1A, the FinFET 10a includes fin-shaped first to third active patterns A1 to A3 extending in the X-axis direction between shallow trench isolations (STIs) and Y-axis directions. It may be formed by an extending gate electrode (G). Source/drain regions (SD) may be formed on both sides of the gate electrode (G), and first to third channels (CH1 to CH3) corresponding to the first to third active patterns (A1 to A3), respectively, are source/drain regions (SD). It may be formed between the /drain region (SD). The first to third channels (CH1 to CH3) may overlap the gate electrode (G) in the Y-axis and Z-axis directions, and an insulating film is formed between the first to third channels (CH1 to CH3) and the gate electrode (G). This can be formed. In some embodiments, the source/drain region SD may be composed of three parts respectively corresponding to the first to third active patterns A1 to A3, differently from what is shown in FIG. 1A.

The effective channel width of FinFET 10a may depend on the number of active patterns, and thus FinFET 10a may have a current driving capability corresponding to the number of active patterns. For example, a FinFET including one or two channels may have lower current driving capability and power consumption than FinFET 10a of FIG. 1A. Additionally, a FinFET containing more than three channels may have higher current driving capability and power consumption than FinFET 10a of Figure 1A. The integrated circuit may include FinFETs with varying numbers of channels for optimization of performance and efficiency.

Referring to FIG. 1B, the GAAFET 10b may be formed by an active pattern A1 extending in the X-axis direction and a gate electrode G extending in the Y-axis direction. Source/drain regions (SD) may be formed on both sides of the gate electrode (G), and may be spaced apart from each other in the Z-axis direction on the active pattern (A1), extend in the X-axis direction, and have a first width (W1). to third nanosheets (NS1 to NS3) may form channels between the source/drain regions (SD). As shown in FIG. 1B, the GAAFET 10b including a nanosheet may be referred to as a multi-bridge channel field effect transistor (MBCFET). The first to third nanosheets may overlap the gate electrode (G) in the Y-axis and Z-axis directions, and an insulating film is formed between the first to third nanosheets and the gate electrode (G). It can be.

The effective channel width of the GAAFET 10b may depend on the number and width of the nanosheets, and accordingly, the GAAFET 10b may have a current driving capability corresponding to the number and width of the nanosheets. For example, a GAAFET including one or two nanosheets or nanosheets having a width smaller than the first width W1 may have lower current driving capability and power consumption than the GAAFET 10b of FIG. 1B. there is. Additionally, a GAAFET including more than three nanosheets or nanosheets having a width greater than the first width W1 may have higher current driving capability and power consumption than the GAAFET 10b of FIG. 1B. Integrated circuits may include GAAFETs containing nanosheets of varying numbers and widths to optimize performance and efficiency.

Transition of an active pattern may refer to a change in the number and/or width of active patterns in adjacent devices. The FinFET (10a) can implement the transition of the active pattern by adjusting the number of channels (or the number of fins), while the GAAFET (10b) can implement the transition of the active pattern by adjusting the first width (W1) of the nanosheet. Transitions can be implemented, and accordingly, the GAAFET (10b) can support devices with more diverse characteristics than the FinFET (10a).

As the size of the device decreases for high integration, the difficulty of the semiconductor process may increase and the transition of the active pattern may be limited by the semiconductor process. For example, if a large transition of the active pattern occurs in adjacent devices, for example, if a structure is designed in which the width of the nanosheet is greatly reduced or greatly increased in an integrated circuit, the semiconductor process may not be able to easily implement the designed structure. You can. Accordingly, when a large transition of the active pattern occurs, the yield of the integrated circuit may decrease, or the area of the integrated circuit may increase due to a space for the transition of the active pattern (eg, diffusion break).

As will be explained below with reference to the drawings, integrated circuits can be designed in consideration of the semiconductor process, thereby not only reducing the time and cost required to design the integrated circuit, but also improving the yield of the integrated circuit. It can be. Additionally, integrated circuits can have high reliability, and thus the reliability of applications including integrated circuits can be improved. Additionally, integrated circuits with high reliability can be easily designed, and thus the time-to-market of the integrated circuit can be significantly shortened. In the following, GAAFET, or MBCFET, will mainly be described as an example of a device, but it is noted that the exemplary embodiments of the present disclosure are not limited thereto. Additionally, although the transition of the active pattern that occurs by changing the width of the nanosheets will be mainly explained, it is noted that the transition of the active pattern may also occur by changing the number of nanosheets as described above.

2A and 2B are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure. Hereinafter, overlapping content in the description of FIGS. 2A and 2B will be omitted.

Referring to FIG. 2A, an integrated circuit may include a plurality of standard cells. A standard cell is a unit of layout included in an integrated circuit and may simply be referred to as a cell. Cells may contain transistors and may be designed to perform predefined functions. In an integrated circuit, cells may be arranged in rows. For example, in FIG. 2A, the first row (R1) and the second row (R2) may extend in the X-axis direction, and cells are arranged in the first row (R1) and/or the second row (R2) It can be. A cell placed in one row may be referred to as a single height cell, and a cell placed in two or more consecutive rows may be referred to as a multi-height cell. Single-height cells placed in the first row (R1) may have a first height (H1) in the Y-axis direction, and single-height cells placed in the second row (R2) may have a second height (H2) in the Y-axis direction. ), and the multi-height cells continuously arranged in the first row (R1) and the second row (R2) correspond to the sum of the first height (H1) and the second height (H2) in the Y-axis direction. It can have height.

In some embodiments, the first height H1 of the first row R1 and the second height H2 of the second row R2 may be the same or different. For example, as shown in FIG. 2A, the second height H2 may be greater than the first height H1 (H2>H1). Rows with different heights can be arranged in various ways. For example, rows with the first height H1 and rows with the second height H2 may be arranged alternately at a ratio of 1:1, 2:2, 4:4, etc.

Patterns for powering the cells may be placed on the boundaries of the rows. For example, as shown in FIG. 2A, the first to third metal patterns M21 to M23 may extend in the X-axis direction on the boundaries of the first row R1 and the second row R2. . A negative supply voltage (VSS) may be applied to the first and third metal patterns (M21, M23), and an n-channel field effect transistor (NFET) may be installed adjacent to the first and third metal patterns (M21, M23). can be placed. Additionally, a positive supply voltage (VDD) may be applied to the second metal pattern (M22), and a p-channel field effect transistor (PFET) may be disposed adjacent to the second metal pattern (M22).

The integrated circuit may include active patterns extending in the X-axis direction, and the cell may include a transistor formed by the active patterns. For example, as shown in FIG. 2A, the integrated circuit 20a includes, in the first row R1, a plurality of first active patterns A11 to A13 overlapping each other in the X-axis direction and It may include a plurality of second active patterns A21 to A23 that overlap each other. In addition, in the second row, the integrated circuit 20a includes a plurality of third active patterns (A3 to A33) overlapping each other in the X-axis direction and a plurality of fourth active patterns (A41 to A41) overlapping with each other in the A43) may be included. As shown in FIG. 2A, a plurality of first active patterns A11 to A13 and a plurality of fourth active patterns adjacent to the first and third metal patterns M21 and M23 to which the negative supply voltage VSS is applied. The patterns A41 to A43 may form an n-channel field effect transistor (NFET), while a plurality of second active patterns are adjacent to the second metal pattern M22 to which the positive supply voltage VDD is applied. (A21 to A23) and the plurality of second active patterns (A31 to A33) may form a p-channel field effect transistor (PFET).

In some embodiments, the transition of the activation pattern may be limited to a predefined size. For example, as shown in FIG. 2A , the transition of the active pattern in the plurality of first active patterns A11 to A13 in the first row R1 may be limited to the first offset OS1. Accordingly, the difference between the widths of the adjacent first active patterns A11 and A12 may correspond to the first offset OS1, and the difference between the widths of the adjacent first active patterns A12 and A13 may also correspond to the first offset OS1. It can support offset (OS1). Additionally, the transition of the active pattern in the plurality of second active patterns A21 to A23 in the first row R1 may be limited to the second offset OS2. In some embodiments, the first offset (OS1) and the second offset (OS2) may be the same. Similarly, the transition of the active pattern in the plurality of third active patterns A31 to A33 in the second row R2 may be limited to the third offset OS3, and the plurality of third active patterns A31 to A33 in the second row R2 may be limited to the third offset OS3. The transition of the active patterns in the four active patterns A41 to A43 may be limited to the fourth offset OS4. In some embodiments, the third offset (OS3) and the fourth offset (OS4) may be the same. The first to fourth offsets OS1 to OS4 may be defined by a semiconductor process for manufacturing the integrated circuit 20a, thereby eliminating errors due to excessive transition of the active pattern in the integrated circuit 20a. You can.

In some embodiments, the widths of the active patterns in the first row (R1) and the widths of the active patterns in the second row (R2) may be different. For example, the maximum width (or minimum width) of the plurality of first active patterns A11 to A13 in the first row R1 is the maximum width of the fourth active patterns A41 to A43 in the second row R2. (or minimum width) may be different. Additionally, the maximum width (or minimum width) of the plurality of second active patterns A21 to A23 in the first row R1 is the maximum width (or minimum width) of the third active patterns A31 to A33 in the second row R2. minimum width) may be different.

Referring to FIG. 2B, the active pattern in integrated circuit 20b can have one of two widths. For example, as shown in FIG. 2B, each of the plurality of first active patterns (A11 to A13) overlapped with each other in the X-axis direction in the first row (R1) has a difference by the first offset (OS1). It can have one of two widths (W11, W12). In addition, each of the plurality of second active patterns A21 to A23 overlapped with each other in the You can have In some embodiments, the first offset (OS1) and the second offset (OS2) may be the same. In some embodiments, the widths W11 and W12 of the plurality of first active patterns A11 to A13 may be equal to the widths W21 and W22 of the plurality of second active patterns A21 to A23, respectively. there is. Similarly, in the second row, each of the plurality of third active patterns (A31 to A34) overlapped with each other in the Each of the plurality of fourth active patterns A41 to A43 overlapping each other in the X-axis direction may have one of two widths W41 and W42 that are different from each other by the fourth offset OS4. In some embodiments, the third offset (OS3) and the fourth offset (OS4) may be the same. In some embodiments, the widths W31 and W32 of the plurality of third active patterns A31 to A33 may be equal to the widths W41 and W42 of the plurality of fourth active patterns A41 to A43, respectively. there is.

3A and 3B are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure. In some embodiments, a cell may terminate with a diffusion break, and a transition in the activity pattern may occur at the diffusion break. In some embodiments, the activation pattern within a cell may have a constant width. For example, as shown in FIGS. 3A and 3B, the active pattern may have a constant width within a cell, while having different widths in different cells. Hereinafter, overlapping content in the description of FIGS. 3A and 3B will be omitted.

Referring to FIG. 3A, the integrated circuit 30a may include a first cell C31a and a second cell C32a. The first cell C31a may include active patterns A11 and A21 extending in the X-axis direction and gate electrodes extending in the Y-axis direction. The second cell C32a may include active patterns A12 and A22 extending in the X-axis direction and gate electrodes extending in the Y-axis direction. The gate electrodes may extend in the Y-axis direction with a contact poly pitch (CPP), and in FIG. 3A, each of the first cell (C31a) and the second cell (C32a) may have a length in the X-axis direction corresponding to 3CPP. .

Diffusion breaks may be formed instead of gate electrodes at the boundaries parallel to the Y axis of the first cell C31a and the second cell C32a, and the first cell C31a and the second cell C32a are disposed adjacent to each other. ) can share one diffusion break. As shown in FIG. 3A, the diffusion break disposed at the position of the gate electrode may be referred to as a single diffusion break (SDB) or a dummy gate. In some embodiments, different from what is shown in FIG. 3A, a cell may have boundaries extending in the X-axis direction between gate electrodes, and the diffusion break formed between the gates of adjacent cells may be double diffusion (DDB). break).

As shown in FIG. 3A, the active pattern A11 for the PFET in the first cell C31a may have a first width W1, and the active pattern A12 for the NFET in the second cell C32a may have a first width W1. may have a second width (W2). As described above with reference to FIGS. 2A and 2B, the second width W2 may be larger than the first width W1 by the first offset OS1. The width of the active pattern may be changed at the diffusion break between the first cell C31a and the second cell C32a, and the active pattern may be removed from the diffusion break.

Referring to FIG. 3B, the integrated circuit 30b may include first to fourth cells C31b to C34b. The first cell C31b may include active patterns A11 and A21 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The second cell C32b may include active patterns A12 and A22 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. As shown in FIG. 3B, the active pattern A11 of the first cell C31b and the active pattern A12 of the second cell C32b may have a first width W1, and the active pattern A12 of the first cell C31b may have a first width W1. ) and the second cell C32b may be separated from each other by an SDB extending in the Y-axis direction.

The fourth cell C34b may include active patterns A13 and A23 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The second width W2 of the active pattern A13 of the fourth cell C34b may be greater than the first width W1 of the active pattern A12 of the second cell C32b by the first offset OS1. . Unlike the integrated circuit 30a of FIG. 3A, the transition of the active pattern in the integrated circuit 30b of FIG. 3B may require a diffusion break extending in the Y-axis direction with a width of CPP or more. Accordingly, the integrated circuit 30b may include a third cell C33b between the second cell C32b and the fourth cell C34b, and active patterns may be removed from the third cell C33b. . In this specification, cells designed to include a transistor (or active pattern) and perform a function by a transistor, such as the first cell (C31b), the second cell (C32b), and the fourth cell (C34b), have a function. It may be referred to as a cell. Additionally, like the third cell C33b, a cell inserted between functional cells for transition of the active pattern may be referred to as a filler cell. In some embodiments, different from what is shown in FIG. 3B, the pillar cell may have a length in the X-axis direction corresponding to CPP or exceeding 2CPP.

Figure 4 is a plan view showing the layout of a cell according to an exemplary embodiment of the present disclosure. In some embodiments, transitions in activity patterns may occur within a cell.

Referring to FIG. 4 , the cell C40 may include active patterns A11 and A12 that overlap each other in the X-axis direction and active patterns (A21 and A22) that overlap each other in the X-axis direction. The width W12 of the active pattern A12 may be larger than the width W11 of the active pattern A11 by the first offset OS1, and the width W22 of the active pattern A22 may be larger than the width W11 of the active pattern A11. It may be larger than the width W21 by the second offset OS2. The first offset (OS1) and the second offset (OS2) may be defined by a semiconductor process, and the cell C40 includes a transition of an active pattern corresponding to the first offset (OS1) or the second offset (OS2). It can be designed to do so. Accordingly, the cell C40 can be designed to have optimized performance and efficiency, while errors caused by the cell C40 can be prevented.

Figure 5 is a plan view showing the layout of the integrated circuit 50 according to an exemplary embodiment of the present disclosure. As described above with reference to FIGS. 2A and 2B, the integrated circuit 50 may include a plurality of cells, and the plurality of cells may include rows extending in the X-axis direction, such as the first row R1 and/or It may be placed in the second row (R2). As described above with reference to FIGS. 2A and 2B, the first height H1 of the first row R1 and the second height H2 of the second row R2 may be the same or different.

In some embodiments, the width of the active pattern for NFETs and the width of the active pattern for PFETs in a cell may be different. For example, as shown in FIG. 5 , in the first row R1, the active pattern A11 for the NFET and the active pattern A12 for the PFET may extend in the X-axis direction. The width W11 of the active pattern A11 for the NFET may be smaller than the width W12 of the active pattern A12 for the PFET (W11<W12). In some embodiments, different from what is shown in FIG. 5, the width W11 of the active pattern A11 for the NFET may be greater than the width W12 of the active pattern A12 for the PFET (W11>W12 ). Additionally, as shown in FIG. 5 , in the second row R2, the active pattern A21 for the PFET and the active pattern A22 for the NFET may extend in the X-axis direction. The width W21 of the active pattern A21 for the PFET may be larger than the width W22 of the active pattern A22 for the NFET (W21>W22). In some embodiments, different from what is shown in FIG. 5, the width W21 of the active pattern A21 for the PFET may be smaller than the width W22 of the active pattern A22 for the NFET (W11<W12 ).

6A to 6F are plan views showing layouts of integrated circuits according to example embodiments of the present disclosure. The plan views of FIGS. 6A to 6F show examples in which active patterns each having different widths are arranged in various ways. 6A to 6F, each of the integrated circuits 60a to 60f includes first to third metal patterns M61 to 3 extending in the X-axis direction on the boundaries of the first row R1 and the second row R2. M63) may be included. A positive supply voltage (VDD) may be applied to the first and third metal patterns (M61, M63), and a negative supply voltage (VSS) may be applied to the second metal pattern (M62).

Referring to FIG. 6A , the integrated circuit 60a may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, the integrated circuit 60a may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction in the first row R1, and overlapping each other in the X-axis direction. It may include a plurality of second active patterns A21 to A24. In some embodiments, the transition of the activation pattern may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be equal to the offset between adjacent active patterns A12 and A13, while the offset between adjacent active patterns A13 and A14 may be equal to the offset between adjacent active patterns A11 and A12. may be different.

In some embodiments, the active patterns may have boundaries overlapping a line extending in the X-axis direction. For example, as shown in FIG. 6A, the plurality of first active patterns A11 to A14 may have boundaries that overlap with the line X1-X1' extending in the The patterns A21 to A24 may have boundaries that overlap with the line X2-X2' extending in the X-axis direction. As shown in FIG. 6A, the lines X1-X1' and lines And a plurality of second active patterns A21 to A24 may be disposed between lines X1-X1' and lines X2-X2'.

Referring to FIG. 6B , the integrated circuit 60b may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, the integrated circuit 60b may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction in the first row R1, and overlapping each other in the X-axis direction. It may include a plurality of second active patterns A21 to A24. In some embodiments, the transition of the activation pattern may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be equal to the offset between adjacent active patterns A12 and A13, while the offset between adjacent active patterns A13 and A14 may be equal to the offset between adjacent active patterns A11 and A12. may be different.

In some embodiments, the active patterns may have boundaries overlapping a line extending in the X-axis direction. For example, as shown in FIG. 6B, the plurality of first active patterns A11 to A14 may have boundaries that overlap with the line X1-X1' extending in the The patterns A21 to A24 may have boundaries that overlap with the line X2-X2' extending in the X-axis direction. As shown in FIG. 6B, the lines X1-X1' and lines X2-X2' may be adjacent to the center of the first row R1, respectively, and accordingly, the lines It may extend in the X-axis direction between the first active patterns A11 to A14 and the plurality of second active patterns A21 to A24.

Referring to FIG. 6C , the integrated circuit 60c may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, the integrated circuit 60c may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction in the first row R1, and overlapping each other in the X-axis direction. It may include a plurality of second active patterns A21 to A24. In some embodiments, the transition of the activation pattern may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be equal to the offset between adjacent active patterns A12 and A13, while the offset between adjacent active patterns A13 and A14 may be equal to the offset between adjacent active patterns A11 and A12. may be different.

In some embodiments, the active patterns may have boundaries overlapping a line extending in the X-axis direction. For example, as shown in FIG. 6C, the plurality of first active patterns A11 to A14 may have boundaries that overlap with the line X1-X1' extending in the The patterns A21 to A24 may have boundaries that overlap with the line X2-X2' extending in the X-axis direction. As shown in FIG. 6C, line X1-X1' may be adjacent to the border of first row R1, while line X2-X2' may be adjacent to the center of first row R1. Accordingly, a plurality of first active patterns (A11 to A14) may be disposed between lines X1-X1' and lines X2-X2', and lines ) and may extend in the X-axis direction between lines X2-X2'.

Referring to FIG. 6D , the integrated circuit 60d may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, the integrated circuit 60d may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction in the first row R1, and overlapping each other in the X-axis direction. It may include a plurality of second active patterns A21 to A24. In some embodiments, the transition of the activation pattern may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be equal to the offset between adjacent active patterns A12 and A13, while the offset between adjacent active patterns A13 and A14 may be equal to the offset between adjacent active patterns A11 and A12. may be different.

In some embodiments, each of the active patterns may be aligned so that its center overlaps a line extending in the X-axis direction. For example, as shown in FIG. 6D, each of the plurality of first active patterns A11 to A14 may be aligned so that its center overlaps the line X1-X1' extending in the Each of the two active patterns A21 to A24 may be aligned so that its center overlaps the line X2-X2' extending in the X-axis direction.

Referring to FIG. 6E , the integrated circuit 60e may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, the integrated circuit 60e may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction in the first row R1, and overlapping each other in the X-axis direction. It may include a plurality of second active patterns A21 to A24. Additionally, the integrated circuit 60e may include a plurality of third active patterns A31 to A34 overlapping each other in the X-axis direction in the second row R2. In some embodiments, the transition of the activation pattern may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be equal to the offset between adjacent active patterns A12 and A13, while the offset between adjacent active patterns A13 and A14 may be equal to the offset between adjacent active patterns A11 and A12. may be different.

In some embodiments, the active patterns may be arranged and have a width such that they have a constant distance from adjacent active patterns in the Y-axis direction. For example, as shown in FIG. 6E, in the first row R1, the plurality of first active patterns A11 to A14 correspond to the plurality of second active patterns A21 to A24 and the first plurality of active patterns A11 to A14. Each may be spaced apart by a distance D1. Additionally, the plurality of second active patterns A21 to A24 in the first row may be spaced apart from the corresponding plurality of third active patterns A31 to A34 by a second distance D2. The first distance D1 and the second distance D2 may be the same or different.

Referring to FIG. 6F , the integrated circuit 60D may include active patterns extending in the X-axis direction in the first row R1 and the second row R2. For example, the integrated circuit 60D may include a plurality of first active patterns A11 to A14 overlapping each other in the X-axis direction in the first row R1, and overlapping each other in the X-axis direction. may include a plurality of second active patterns A21 to A24. Additionally, the integrated circuit 60f may include a plurality of third active patterns A31 to A34 overlapping each other in the X-axis direction in the second row R2. In some embodiments, the transition of the activation pattern may support two offsets. For example, the offset between adjacent active patterns A11 and A12 may be equal to the offset between adjacent active patterns A12 and A13, while the offset between adjacent active patterns A13 and A14 may be equal to the offset between adjacent active patterns A11 and A12. may be different.

In some embodiments, each of the active patterns may be aligned so that its center overlaps a line extending in the X-axis direction. For example, as shown in FIG. 6F, each of the plurality of first active patterns A11 to A14 may be aligned so that its center overlaps the line X1-X1' extending in the Each of the two active patterns (A21 to A24) may be aligned so that its center overlaps the line X2-X2' extending in the It can be aligned to overlap the line X3-X3' extending in the direction.

In some embodiments, each of the active patterns may have a width such that it has a constant distance from an adjacent active pattern in the Y-axis direction. For example, as shown in FIG. 6F, in the first row R1, the plurality of first active patterns A11 to A14 have a first distance from the corresponding plurality of second active patterns A21 to A24. Each can be spaced apart by (D1). Additionally, the plurality of second active patterns A21 to A24 in the first row R1 may be spaced apart from the corresponding plurality of third active patterns A31 to A34 by a second distance D2. The first distance D1 and the second distance D2 may be the same or different.

7 is a flow chart illustrating a method for manufacturing an integrated circuit (IC) according to an example embodiment of the present disclosure. Specifically, the flowchart of FIG. 7 shows an example of a method for manufacturing an integrated circuit (IC) containing standard cells. As shown in FIG. 7, a method for manufacturing an integrated circuit (IC) may include a plurality of steps S10, S30, S50, S70, and S90.

The cell library (or standard cell library) D12 may include information about standard cells, such as information about functions, characteristics, layout, etc. In some embodiments, cell library D12 may define standard cells each containing active patterns of different widths. In some embodiments, the cell library D12 may define standard cells whose widths change internally. In some embodiments, the cell library D12 may define filler cells inserted for transition of the active pattern. In some embodiments, the cell library D12 may define standard cells including an active pattern for a PFET and an active pattern for an NFET each having different widths.

Design rules (D14) may include requirements that the layout of an integrated circuit (IC) must comply with. For example, the design rule D14 may include requirements for the distance (space) between patterns in the same layer, the minimum width of the pattern, the routing direction of the wiring layer, etc. In some embodiments, design rule D14 may define a minimum separation distance within the same track of the wiring layer.

In step S10, a logical synthesis operation may be performed to generate a netlist (D13) from RTL data (D11). For example, a semiconductor design tool (e.g., a logic synthesis tool) synthesizes logic by referencing a cell library (D12) from RTL data (D11) written in a Hardware Description Language (HDL) such as VHSIC Hardware Description Language (VHDL) and Verilog. By performing , a netlist D13 including a bitstream or a netlist can be created. The netlist D13 may correspond to the input of place and routing, which will be described later.

In step S30, cells may be deployed. For example, a semiconductor design tool (eg, P&R tool) may place standard cells used in the netlist D13 with reference to the cell library D12 and design rule D14. In some embodiments, design rule D14 may define transitions of activation patterns allowed in one row. For example, the design rule D14 may define at least one offset allowed in one row, and mutually adjacent active patterns may have the same width or be offset by at least one offset defined by the design rule D14. Each can have different widths. The semiconductor design tool can select a standard cell containing an active pattern with an appropriate width from the cell library D12 by considering adjacent standard cells, and can place the selected standard cell.

In step S50, the pins of the cells may be routed. For example, a semiconductor design tool can generate interconnections that electrically connect the output pins and input pins of placed standard cells, and layout data (D15) defining the placed standard cells and the created interconnections. ) can be created. The interconnections may include a pattern of vias and/or interconnection layers of vias. In some embodiments, the interconnections may include a pattern for connecting disparate devices. The layout data D15 may have a format such as GDSII, for example, and may include geometric information of cells and interconnections. The semiconductor design tool can refer to the design rule (D14) while routing the pins of the cells. Layout data D15 may correspond to the output of placement and routing. Step S50 alone, or steps S30 and S50 collectively, may be referred to as a method for designing an integrated circuit.

In step S70, an operation of manufacturing a mask may be performed. For example, in photolithography, optical proximity correction (OPC) to correct distortion such as refraction due to the characteristics of light may be applied to the layout data D15. Patterns on a mask may be defined to form patterns arranged in a plurality of layers based on OPC applied data, and at least one mask (or photomask) may be manufactured to form patterns in each of the plurality of layers. You can. In some embodiments, the layout of the integrated circuit (IC) may be limitedly modified in step S70, and the limited modification of the integrated circuit (IC) in step S70 may be performed after optimizing the structure of the integrated circuit (IC). As a treatment, it may be referred to as design polishing.

In step S90, an operation of fabricating an integrated circuit (IC) may be performed. For example, an integrated circuit (IC) may be manufactured by patterning a plurality of layers using at least one mask fabricated in step S70. Front-end-of-line (FEOL) includes, for example, planarizing and cleaning the wafer, forming a trench, forming a well, and forming a gate electrode. may include forming a source and a drain, and by FEOL, individual elements, such as transistors, capacitors, resistors, etc., may be formed on the substrate. Additionally, back-end-of-line (BEOL) includes, for example, siliciding the gate, source, and drain regions, adding a dielectric, planarizing, forming holes, and adding metal layers. , forming a via, forming a passivation layer, etc., and by BEOL, individual elements, such as transistors, capacitors, resistors, etc., may be interconnected. In some embodiments, middle-of-line (MOL) may be performed between the FEOL and BEOL and contacts may be formed on the individual devices. The integrated circuit (IC) can then be packaged in a semiconductor package and used as a component in a variety of applications.

FIG. 8 is a block diagram illustrating a system on chip (SoC) 80 according to an example embodiment of the present disclosure. The system-on-chip 80 is a semiconductor device and may include an integrated circuit according to an example embodiment of the present disclosure. The system-on-chip 80 implements complex blocks such as IP (intellectual property) that perform various functions on a single chip, and is used in the method of designing an integrated circuit according to example embodiments of the present disclosure. Thus, the system-on-chip 80 can be designed, and thus the system-on-chip 80 can provide high yield and reliability, and have optimal performance and efficiency. Referring to FIG. 8, the system-on-chip 80 includes a modem 82, a display controller 83, a memory 84, an external memory controller 85, a central processing unit (CPU) 86, and a transaction unit. (87), it may include a PMIC (88), and a graphics processing unit (GPU) (89), and each functional block of the system-on-chip (80) can communicate with each other through the system bus (81).

The CPU 86, which can control the operation of the system-on-chip 80 at the top layer, can control the operation of other functional blocks 82 to 89. The modem 82 can demodulate a signal received from outside the system-on-chip 80 or modulate a signal generated inside the system-on-chip 80 and transmit it to the outside. . The external memory controller 85 may control the operation of transmitting and receiving data from an external memory device connected to the system-on-chip 80. For example, programs and/or data stored in an external memory device may be provided to the CPU 86 or GPU 89 under the control of the external memory controller 85. The GPU 89 can execute program instructions related to graphics processing. The GPU 89 may receive graphics data through the external memory controller 85, and may send graphics data processed by the GPU 89 to the outside of the system-on-chip 80 through the external memory controller 85. You can also send it. The transaction unit 87 can monitor data transactions of each functional block, and the PMIC 88 can control power supplied to each functional block according to the control of the transaction unit 87. The display controller 83 can transmit data generated inside the system-on-chip 80 to the display by controlling a display (or display device) outside the system-on-chip 80. The memory 84 may include non-volatile memory such as Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, etc., Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. It may also contain the same volatile memory.

FIG. 9 is a block diagram illustrating a computing system 90 including a memory for storing a program according to an exemplary embodiment of the present disclosure. A method of designing an integrated circuit, according to example embodiments of the present disclosure, such as at least some of the steps in the flowchart described above, may be performed on a computing system (or computer) 90.

Computing system 90 may be a stationary computing system, such as a desktop computer, workstation, server, etc., or a portable computing system, such as a laptop computer. As shown in Figure 9, the computing system 90 includes a processor 91, input/output devices 92, a network interface 93, random access memory (RAM) 94, and read only memory (ROM) 95. ) and a storage device 96. The processor 91, input/output devices 92, network interface 93, RAM 94, ROM 95, and storage device 96 may be connected to the bus 97 and communicate with each other through the bus 97. Can communicate.

The processor 91 may be referred to as a processing unit, such as a microprocessor, an application processor (AP), a digital signal processor (DSP), or a graphic processing unit (GPU), and may have any instruction set (e.g., It may include at least one core capable of executing IA-32 (Intel Architecture-32), 64-bit extensions IA-32, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). For example, the processor 91 can access memory, such as RAM 94 or ROM 95, through the bus 97 and execute instructions stored in RAM 94 or ROM 95.

The RAM 94 may store a program 94_1 or at least a portion thereof for a method of designing an integrated circuit according to an exemplary embodiment of the present disclosure, where the program 94_1 causes the processor 91 to: It is possible to perform at least some of the steps included in the method of designing, for example, the methods of FIG. 7. That is, the program 94_1 may include a plurality of instructions executable by the processor 91, and the plurality of instructions included in the program 94_1 allow the processor 91 to execute, for example, the instructions included in the above-described flowcharts. You can have at least some of the steps performed.

The storage device 96 may not lose stored data even if power supplied to the computing system 90 is cut off. For example, storage device 96 may include a non-volatile memory device or may include a storage medium such as magnetic tape, optical disk, or magnetic disk. Additionally, storage device 96 may be removable from computing system 90. The storage device 96 may store the program 94_1 according to an exemplary embodiment of the present disclosure, and the program 94_1 or At least part of it may be loaded into RAM 94. Alternatively, the storage device 96 may store a file written in a program language, and the program 94_1 or at least a portion thereof generated by a compiler or the like from the file may be loaded into the RAM 94. Additionally, as shown in FIG. 9 , the storage device 96 may store a database 96_1, which may store information necessary for designing an integrated circuit, such as information on designed blocks, the cell of FIG. 7 It may include a library (D12) and/or design rules (D14).

The storage device 96 may store data to be processed by the processor 91 or data processed by the processor 91. That is, the processor 91 may generate data by processing data stored in the storage device 96 according to the program 94_1, and may store the generated data in the storage device 96. For example, the storage device 96 may store RTL data D11, netlist D13, and/or layout data D15 of FIG. 7 .

Input/output devices 92 may include input devices such as keyboards, pointing devices, etc., and may include output devices such as display devices, printers, etc. For example, the user may trigger execution of the program 94_1 by the processor 91, through the input/output devices 92, and use the RTL data D11 and/or the netlist D13 of FIG. 7. You can also input or check the layout data (D15) of FIG. 7.

Network interface 93 may provide access to a network external to computing system 90. For example, a network may include multiple computing systems and communication links, which may include wired links, optical links, wireless links, or any other type of links.

As above, exemplary embodiments have been disclosed in the drawings and specification. Although embodiments have been described in this specification using specific terms, this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure as set forth in the claims. . Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom.

Claims (20)

a first active pattern group extending in a first row extending in a first direction and including a plurality of active patterns that overlap each other in the first direction; and
A plurality of gate electrodes extending in the first row in a second direction perpendicular to the first direction,
In the first active pattern group, two active patterns adjacent to each other in the first direction have the same width in the second direction or have widths different from each other by a first offset or a second offset in the second direction. Characterized integrated circuit. In claim 1,
The plurality of gate electrodes extend in the second direction at a first pitch,
The first active pattern group includes a first active pattern and a second active pattern adjacent to each other in the first direction and each having different widths in the second direction,
The first active pattern and the second active pattern are spaced apart from each other by at least one first pitch in the first direction. In claim 2,
An integrated circuit, wherein an active pattern is removed between the first active pattern and the second active pattern. In claim 1,
An integrated circuit, wherein each of the plurality of active patterns of the first active pattern group has a first width in the second direction or a second width greater than the first width by the first offset. In claim 1,
Further comprising a second active pattern group extending in the first direction in a second row adjacent to the first row and including a plurality of active patterns overlapping with each other in the first direction,
The first row and the second row each have different widths in the second direction. In claim 5,
In the second active pattern group, two active patterns adjacent to each other in the first direction have the same width in the second direction or have widths different from each other by a third offset or a fourth offset in the second direction,
The third offset is different from the first offset and the second offset. In claim 5,
An integrated circuit, wherein a maximum width of the plurality of active patterns of the first active pattern group in the second direction is different from a maximum width of the plurality of active patterns of the second active pattern group in the second direction. In claim 5,
An integrated circuit wherein the minimum width of the plurality of active patterns of the first active pattern group in the second direction is different from the minimum width of the plurality of active patterns of the second active pattern group in the second direction. . In claim 1,
Further comprising a third active pattern group extending from the first row in the first direction and including a plurality of active patterns overlapping with each other in the first direction,
In the third active pattern group, two active patterns adjacent to each other in the first direction have the same width in the second direction or have widths different from each other by the first offset or the second offset in the second direction. An integrated circuit characterized by having. In claim 9,
Each of the plurality of active patterns of the first active pattern group has a boundary overlapping with a first line extending in the first direction,
An integrated circuit, wherein each of the plurality of active patterns of the third active pattern group has a boundary overlapping with a second line extending in the first direction. In claim 10,
The first active pattern group and the third active pattern group are located between the first line and the second line. In claim 10,
The first line and the second line are between the first active pattern group and the third active pattern group. In claim 10,
The second line is between the first active pattern group and the third active pattern group. In claim 9,
The integrated circuit, wherein the plurality of active patterns of the first active pattern group are spaced apart from the plurality of active patterns of the third active pattern group by a first distance in the second direction. In claim 9,
Each of the plurality of active patterns of the first active pattern group has a center overlapped with a first line extending in the first direction,
An integrated circuit, wherein each of the plurality of active patterns of the third active pattern group has a center overlapped with a second line extending in the first direction. In claim 9,
An integrated circuit, wherein the active patterns of the first active pattern group and the active patterns of the third active pattern group, opposite in the second direction, each have different widths in the second direction. In claim 1,
Each of the plurality of active patterns of the first active pattern group includes at least one overlapping with at least one of the plurality of gates in the third direction and the second direction perpendicular to the first direction and the second direction. An integrated circuit comprising a nanosheet. comprising a plurality of functional cells arranged in a first row extending in a first direction,
Each of the plurality of functional cells arranged in the first row,
an active pattern extending in the first direction; and
At least one gate electrode extending in a second direction perpendicular to the first direction,
The two active patterns each included in two adjacent functional cells in the first row and overlapping each other in the first direction have the same width in the second direction, or have a first offset or a first offset in the second direction. An integrated circuit characterized by each having widths that differ by 2 offsets. In claim 18,
The plurality of functional cells include a first functional cell and a second functional cell adjacent to each other in the first direction,
The first functional cell includes a first active pattern having a first width in the second direction,
The second functional cell includes a second active pattern that overlaps the first active pattern in the first direction and has a second width different from the first width in the second direction,
The integrated circuit further comprising a pillar cell disposed between the first functional cell and the second functional cell in the first row. An integrated circuit comprising a plurality of cells,
first and second patterns extending in a first direction and adjacent to each other to supply power to first cells among the plurality of cells;
a plurality of first active patterns extending in the first direction between the first pattern and the second pattern and overlapping each other in the first direction; and
A plurality of first gate electrodes extending in a second direction perpendicular to the first direction between the first pattern and the second pattern,
Among the plurality of first active patterns, two first active patterns adjacent to each other in the first direction have the same width in the second direction, or have widths different from each other by a first offset or a second offset in the second direction. An integrated circuit characterized by having.

Images