CN116741777A - Integrated circuit including active pattern having variable width and design method thereof - Google Patents

Abstract

An integrated circuit may include: a first active pattern group extending in a first direction in a first row and including a plurality of active patterns overlapping each other in the first direction, the first row extending in the first direction; and a plurality of gate electrodes extending in a second direction perpendicular to the first direction in the first row, wherein two active patterns adjacent to each other in the first direction in the first active pattern group may have the same width in the second direction or have widths different by a first offset amount or a second offset amount in the second direction.

Description

Integrated circuit including active pattern having variable width and design method thereof

Cross Reference to Related Applications

The present application is based on and claims priority of korean patent application No.10-2022-0030331 filed on 3/10/2022 and korean patent application No. 10-2022-0076180 filed on 22/2022, which disclosures are incorporated herein by reference in their entireties.

Technical Field

The present inventive concept relates to an integrated circuit, and more particularly, to an integrated circuit including an active pattern having a variable width and a method of designing the same.

Background

Devices having various structures have been developed, and these devices may each have unique characteristics. New devices may be formed by new processes (e.g., sub-processes), and accordingly, new design rules may be beneficial in designing integrated circuits that include the new devices.

Disclosure of Invention

The present inventive concept provides an integrated circuit including an active pattern having a variable width and a method of designing the same.

According to one aspect of the inventive concept, there is provided an integrated circuit comprising: a first active pattern group extending in a first direction in a first row and including a plurality of active patterns overlapping each other in the first direction, the first row extending in the first direction; and a plurality of gate electrodes extending in a second direction perpendicular to the first direction in the first row, wherein two active patterns adjacent to each other in the first direction in the first active pattern group may have the same width in the second direction or have widths different by a first offset amount or a second offset amount in the second direction.

According to an aspect of the inventive concept, there is provided an integrated circuit including a plurality of functional units arranged in a first row extending in a first direction, wherein each of the plurality of functional units arranged in the first row may include an active pattern extending in the first direction and at least one gate electrode extending in a second direction perpendicular to the first direction, and two active patterns respectively included in two functional units adjacent to each other in the first row and overlapping each other in the first direction may have the same width in the second direction or have widths different by a first offset amount or a second offset amount in the second direction.

According to one aspect of the inventive concept, there is provided an integrated circuit comprising: a plurality of units; a first pattern and a second pattern extending in a first direction and adjacent to each other to supply power to a first cell of the plurality of cells; a plurality of first active patterns extending in a first direction between the first pattern and the second pattern and overlapping each other in the first direction; and a plurality of first gate electrodes extending between the first pattern and the second pattern along a second direction perpendicular to the first direction, wherein two first active patterns adjacent to each other in the first direction among the plurality of first active patterns may have the same width in the second direction or have widths differing by a first offset amount or a second offset amount in the second direction.

Drawings

Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

FIGS. 1A and 1B are perspective views of a device according to example embodiments;

fig. 2A and 2B are plan views showing a layout of an integrated circuit according to example embodiments;

fig. 3A and 3B are plan views showing a layout of an integrated circuit according to example embodiments;

Fig. 4 is a plan view showing a layout of cells according to an example embodiment;

FIG. 5 is a plan view showing a layout of an integrated circuit according to an example embodiment;

fig. 6A, 6B, 6C, 6D, 6E, and 6F are plan views showing a layout of an integrated circuit according to example embodiments;

FIG. 7 is a flowchart illustrating a method of manufacturing an integrated circuit according to an example embodiment;

FIG. 8 is a block diagram illustrating a system on a chip according to an example embodiment; and

FIG. 9 is a block diagram illustrating a computing system including memory for storing programs in accordance with an example embodiment.

Detailed Description

Fig. 1A and 1B are perspective views of a device according to example embodiments. For example, fig. 1A shows a fin field effect transistor (FinFET) 10a, and fig. 1B shows a gate-all-around field effect transistor (GAAFET) 10B. For ease of illustration, fig. 1A and 1B show a state in which one of the two source/drain regions has been removed.

Herein, the X-axis direction and the Y-axis direction may be referred to as a first direction (also referred to as a first horizontal direction) and a second direction (also referred to as a second horizontal direction), respectively, and the Z-axis direction may be referred to as a vertical direction or a third direction. The plane having the X-axis and the Y-axis may be referred to as a horizontal plane, the components arranged in the +z direction with respect to the other components may be referred to as components above the other components, and the components arranged in the-Z direction with respect to the other components may be referred to as components below the other components. In addition, the area of the component may refer to the size occupied by the component in a plane parallel to the horizontal plane, and the width of the component may refer to the length in a direction perpendicular to the direction in which the component extends (e.g., longitudinally extends). The surface exposed in the +z direction may be referred to as a top surface or an upper surface, the surface exposed in the-Z direction may be referred to as a bottom surface or a lower surface, and the surface exposed in the ±x direction or the ±y direction may be referred to as a side surface. In the drawings, only some layers may be shown for convenience of explanation, and the via hole may be shown although it is located under the upper pattern for indicating connection between the upper pattern and the lower pattern. In addition, a pattern made of a conductive material (for example, a pattern of a wiring layer) may be referred to as a conductive pattern or may be simply referred to as a pattern.

Integrated circuits may be fabricated by semiconductor processes and may include a plurality of devices. For example, the integrated circuit may include active devices such as transistors and/or passive devices such as capacitors. The semiconductor process may include a series of sub-processes for forming a transistor having a predefined structure. For example, the FinFET 10a and GAAFET 10b may be formed by a semiconductor process. In some embodiments, the semiconductor process may include a sub-process for forming a transistor having a structure different from that of the FinFET 10a and GAAFET 10 b. For example, the nanoflakes for P-type transistors and the nanoflakes for N-type transistors may be separated by dielectric walls, thereby forming a fork fet having structures of N-type transistors and P-type transistors adjacent to each other through a semiconductor process. In addition, bipolar junction transistors and Field Effect Transistors (FETs) (e.g., complementary FETs (CFETs), negative FETs (NCFETs), carbon Nanotube (CNT) FETs, etc.) may be formed by semiconductor processes.

Referring to fig. 1a, the finfet 10a may be formed of first to third active patterns A1 to A3 and a gate electrode G extending in the Y-axis direction, wherein the first to third active patterns A1 to A3 have a fin shape extending in the X-axis direction between Shallow Trench Isolations (STI). The source/drain regions SD may be formed at either side of the gate electrode G, and first to third channels CH1 to CH3 respectively corresponding to the first to third active patterns A1 to A3 may be formed between the source/drain regions SD. The first to third channels CH1 to CH3 may overlap the gate electrode G in the Y-axis and Z-axis directions, and an insulating layer may be formed between the gate electrode G and each of the first to third channels CH1 to CH3. In some embodiments, unlike the one shown in fig. 1A, the source/drain region SD may be composed of three portions corresponding to the first to third active patterns A1 to A3, respectively. As used herein, "element a extends in the X-direction" (or similar language) may mean that element a extends longitudinally in the X-direction. Furthermore, as used herein, "element a overlaps element B in the X-direction" (or similar language) means that there is at least one line extending in the X-direction and intersecting both elements a and B.

The effective channel width of the FinFET 10a may depend on the number of active patterns, and thus, the FinFET 10a may have current driving capability corresponding to the number of active patterns. For example, a FinFET including one or two channels may have lower current drive capability and power consumption than FinFET 10a of fig. 1A. Furthermore, finfets comprising more than three channels may have higher current drive capability and power consumption than FinFET 10a of fig. 1A. The integrated circuit may include finfets that include various numbers of channels to optimize performance and efficiency.

Referring to fig. 1b, gaafet 10b may be formed of an active pattern A1 extending in the X-axis direction and a gate electrode G extending in the Y-axis direction. The source/drain regions SD may be formed at either side of the gate electrode G, and the first to third nanoplatelets NS1 to NS3 spaced apart from each other in the Z-axis direction and extending in the X-axis direction while having the first width W1 may form channels between the source/drain regions SD. As shown in fig. 1B, GAAFET 10B comprising nanoplatelets may be referred to as a multi-bridge channel field effect transistor (MBCFET). The first to third nanoplatelets may overlap the gate electrode G in Y-axis and Z-axis directions, and an insulating layer may be formed between the gate electrode G and each of the first to third nanoplatelets.

The effective channel width of GAAFET10b may depend on the number and width of the nanoplatelets, and thus GAAFET10b may have a current driving capability corresponding to the number and width of the nanoplatelets. For example, a GAAFET including one or two nanoplatelets or including nanoplatelets having a width less than the first width W1 may have lower current drive capability and power consumption than GAAFET10B of fig. 1B. Further, GAAFET including more than three nanoplatelets or including nanoplatelets having a width greater than the first width W1 may have higher current driving capability and power consumption than GAAFET10B of fig. 1B. Integrated circuits may include GAAFET that includes various numbers and widths of nanoplatelets to optimize performance and efficiency.

The transition of the active patterns may refer to a change in the number and/or width of active patterns adjacent to each other in the device. The FinFET 10a may achieve the transition of the active pattern by adjusting the number of channels (or the number of fins), while the GAAFET10b may achieve the transition of the active pattern by adjusting the first width W1 of the nano-plate, and thus, the GAAFET10b may support devices having more various characteristics than the FinFET 10 a.

As device dimensions decrease to achieve high integration, the difficulty of semiconductor processing may increase and the transition of active patterns may be limited by the semiconductor processing. For example, when large transitions of the active pattern occur, such as when designing structures with greatly reduced or greatly increased widths of the nanoplatelets in an integrated circuit, the semiconductor process may not readily implement the designed structures. Accordingly, when the transition of the active pattern is large, the yield of the integrated circuit may be reduced, or the area of the integrated circuit may be increased due to a space (e.g., diffusion break) for the transition of the active pattern.

As described below with reference to the drawings, an integrated circuit may be designed in consideration of a semiconductor process, thereby reducing time and cost required to design the integrated circuit and improving yield of the integrated circuit. Furthermore, the integrated circuit can have high reliability, and accordingly, the reliability of applications including the integrated circuit can be improved. In addition, an integrated circuit with high reliability can be easily designed, thereby significantly shortening the time-to-market of the integrated circuit. Hereinafter, GAAFET (i.e., MBCFET) will be mainly described as an example of a device, but it is noted that embodiments of the inventive concept are not limited thereto. Further, although the transition of the active pattern by changing the width of the nano-sheets will be mainly described, it is noted that the transition of the active pattern may occur by changing the number of nano-sheets, as described above.

Fig. 2A and 2B are plan views showing a layout of an integrated circuit according to example embodiments. Hereinafter, redundant descriptions of fig. 2A and 2B will be omitted.

Referring to fig. 2A, an integrated circuit may include a plurality of standard cells. A standard cell is a layout unit included in an integrated circuit, and may be simply referred to as a cell. The cell may comprise a transistor and may be designed to perform a predefined function. In an integrated circuit, cells may be aligned and arranged along rows. For example, in fig. 2A, the first and second rows R1 and R2 may extend in the X-axis direction, and the cells may be arranged in the first and/or second rows R1 and R2. The cells arranged in one row may be referred to as single-height cells, and the cells arranged in two or more consecutive rows may be referred to as multi-height cells. The single height units arranged in the first row R1 may have a first height H1 in the Y-axis direction, the single height units arranged in the second row R2 may have a second height H2 in the Y-axis direction, and the multi-height units continuously arranged in the first and second rows R1 and R2 may have a height corresponding to the sum of the heights H1 and H2 in the Y-axis direction.

In some embodiments, the first height H1 of the first row R1 and the second height H2 of the second row R2 may be the same or different from each other. For example, as shown in fig. 2A, the second height H2 may be greater than the first height H1 (H2 > H1). Rows having different heights may be arranged in various ways. For example, rows having a first height H1 and rows having a second height H2 may be alternately arranged in a ratio of 1:1, 2:2, 4:4, etc.

A pattern for supplying power to the cells may be arranged on the boundaries of the rows. For example, as shown in fig. 2A, the first to third metal patterns M21 to M23 may extend in the X-axis direction on the boundary of the first and second rows R1 and R2. The negative power supply voltage VSS may be applied to the first and third metal patterns M21 and M23, and an n-channel field-effect transistor (NFET) may be disposed adjacent to the first and third metal patterns M21 and M23. In addition, a positive power supply voltage VDD may be applied to the second metal pattern M22, and a p-channel field effect transistor (PFET) may be disposed adjacent to the second metal pattern M22.

The integrated circuit may include an active pattern extending in an X-axis direction, and the cell may include a transistor formed of the active pattern. For example, as shown in fig. 2A, the integrated circuit 20a may include a plurality of first active patterns a11 to a13 overlapping each other in the X-axis direction and a plurality of second active patterns a21 to a23 overlapping each other in the X-axis direction in the first row R1. Further, the integrated circuit 20a may include a plurality of third active patterns a31 to a33 overlapping each other in the X-axis direction and a plurality of fourth active patterns a41 to a43 overlapping each other in the X-axis direction in the second row R2. As shown in fig. 2A, the plurality of first active patterns a11 to a13 and the plurality of fourth active patterns a41 to a43 adjacent to the first metal pattern M21 and the third metal pattern M23 to which the negative power supply voltage VSS is applied may form an n-channel field effect transistor (NFET), and the plurality of second active patterns a21 to a23 and the plurality of second active patterns a31 to a33 adjacent to the second metal pattern M22 to which the positive power supply voltage VDD is applied may form a p-channel field effect transistor (PFET).

In some embodiments, the transition of the active pattern may be limited to a predefined size. For example, as shown in fig. 2A, transition of the active patterns in the plurality of first active patterns a11 to a13 in the first row R1 may be limited to the first offset OS1. Accordingly, the difference between the widths of the first active patterns a11 and a12 adjacent to each other may correspond to the first offset amount OS1, and the difference between the widths of the first active patterns a12 and a13 adjacent to each other may also correspond to the first offset amount OS1. Further, the transition of the active patterns in the plurality of second active patterns a21 to a23 in the first row R1 may be limited to the second offset OS2. In some embodiments, the first offset OS1 and the second offset OS2 may be the same. Similarly, the transition of the active patterns in the plurality of third active patterns a31 to a33 in the second row R2 may be limited to the third offset OS3, and the transition of the active patterns in the plurality of fourth active patterns a41 to a43 in the second row R2 may be limited to the fourth offset OS4. In some embodiments, the third offset OS3 and the fourth offset OS4 may be the same. The first to fourth offsets OS1 to OS4 may be defined by a semiconductor process for manufacturing the integrated circuit 20a, and thus, errors caused by excessive transition of the active pattern in the integrated circuit 20a may be eliminated.

In some embodiments, the width of the active patterns in the first row R1 and the width of the active patterns in the second row R2 may be different. For example, the maximum width (or minimum width) of the plurality of first active patterns a11 to a13 in the first row R1 may be different from the maximum width (or minimum width) of the plurality of fourth active patterns a41 to a43 in the second row R2. Further, the maximum width (or minimum width) of the plurality of second active patterns a21 to a23 in the first row R1 may be different from the maximum width (or minimum width) of the plurality of third active patterns a31 to a33 in the second row R2. The maximum width of the active pattern may refer to the widest width of the active pattern. Accordingly, the maximum width of the first active patterns a11 to a13 may be the width of the first active pattern a13, and the maximum width of the second active patterns a21 to a23 may be the width of the second active pattern a 23. Further, the minimum width of the active pattern may refer to the narrowest width of the active pattern. Accordingly, the minimum width of the first active patterns a11 to a13 may be the width of the first active pattern a11, and the minimum width of the second active patterns a21 to a23 may be the width of the second active pattern a 21.

Referring to fig. 2B, the active pattern in the integrated circuit 20B may have one of two widths. For example, as shown in fig. 2B, each of the plurality of first active patterns a11 to a13 overlapping each other in the X-axis direction in the first row R1 may have one of two widths W11 and W12 differing by the first offset amount OS 1. Further, each of the plurality of second active patterns a21 to a23 overlapping each other in the X-axis direction in the first row R1 may have one of two widths W21 and W22 differing by the second offset amount OS 2. In some embodiments, the first offset OS1 and the second offset OS2 may be the same. In some embodiments, widths W11 and W12 of the plurality of first active patterns a11 to a13 may be the same as widths W21 and W22 of the plurality of second active patterns a21 to a23, respectively. Similarly, in the second row, each of the plurality of third active patterns a31 to a33 overlapping each other in the X-axis direction may have one of two widths W31 and W32 differing by the third offset amount OS3, and each of the plurality of fourth active patterns a41 to a43 overlapping each other in the X-axis direction may have one of two widths W41 and W42 differing by the fourth offset amount OS 4. In some embodiments, the third offset OS3 and the fourth offset OS4 may be the same. In some embodiments, widths W31 and W32 of the plurality of third active patterns a31 to a33 may be the same as widths W41 and W42 of the plurality of fourth active patterns a41 to a43, respectively.

Fig. 3A and 3B are plan views illustrating a layout of an integrated circuit according to example embodiments. In some embodiments, the cells may be terminated by a Diffusion Break (Diffusion Break), and the transition of the active pattern may occur in the Diffusion Break. In some embodiments, the active pattern in the cell may have a constant width. For example, as shown in fig. 3A and 3B, the active pattern may have a constant width within a cell, and a different width in different cells. Hereinafter, redundant descriptions of fig. 3A and 3B will be omitted.

Referring to fig. 3A, the integrated circuit 30a may include a first cell C31a and a second cell C32a. The first cell C31a may include active patterns a11 and a21 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The second cell C32a may include active patterns a12 and a22 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The gate electrode may extend in the Y-axis direction at a contact multi-pitch (CPP: contacted Poly Pitch), and in fig. 3A, each of the first cell C31a and the second cell C32a may have a length corresponding to three CPPs in the X-axis direction.

Instead of the gate electrode, a diffusion break may be formed at a boundary of the first cell C31a and the second cell C32a parallel to the Y axis, and the first cell C31a and the second cell C32a disposed adjacent to each other may share one diffusion break. As shown in fig. 3A, the diffusion break disposed at the position of the gate electrode may be referred to as a Single Diffusion Break (SDB) or a dummy gate. In some embodiments, unlike the illustration in fig. 3A, the cells may have boundaries extending in the X-axis direction between gate electrodes, and diffusion breaks formed between gates of adjacent cells may be referred to as Double Diffusion Breaks (DDBs).

As shown in fig. 3A, the active pattern a11 for PFET in the first cell C31a may have a first width W1, and the active pattern a12 for PFET in the second cell C32a may have a second width W2. As described above with reference to fig. 2A and 2B, the second width W2 may be greater than the first width W1 by the first offset OS1. The width of the active pattern may be changed at the diffusion break between the first cell C31a and the second cell C32a, and the active pattern may be removed from the diffusion break. The active patterns a11 and a12 may be spaced apart from each other in the X-axis direction, and no active pattern may be provided between the active patterns a11 and a12, as shown in fig. 3A. The active pattern a11 and the active pattern a12 may be directly adjacent to each other. The term "immediately adjacent" as used herein includes configurations in which: the two "elements" (e.g., active patterns a11 and a 12) that are directly adjacent to each other are positioned such that no other similar element is located between the two elements that are directly adjacent to each other.

Referring to fig. 3B, the integrated circuit 30B may include first to fourth cells C31B to C34B. The first cell C31b may include active patterns a11 and a21 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The second cell C32b may include active patterns a12 and a22 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. As shown in fig. 3B, the active pattern a11 of the first cell C31B and the active pattern a12 of the second cell C32B may have a first width W1 and may be spaced apart from each other by SDB extending in the Y-axis direction between the first cell C31B and the second cell C32B.

The fourth cell C34b may include active patterns a13 and a23 extending in the X-axis direction and a gate electrode extending in the Y-axis direction. The second width W2 of the active pattern a13 of the fourth cell C34b may be greater than the first width W1 of the active pattern a12 of the second cell C32b by a first offset OS1. Unlike the integrated circuit 30a of fig. 3A, the transition of the active pattern in the integrated circuit 30B of fig. 3B may require the diffusion break to extend in the Y-axis direction for CPP or more. Thus, the integrated circuit 30b may include the third cell C33b between the second cell C32b and the fourth cell C34b, and the active pattern may be removed from the third cell C33 b. In some embodiments, the third cell C33b may not include any active pattern. Herein, the units (e.g., the first unit C31b, the second unit C32b, and the fourth unit C34 b) including the transistor (or the active pattern) and designed to perform a function through the transistor may be referred to as functional units. Further, as shown in the third cell C33b, a cell for transition of an active pattern interposed between functional cells may be referred to as a filler cell. In some embodiments, unlike the illustration in fig. 3B, the filler unit may correspond to one CPP (1 CPP) or have a length in the X-axis direction of more than two CPPs (2 CPPs).

Fig. 4 is a plan view showing a layout of cells according to an example embodiment. In some embodiments, the transition of the active pattern may occur in the cell.

Referring to fig. 4, the cell C40 may include active patterns a11 and a12 overlapping each other in the X-axis direction and active patterns a21 and a22 overlapping each other in the X-axis direction. The width W12 of the active pattern a12 may be greater than the width W11 of the active pattern a11 by a first offset OS1, and the width W22 of the active pattern a22 may be greater than the width W21 of the active pattern a21 by a second offset OS2. The first offset OS1 and the second offset OS2 may be defined by a semiconductor process, and the cell C40 may be designed to include transition of an active pattern corresponding to the first offset OS1 or the second offset OS2. Thus, the cell C40 may be designed with optimized performance and efficiency, and errors caused by the cell C40 may be reduced or prevented.

Fig. 5 is a plan view showing a layout of an integrated circuit 50 according to an example embodiment. As described above with reference to fig. 2A and 2B, the integrated circuit 50 may include a plurality of cells, and the plurality of cells may be arranged in rows (e.g., the first row R1 and/or the second row R2) extending in the X-axis direction. As described above with reference to fig. 2A and 2B, the first height H1 of the first row R1 and the second height H2 of the second row R2 may be the same as or different from each other.

In some embodiments, the width of the active pattern for NFETs and the width of the active pattern for PFETs in a cell may be different from each other. For example, as shown in fig. 5, an active pattern a11 for an NFET and an active pattern a12 for a PFET may extend in the X-axis direction in the first row R1. The width W11 of the active pattern a11 for the NFET may be smaller than the width W12 of the active pattern a12 for the PFET (W11 < W12). In some embodiments, unlike the illustration in fig. 5, the width W11 of the active pattern a11 for NFETs may be greater than the width W12 of the active pattern a12 for PFETs (W11 > W12). Further, as shown in fig. 5, an active pattern a21 for PFET and an active pattern a22 for NFET may extend in the X-axis direction in the second row R2. The width W21 of the active pattern a21 for PFETs may be greater than the width W22 of the active pattern a22 for NFETs (W21 > W22). In some embodiments, unlike the illustration in fig. 5, the width W21 of the active pattern a21 for PFETs may be smaller than the width W22 of the active pattern a22 for NFETs (W21 < W22).

Fig. 6A to 6F are plan views showing a layout of an integrated circuit according to an example embodiment. Fig. 6A to 6F are plan views illustrating examples in which active patterns having different widths are aligned in various ways. In fig. 6A to 6F, each of the integrated circuits 60a to 60F may include first to third metal patterns M61 to M63 extending in the X-axis direction on the boundary of the first and second rows R1 and R2. The negative power supply voltage VSS may be applied to the first metal pattern M61 and the third metal pattern M63, and the positive power supply voltage VDD may be applied to the second metal pattern M62.

Referring to fig. 6A, the integrated circuit 60a may include an active pattern extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60a may include a plurality of first active patterns a11 to a14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns a21 to a24 overlapping each other in the X-axis direction. In some embodiments, the transition of the active pattern may support two offsets. For example, the offset between the adjacent active patterns a11 and a12 may be the same as the offset between the adjacent active patterns a12 and a13, and may be different from the offset between the adjacent active patterns a13 and a 14.

In some embodiments, the active pattern may have a boundary overlapping a line extending in the X-axis direction. For example, as shown in fig. 6A, the plurality of first active patterns a11 to a14 may have boundaries overlapping with the lines X1-X1 'extending in the X-axis direction, and the plurality of second active patterns a21 to a24 may have boundaries overlapping with the lines X2-X2' extending in the X-axis direction. As shown in fig. 6A, the lines X1-X1 'and X2-X2' may be adjacent to the boundary of the first row R1, and thus, the plurality of first active patterns a11 to a14 and the plurality of second active patterns a21 to a24 may be disposed between the lines X1-X1 'and X2-X2'. The plurality of first active patterns a11 to a14 may include respective side surfaces (also referred to as first outer side surfaces) aligned in the X-axis direction, and the plurality of second active patterns a21 to a24 may include respective side surfaces (also referred to as second outer side surfaces) aligned in the X-axis direction, as shown in fig. 6A. The plurality of first active patterns a11 to a14 may further include a first inner side surface facing the plurality of second active patterns a21 to a24, and the plurality of second active patterns a21 to a24 may further include a second inner side surface facing the plurality of first active patterns a11 to a 14.

Referring to fig. 6B, the integrated circuit 60B may include an active pattern extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60b may include a plurality of first active patterns a11 to a14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns a21 to a24 overlapping each other in the X-axis direction. In some embodiments, the transition of the active pattern may support two offsets. For example, the offset between the adjacent active patterns a11 and a12 may be the same as the offset between the adjacent active patterns a12 and a13, and may be different from the offset between the adjacent active patterns a13 and a 14.

In some embodiments, the active pattern may have a boundary overlapping a line extending in the X-axis direction. For example, as shown in fig. 6B, the plurality of first active patterns a11 to a14 may have boundaries overlapping with the lines X1-X1 'extending in the X-axis direction, and the plurality of second active patterns a21 to a24 may have boundaries overlapping with the lines X2-X2' extending in the X-axis direction. As shown in fig. 6B, the lines X1-X1 'and X2-X2' may be adjacent to the center of the first row R1, and thus, the lines X1-X1 'and X2-X2' may extend in the X-axis direction between the plurality of first active patterns a11 to a14 and the plurality of second active patterns a21 to a24. The plurality of first active patterns a11 to a14 may include first inner side surfaces aligned in the X-axis direction and facing the plurality of second active patterns a21 to a24, and the plurality of second active patterns a21 to a24 may include second inner side surfaces aligned in the X-axis direction and facing the plurality of first active patterns a11 to a14, as shown in fig. 6B.

Referring to fig. 6C, the integrated circuit 60C may include an active pattern extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60c may include a plurality of first active patterns a11 to a14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns a21 to a24 overlapping each other in the X-axis direction. In some embodiments, the transition of the active pattern may support two offsets. For example, the offset between the adjacent active patterns a11 and a12 may be the same as the offset between the adjacent active patterns a12 and a13, and may be different from the offset between the adjacent active patterns a13 and a 14.

In some embodiments, the active pattern may have a boundary overlapping a line extending in the X-axis direction. For example, as shown in fig. 6C, the plurality of first active patterns a11 to a14 may have boundaries overlapping with the lines X1-X1 'extending in the X-axis direction, and the plurality of second active patterns a21 to a24 may have boundaries overlapping with the lines X2-X2' extending in the X-axis direction. As shown in FIG. 6C, the line X1-X1 'may be adjacent to the boundary of the first row R1, while the line X2-X2' may be adjacent to the center of the first row R1. Accordingly, the plurality of first active patterns a11 to a14 may be disposed between the lines X1-X1' and X2-X2', and the lines X2-X2' may extend in the X-axis direction between the plurality of first active patterns a11 to a14 and the plurality of second active patterns a21 to a24. The plurality of first active patterns a11 to a14 may include first outer side surfaces aligned in the X-axis direction and may include first inner side surfaces facing the plurality of second active patterns a21 to a24, and the plurality of second active patterns a21 to a24 may include second inner side surfaces aligned in the X-axis direction and facing the plurality of first active patterns a11 to a14, as shown in fig. 6C.

Referring to fig. 6D, the integrated circuit 60D may include an active pattern extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60d may include a plurality of first active patterns a11 to a14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns a21 to a24 overlapping each other in the X-axis direction. In some embodiments, the transition of the active pattern may support two offsets. For example, the offset between the adjacent active patterns a11 and a12 may be the same as the offset between the adjacent active patterns a12 and a13, and may be different from the offset between the adjacent active patterns a13 and a 14.

In some embodiments, the center of each active pattern (e.g., a center point in the Y-axis direction) may be aligned to overlap with a line extending in the X-axis direction. For example, as shown in fig. 6D, the center of each of the first active patterns a11 to a14 may be aligned to overlap with a line X1-X1 'extending in the X-axis direction, and the center of each of the plurality of second active patterns a21 to a24 may be aligned to overlap with a line X2-X2' extending in the X-axis direction. The first active patterns a11 to a14 may include respective center points in the Y-axis direction, and the center points of the first active patterns a11 to a14 are aligned in the X-axis direction. The second active patterns a21 to a24 may include respective center points in the Y-axis direction, and the center points of the second active patterns a21 to a24 are aligned in the X-axis direction, as shown in fig. 6D.

Referring to fig. 6E, the integrated circuit 60E may include an active pattern extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60e may include a plurality of first active patterns a11 to a14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns a21 to a24 overlapping each other in the X-axis direction. Further, the integrated circuit 60e may include a plurality of third active patterns a31 to a34 overlapping each other in the X-axis direction in the second row R2. In some embodiments, the transition of the active pattern may support two offsets. For example, the offset between the adjacent active patterns a11 and a12 may be the same as the offset between the adjacent active patterns a12 and a13, and may be different from the offset between the adjacent active patterns a13 and a 14.

In some embodiments, the active patterns may be arranged and may have a width to have a constant distance from adjacent active patterns in the Y-axis direction. For example, as shown in fig. 6E, in the first row R1, the plurality of first active patterns a11 to a14 may be spaced apart from the plurality of corresponding second active patterns a21 to a24, respectively, by a first distance D1. Further, the plurality of second active patterns a21 to a24 in the first row may be spaced apart from the plurality of corresponding third active patterns a31 to a34, respectively, by a second distance D2. The first distance D1 and the second distance D2 may be the same as each other or different from each other.

Referring to fig. 6F, the integrated circuit 60F may include an active pattern extending in the X-axis direction in the first and second rows R1 and R2. For example, in the first row R1, the integrated circuit 60f may include a plurality of first active patterns a11 to a14 overlapping each other in the X-axis direction, and may include a plurality of second active patterns a21 to a24 overlapping each other in the X-axis direction. Further, the integrated circuit 60f may include a plurality of third active patterns a31 to a34 overlapping each other in the X-axis direction in the second row R2. In some embodiments, the transition of the active pattern may support two offsets. For example, the offset between the adjacent active patterns a11 and a12 may be the same as the offset between the adjacent active patterns a12 and a13, and may be different from the offset between the adjacent active patterns a13 and a 14.

In some embodiments, the center of each active pattern (e.g., a center point in the Y-axis direction) may be aligned to overlap with a line extending in the X-axis direction. For example, as shown in fig. 6F, the center of each of the first active patterns a11 to a14 may be aligned to overlap a line X1-X1' extending in the X-axis direction, the center of each of the plurality of second active patterns a21 to a24 may be aligned to overlap a line X2-X2' extending in the X-axis direction, and the center of each of the plurality of third active patterns a31 to a34 may be aligned to overlap a line X3-X3' extending in the X-axis direction.

In some embodiments, each active pattern may have a width to have a constant distance from an adjacent active pattern in the Y-axis direction. For example, as shown in fig. 6F, in the first row R1, the plurality of first active patterns a11 to a14 may be spaced apart from the plurality of corresponding second active patterns a21 to a24, respectively, by a first distance D1. Further, the plurality of second active patterns a21 to a24 in the first row R1 may be spaced apart from the plurality of corresponding third active patterns a31 to a34, respectively, by a second distance D2. The first distance D1 and the second distance D2 may be the same as each other or different from each other.

Fig. 7 is a flowchart illustrating a method of manufacturing an Integrated Circuit (IC) according to an example embodiment. For example, the flow chart of fig. 7 shows an example of a method of manufacturing an Integrated Circuit (IC) including standard cells. As shown in fig. 7, a method of manufacturing an Integrated Circuit (IC) may include a plurality of operations S10, S30, S50, S70, and S90.

The cell library (or standard cell library) D12 may include information about standard cells, such as information about functions, characteristics, layout, and the like. In some embodiments, the cell library D12 may define standard cells, each standard cell including an active pattern of different widths. In some embodiments, the cell library D12 may define standard cells including active patterns whose widths are changed. In some embodiments, the cell library D12 may define filler cells inserted for transitions of the active pattern. In some embodiments, cell library D12 may define standard cells that include active patterns for PFETs and active patterns for NFETs, respectively, with different widths.

Design rule D14 may include requirements to be complied with by the layout of the integrated circuit IC. For example, design rule D14 may include requirements for spacing between patterns of the same layer, minimum width of the patterns, routing direction of the wiring layers, and so forth. In some embodiments, design rule D14 may define a minimum separation distance in the same track of the routing layer.

In operation S10, a logic synthesis operation of generating netlist D13 from Register Transfer Level (RTL) data D11 may be performed. For example, a semiconductor design tool (e.g., a logic synthesis tool) may perform logic synthesis on RTL data D11 with reference to cell library D12 and generate netlist D13 comprising a bit stream or netlist written as Hardware Description Language (HDL), such as VHSIC Hardware Description Language (VHDL) and Verilog. Netlist D13 may correspond to inputs for placement and routing, as will be described below.

In operation S30, units may be arranged. For example, a semiconductor design tool (e.g., a P & R tool) may refer to cell library D12 and design rule D14 to place standard cells used in netlist D13. In some embodiments, design rule D14 may define the transitions of the active pattern allowed in a row. For example, the design rule D14 may define at least one offset allowed in a row, and the adjacent active patterns may have the same width, or the widths of the adjacent active patterns may differ by at least one offset defined by the design rule D14. The semiconductor design tool may select standard cells including active patterns having an appropriate width from the cell library D12 in consideration of adjacent standard cells, and may arrange the selected standard cells.

In operation S50, pins of the unit may be routed. For example, the semiconductor design tool may generate an interconnect that electrically connects the output pins and the input pins of the arranged standard cells, and may generate layout data D15 that defines the arranged standard cells and the generated interconnect. Each interconnect may include a pattern of vias and/or routing layers of the via layer. Layout data D15 may have a format such as graphic design System-II (GDSII) and may include geometric information for the cells and interconnects. The semiconductor design tool may reference design rule D14 while routing the pins of the unit. Layout data D15 may correspond to the output of the arrangement and routing. Operation S50 may be referred to as a method of designing an integrated circuit alone, or operations S30 and S50 may be collectively referred to as a method of designing an integrated circuit.

In operation S70, an operation of manufacturing a mask may be performed. For example, optical Proximity Correction (OPC) for correcting distortion (for example, refraction due to light characteristics in photolithography) may be applied to the layout data D15. Based on the OPC-applied data, a pattern on the mask may be defined to form a pattern arranged on the plurality of layers, and at least one mask (or photomask) for forming a pattern of each of the plurality of layers may be manufactured. In some embodiments, the layout of an Integrated Circuit (IC) may be changed limitedly in operation S70, and the limited change to the integrated circuit IC in operation S70 may be referred to as design supervision as a post-process for optimizing the structure of the Integrated Circuit (IC).

In operation S90, an operation of manufacturing an Integrated Circuit (IC) may be performed. For example, an Integrated Circuit (IC) may be manufactured by patterning the plurality of layers using at least one mask manufactured in operation S70. The front end of line (FEOL) may include, for example, the following operations: planarizing and cleaning the wafer; forming a groove; forming a well; forming a gate electrode; and forming a source and a drain. With FEOL, individual devices, such as transistors, capacitors, resistors, etc., can be formed on a substrate. Further, the back end of line (BEOL) may include, for example, the following operations: siliciding the gate region, the source region and the drain region; adding a dielectric; performing planarization; forming holes and adding a metal layer; forming a via hole; a passivation layer, etc. is formed. Individual devices such as transistors, capacitors, resistors, etc. may be interconnected by BEOL. In some embodiments, a medium process (MOL) may be performed between the FEOL and the BEOL, and contacts may be formed on the respective devices. Integrated Circuits (ICs) may then be packaged in semiconductor packages and used as components for various applications.

Fig. 8 is a block diagram illustrating a system on a chip (SoC) 80 in accordance with an example embodiment. The system on a chip 80 is a semiconductor device and may include an integrated circuit according to example embodiments. The system on chip 80 implements complex blocks (e.g., intellectual Property (IP)) that perform various functions in one chip, and the system on chip 80 may be designed by a method of designing an integrated circuit according to example embodiments, and thus, the system on chip 80 may provide high yield and reliability and have good (e.g., optimal or highest) performance and efficiency. Referring to fig. 8, the system on chip 80 may include a modem 82, a display controller 83, a memory 84, an external memory controller 85, a Central Processing Unit (CPU) 86, a transaction unit 87, a Power Management IC (PMIC) 88, and a Graphics Processing Unit (GPU) 89. The various functional blocks of the system on chip 80 may communicate with each other via a system bus 81.

The CPU 86, which is capable of controlling the operation of the system on chip 80 at the highest level, may control the operation of the other functional blocks 82 to 85 and 87 to 89. The modem 82 may demodulate a signal received from the outside of the system on chip 80 or modulate a signal generated inside the system on chip 80 to transmit the signal to the outside. The external memory controller 85 may control an operation of transmitting and receiving data from an external memory device connected to the system on chip 80. For example, programs and/or data stored in the external storage device may be provided to the CPU 86 or GPU 89 under the control of the external memory controller 85. GPU 89 may execute program instructions related to graphics processing. GPU 89 may receive graphics data through external memory controller 85 or may send graphics data processed by GPU 89 to the outside of system-on-chip 80 through external memory controller 85. The transaction unit 87 may monitor data transactions of each functional block, and the PMIC 88 may control power supplied to each functional block under the control of the transaction unit 87. The display controller 83 may transmit data generated inside the system on chip 80 to a display (or display device) through controlling the display outside the system on chip 80. The memory 84 may include non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), or may include volatile memory (e.g., dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), etc.).

Fig. 9 is a block diagram illustrating a computing system 90 including memory for storing programs in accordance with an example embodiment. A method of designing an integrated circuit according to example embodiments, such as at least some of the operations of the flowcharts described above, may be performed in a computing system (or computer) 90.

The computing system 90 may be a fixed computing system (e.g., a desktop computer, workstation, server, etc.), or may be a portable computing system (e.g., a laptop computer, etc.). As shown in fig. 9, computing system 90 may include a processor 91, an input/output device 92, a network interface 93, random Access Memory (RAM) 94, read Only Memory (ROM) 95, and a storage device 96. The processor 91, the input/output device 92, the network interface 93, the RAM 94, the ROM 95, and the storage device 96 may be connected to the bus 97, and may communicate with each other through the bus 97.

The processor 91 may be referred to as a processing unit and may include at least one core, such as a microprocessor, an Application Processor (AP), a Digital Signal Processor (DSP), and a graphics processing unit, that may execute any set of instructions (e.g., intel architecture-32 (IA-32), 64-bit extension IA-32, x86-64, powerPC, sparc, MIPS, ARM, IA-64, etc.). For example, the processor 91 may access a memory, i.e., the RAM 94 or the ROM 95, through the bus 97, and may execute instructions stored in the RAM 94 or the ROM 95.

RAM 94 may store a program 941, or at least a portion thereof, of a method of designing an integrated circuit according to example embodiments, and program 941 may enable processor 91 to perform at least some operations included in the method of designing an integrated circuit, for example, the method of fig. 7. That is, the program 941 may include a plurality of instructions executable by the processor 91, and the plurality of instructions included in the program 941 may enable the processor 91 to perform at least some operations such as those included in the flowcharts described above.

The storage device 96 may not lose the stored data even if the power to the computing system 90 is cut off. For example, the storage device 96 may include a non-volatile storage device or may include storage media such as magnetic tape, optical disk, and magnetic disk. Further, the storage device 96 may be removable from the computing system 90. The storage device 96 may store the program 941 according to example embodiments, and the program 941 or at least a portion thereof may be loaded from the storage device 96 into the RAM 94 before the program 941 is executed by the processor 91. Alternatively, the storage device 96 may store a file written in a program language, and the program 941 or at least a part thereof generated from the file by a compiler or the like may be loaded into the RAM 94. In addition, as shown in fig. 9, the storage device 96 may store a Database (DB) 961, and the database 961 may include information required to design an integrated circuit, such as information about the designed block, the cell library D1 2 of fig. 7, and/or the design rule D14.

The storage device 96 may also store data to be processed by the processor 91 or data processed by the processor 91. That is, the processor 91 may generate data by processing the data stored in the storage device 96 according to the program 941, and may enable the storage device 96 to store the generated data. For example, storage device 96 may store RTL data D11, netlist D13, and/or layout data D15 of FIG. 7.

The input/output devices 92 may include input devices such as keyboards and pointing devices, and may include output devices such as display devices and printers. For example, a user may trigger processor 91 to execute program 941 via input/output device 92, may input RTL data D11 and/or netlist D13 of FIG. 7, and may examine layout data D15 of FIG. 7.

Network interface 93 may provide access to a network external to computing system 90. For example, the network may include a plurality of computing systems and communication links, and the communication links may include wired links, optical links, wireless links, or any other form of link.

It will be understood that, although the terms "first," "second," and other terms may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the teachings of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the inventive concept. The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present inventive concepts.

Claims (20)

1. An integrated circuit, comprising:

a first active pattern group extending in a first direction in a first row and including a plurality of first active patterns overlapping each other in the first direction, the first row extending in the first direction; and

a plurality of gate electrodes extending in a second direction perpendicular to the first direction in the first row,

wherein the plurality of first active patterns includes any two first active patterns adjacent to each other in the first direction, the two first active patterns have a first width and a second width in the second direction, respectively, and the first width and the second width are the same or differ by a first offset amount or a second offset amount.

2. The integrated circuit of claim 1, wherein the plurality of gate electrodes extend in the second direction and have a first pitch,

the first width and the second width are different, and

the two first active patterns are spaced apart from each other in the first direction by at least the first pitch.

3. The integrated circuit of claim 2, wherein there is no active pattern between the two first active patterns.

4. The integrated circuit of claim 1, wherein each of the plurality of first active patterns has the first width or the second width that is wider than the first width by the first offset.

5. The integrated circuit of claim 1, wherein the integrated circuit further comprises a second active pattern group extending along the first direction in a second row adjacent to the first row, the second active pattern group comprising a plurality of second active patterns that overlap each other in the first direction, wherein the first row and the second row have different widths in the second direction.

6. The integrated circuit of claim 5, wherein the plurality of second active patterns comprises any two second active patterns adjacent to each other in the first direction and having the same width in the second direction or having widths in the second direction that differ by a third offset or a fourth offset, and the third offset is different from the first offset and the second offset.

7. The integrated circuit of claim 5, wherein a widest width of the plurality of first active patterns in the second direction is different from a widest width of the plurality of second active patterns in the second direction.

8. The integrated circuit of claim 5, wherein a narrowest width of the plurality of first active patterns in the second direction is different from a narrowest width of the plurality of second active patterns in the second direction.

9. The integrated circuit of claim 1, further comprising: a third active pattern group extending in the first direction in the first row and including a plurality of third active patterns overlapping each other in the first direction,

wherein the plurality of third active patterns includes any two third active patterns adjacent to each other in the first direction and having the same width in the second direction or having widths different from each other by the first offset amount or the second offset amount in the second direction.

10. The integrated circuit of claim 9, wherein the plurality of third active patterns includes respective side surfaces aligned along the first direction.

11. The integrated circuit of claim 10, wherein the respective side surfaces of the plurality of first active patterns are first outside surfaces, and the plurality of first active patterns further comprise respective first inside surfaces opposite the first outside surfaces,

The respective side surfaces of the plurality of third active patterns are third outside surfaces, and the plurality of third active patterns further include respective third inside surfaces opposite the third outside surfaces, and

the first inner side surface faces the third inner side surface.

12. The integrated circuit of claim 10, wherein respective side surfaces of the plurality of first active patterns and respective side surfaces of the plurality of third active patterns are spaced apart from each other and face each other in the second direction.

13. The integrated circuit of claim 10, wherein respective side surfaces of the plurality of third active patterns face the plurality of first active patterns.

14. The integrated circuit of claim 9, wherein each first active pattern of the plurality of first active patterns is spaced apart from a corresponding third active pattern of the plurality of third active patterns in the second direction by a first distance.

15. The integrated circuit of claim 9, wherein the plurality of first active patterns have respective center points aligned along the first direction, and

the plurality of third active patterns have respective center points aligned along the first direction.

16. The integrated circuit of claim 9, wherein one of the plurality of first active patterns and one of the plurality of third active patterns face each other and have different widths in the second direction.

17. The integrated circuit of claim 1, wherein each of the plurality of first active patterns comprises at least one nanoplatelet that overlaps at least one of the plurality of gate electrodes in the second direction and a third direction, the third direction being perpendicular to the first direction and the second direction.

18. An integrated circuit includes a plurality of first functional units arranged in a first row extending in a first direction,

wherein each of the plurality of first functional units comprises:

a first active pattern extending along the first direction; and

at least one first gate electrode extending in a second direction perpendicular to the first direction,

wherein the plurality of first functional units includes two first functional units adjacent to each other, the two first functional units include two first active patterns, respectively, and

the two first active patterns overlap each other in the first direction, have respective widths in the second direction, and have the same width or differ by a first offset amount or a second offset amount.

19. The integrated circuit of claim 18, wherein the widths of the two first active patterns are different, and

the integrated circuit further comprises a filler unit located between the two first functional units.

20. An integrated circuit, comprising:

a plurality of units;

a first pattern and a second pattern extending in a first direction, adjacent to each other, and configured to supply power to a first cell of the plurality of cells;

a plurality of first active patterns extending in the first direction between the first pattern and the second pattern and overlapping each other in the first direction; and

a plurality of first gate electrodes extending between the first pattern and the second pattern in a second direction perpendicular to the first direction,

wherein the plurality of first active patterns includes any two first active patterns adjacent to each other in the first direction, the two first active patterns having respective widths that are the same, or differ by a first offset or a second offset, in the second direction.