JPH03225941A - Designing method for layout - Google Patents

Abstract

PURPOSE:To concurrently process disposing and wiring steps in designing a layout by dividing a chip region into several small areas, concurrently disposing and wiring in detail of circuit elements from left to right columns of the small regions, and completing the layout of an entire chip. CONSTITUTION:The chip region of an integrated circuit is formed of N pieces of cell columns in which circuit elements are disposed in a stripe state. (M-1) pieces of vertical cutting lines 13v (k)k=1-(M-1) and (N-1) pieces of horizontal cutting lines h(I), I=1-(N-1) are written on the region to divide the region into rectangular regions called 'small regions of (MXN) pieces. A window 10 is formed of the small regions g(i, j), j=1-N. Cell positions are corrected and wired concurrently while moving the window from the left end to the right end of the region. The positions and wirings of the cells are determined in the left region from the window, called 'a deterministic region 11'. The positions and wirings of the cells in the right region of the window are undetermined, called 'non-deterministic region 12'. The cell position in the non- deterministic region is corrected by the wiring result of the deterministic region, and the window is wired by the disposing result.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a layout design method in an integrated circuit.

(Prior Art) As a technology for layout design processing of integrated circuits, for example, for placement processing, M, A, Breyer “Min-Cu”
tP1acew+ent”, Journal of D
eSing Automation and Fault
-Tolerant Computinq, 0ctob
er 1977, pp. 343-362. As for wiring processing, Hasimoto, A., and J.

5tavens, “Wire routing by
primizing channel lassign
ment with this large apertu
res, “in Proc.

8th Design Automation Work
kshop 1971. pp, 155-163, etc. are known. In layout design in conventional technology,
These placement processing and wiring processing are clearly separated as independent methods. Although these processes are very good, in the processing flow of conventional technology, each process is independent, so the solutions to individual problems are simply accumulated, and even if each individual process does not produce the optimal solution. Even if it is calculated, it is not possible to obtain the optimal layout result in the final result.

For example, in an automatic integrated circuit design method using the standard cell method, after the placement of circuit elements is completed, the circuit elements are moved to secure an area through which wiring can pass. In some cases, this process destroys the optimal positional relationship of the circuit elements obtained by the placement process.

One of the objectives in layout design is to improve the degree of integration, but achieving this objective is different from simply arranging circuit elements so that the area of the chip area is minimized. Ultimately, it is necessary to configure wiring connecting circuit element terminals within the chip area, so the wiring between the terminals must be sufficiently considered in the placement process.

In the above-mentioned example, if it becomes necessary to move a circuit element during the wiring process, the placement process would normally have to be performed again. However, in a process flow in which each process is completely independent, it is difficult to repeatedly perform the two processes of placement and wiring. In the prior art, there is no explicit method of integrating processing with placement and wiring and repeatedly performing layout design.

(Problems to be Solved by the Invention) Various techniques have been proposed to improve the degree of integration of integrated circuits. However, in the layout design process flow according to the conventional technology, each process of placement, general wiring, and detailed wiring is performed independently.

In such a processing flow, even if each process is a method for deriving an optimal solution, it is difficult to obtain an optimal solution in the final layout result. An object of the present invention is to propose a layout design method in which processes that have conventionally been performed independently are performed in parallel.

[Structure of the invention]

(Means for Solving the Problem) The present invention has been made in view of the above circumstances, and includes 4- arranging circuit elements in a plurality of band-shaped areas within a chip area and determining wiring that satisfies connection requirements for circuit element terminals. When doing so, the chip area has a placement/routing determined area where the placement/routing of circuit elements has been determined and a placement/routing undetermined area where the placement/routing of circuit elements has not yet been determined. The rough layout of the circuit elements in the undetermined placement/routing area is corrected based on the area's placement/routing information, and multiple strip areas are created in the undetermined placement/routing area in a direction perpendicular to the longitudinal direction of the band. Determine a planned placement/routing area to cross, determine detailed placement of circuit elements within this planned placement/routing area, determine wiring between circuit elements within the planned placement/routing area, The present invention provides a layout design method characterized by registering and updating a planned placement/routing area for which detailed placement and wiring has been determined as a new placement/routing determination area.

(Operation) This invention divides a chip area into several small areas when designing a layout, and simultaneously advances the detailed placement and wiring of circuit elements from the left column to the right column of these small areas, and By completing the entire layerer 1~ process, parallel processing of placement and wiring processing in layout design becomes possible.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First, the terms used in this embodiment will be defined.

・Cell: Configure the target circuit by wiring between cells placed on a chip. Terminals that connect the wiring and cells are placed in the second wiring layer. Only the second layer of the wiring layer on the cell can be used, and includes regions where wiring can pass and regions where it cannot.

- Chip area: The chip area of an integrated circuit consists of N cell rows in which circuit elements are arranged in a strip.

・Small area 2 In the present invention, as shown in FIG. 4, (1) vertical cut lines 13V(k),
The chip area is divided into MXN rectangular areas by drawing k=1 to M-1 and (N-1) horizontal cut lines h(I), I=t to N-1. This rectangular area is represented by g(i,j), i=1 to M, j=1 to N, and is called a small area, where i is a column number and j is a row number. Here, N is the number of cell rows in the chip area.

The small area includes divided cell rows. The cell set that constitutes that cell row is represented by s (i, j). However, since cell positions change every moment due to the processing according to the present invention, the cell row referred to here does not mean that the detailed positions of individual cells have been determined. A detailed explanatory diagram of the small area is shown in FIG. The left cut line 17 of the small region g (itj) is v (i, j), and the right cut line 18 is v (
i, j+1), cut the upper cut line 19 by h (i, j+
1), and let the lower cut line 20 be h(i, j). r (itj) is a divided cell row included in the small region g (tej).

・Through wiring: Pass through h b+J) and s (i, j)
h(ilj+IL v (II
j) + v baj+ Wiring passing through 1). The relaxation of the through wiring passing through the small region g(IIj) is expressed as th(xt
j). The through wiring passes over the cell r (IIj).

-Through terminal: A terminal virtually provided in an area where the through wiring can pass over the cell for processing convenience, in order to allow the through wiring to pass over the cell. In the processing according to the present invention, when a through wiring passes over a cell, it connects to this virtual terminal once before passing through. A through terminal is always connected to only one through wiring, and is never connected to any other wiring.

-Through cell: A virtual cell for passing through wiring. To secure an area for passing through wiring,
Insert at any position in the cell row.

A through cell is a cell that has only one through terminal, and is not involved in the electrical configuration of the integrated circuit.

-Through capacity: Upper limit on the number of through wiring that can pass through the small area g(i, j). Cell set s(i.

j) is expressed as the sum of all terminals of the cell.

- Channel wiring: The total sum of wiring that passes through the small region g (i, j) other than through wiring and channel wiring that passes through g (i, j) is expressed as ch (x, j).

- Window, Determined Area, Undetermined Area Two In the method according to the present invention, a concept called a window is used in order to perform the wiring step and the cell position correction step 8- at the same time. The window is a rectangular area provided in the chip area perpendicular to the cell rows, and is composed of M small areas. In the example shown in FIG. 4, the window 10 is composed of small areas g (11j) + j=1 to N.

As shown in FIGS. 2 and 3, cell position correction and wiring are performed in parallel while moving this window from the left end to the right end of the chip area. In the area to the left of the window, cell positions and wiring are determined. This area is called a confirmed area 11. In the area to the right of the window, the cell position,
The wiring is in an undetermined state. This area is called an uncertain area 12. Cell positions in the uncertain area are corrected based on the wiring results in the confirmed area, and wiring within the window is performed based on the placement results.

FIG. 1 is a diagram showing a processing flow showing an embodiment of the present invention.

In the present invention, first, connection data (netlist) of cells constituting an integrated circuit and a specified number N of cell rows are inputted and initial data is created.

Next, an example of how to create this initial data (ω to ■) will be shown.

(2) Create placement data consisting of N cell rows by placement processing using conventional technology.

■ By inserting (G1) vertical cut lines and (N-1) horizontal cut lines in the chip area, MXN small areas g (iej) ri=
Divide into 1 to M, j=1 to N.

(2) Let the cells included in these small areas g (IIj) be a cell set s (IIj).

In response to this initial data, the layout design of the chip area is divided into several levels. In the example of this embodiment, the layout design is performed by dividing the processing into 1 to M level processing. The following processes are executed at each level of processing.

■ Reconfigure the cell set included in the small area within the uncertain area 2° (placement correction) ■ Form a window that covers a row of small areas at the left end of the uncertain area.

■ Allocate the wiring that passes through the window to a small area within the window 3゜ (General wiring) (Go) 4゜ Configure cell rows within the window (Detailed placement) ■ 5゜ (Detailed placement) to route the channels within the window Wiring) 0 If there is no 6° uncertain area with the area to the right of the window as the uncertain area, the process ends.

A detailed explanation of each step will be given below. Note that the explanation here assumes that the processing has progressed to this level. That is, the area to the left of the cut line V (k) is a definite area, and the area to the right is an uncertain area. The determined area is a small area g (i, j) + i = 1 to -1° j = 1
~N, and the uncertain region is a small region g(baj) v
1 = k-M t j = 1 to N.

Additionally, placement and wiring within the defined area have been completed. The window W(k) is composed of a small area g(k+j), j = 1 to N.

Adjust the layout> 1- In this process, the placement within the uncertain region is corrected.

Suppose now that k-level processing is to be performed. At this time lk)
The area to the right of 15 becomes the uncertain area 12. The uncertain region is composed of a small region g(iJ, 1=−Ml, j=1 to N. Let s(i, j) be a cell set allocated to the small region g (1+j). g baj) *i
= 1~M, s (i, I), i = 1~
The total sum of wiring that is not connected to any cell in M is TH(I
).

TI((I)=Σth(i,I) i=1. g (xsI) v i= Let the sum of the wiring passing through 1 to N be CH(I).

CH(I)=Σoh(I,j)-1. The arrangement of cells within the uncertain region is corrected so as to decrease these two values. Since the wiring of the definite area has been completed, the wiring information of the definite area can be reflected in the layout correction of the uncertain area.

12- The processing flow of the placement correction process is shown in FIG. This process consists of the following [Wiring modification operation 1] and [Wiring modification operation 2].

[Placement correction operation 1] ■ Combine cell set S(i, j) of small region g (irj) and s(i, j+1) of small region g (baj + 1) to form one cell set s (i, j) (baj +1).

(2) Divide the cell set s (xyj) (Lj+1) into two cell sets s'(baj) and s(i, j+1). Here, s (itj) is a cell set newly included in the small region g (iyj), and s' (lyj+1) is a cell set newly included in the small region g (19j+1). The division index is the evaluation function: TH(i)+TH(j+1)→win(TH(i)+
Minimize TH(j+1). ) len(i,j)-1en(i,j+1)l-+min
(llen(i,j) −1On(i+j+ 1)l
minimize. ) is used. Note that Jan(i, j) is the sum of the lengths of cells included in g(xyj).

■ Register the cell set s' (11j) as s baj).

The cell set s'(i, j+1) is registered as s(i, j+1).

[Placement correction operation 2] ■ Combine cell set S (X+j) of small area g(i, j) and s(i, j+1) of small area g(i+1.j) and 1
Create a cell set s (i, j) (i+Lj).

■ Divide the cell set s (xtj) (1+1.j) into two cell sets "(xtj) and s'(i+1.j).Here, s'(1°j) is divided into the small area g(Lj). The newly included cell set s'(i+1.j) is the small area g(
This is a cell set newly included in i+1−j). The division index is the evaluation function: CH(i) +CH(i+ 1) → win11en(i
, j)-1en(i+1.j)→llll1n.

■ Register the cell set s' (baj) as s (1rj).

Register the cell set s' (i+1.J) as s(i+1tj).

As shown in FIG. 21, the placement correction process involves performing the above [Placement correction operation 1] and [Placement correction operation 2] in a small area of i = k-M, j = 1 to N until there is no improvement in the evaluation function. Do this repeatedly.

<General wiring> In this process, the general route of the wiring is determined. In k-level processing, the small region g (x, j) i=−M,
Rough wiring processing is performed for the uncertain region composed of j=1 to N. The schematic wiring process referred to here is a process that determines the small area (schematic route) through which each wire passes based only on information about which small area a cell belongs to.

In the k-level rough wiring process, the placement and wiring within the defined area are completed by the process up to the k-level. Therefore, the wiring that passes through V (k) and inputs from the definite area to the uncertain area is required. Among these wirings, a set of wirings passing through V(klj) and inputting into the small region g(Lj) is defined as d(k,j).

In this process, a small region gci*J) within the uncertainty region
d(k, j), j=1 to N so that the number of wires passing through y 1 ” k-M p J = 1 to N is uniform.
and 5(LJLi = k −M, j = i =
5-schematic paths between cells included in N, and s(i, j), i = k = M, j
The purpose is to find a rough route between cells included in = i −N. However, in the processing flow according to the present invention, gci+j), i
Cell set s (
i.

j) varies. Therefore, the rough route constructed by the k-level rough wiring process is destroyed by the k+level and subsequent processes. Therefore, it is not necessarily advisable from the point of view of processing efficiency to obtain approximate routes between all cells within the uncertain region through this process. An example of the general wiring processing method shown below focuses only on window W(k).

FIG. 22 shows a schematic flow of wiring processing in this embodiment. This process consists of two operations: [General wiring operation 1] and [General wiring operation 2]. FIG. 23 shows the processing flow of [schematic wiring processing 2].

In the k-level rough wiring process, d (klj) t J = 1~N and S(k, j)
, the approximate path between cells included in j=1 to N, 16- d(k, j), j=1 to N and 5 (+1 to LjL i=
~N + J = Approximate route to cells included in 1 to N, ・s (k, j) l j = Approximate route to cells included in 1 to N, ・s (ktjL j = 1−N and s (1+J)
An approximate route between cells included in t x = 1 to +1 to M and j = 1 to N is determined. s (i, j), i = +1 ~ M, j
= A rough route between cells included in 1 to N is not determined.

In other words, nets with one or more cells belonging to 5(LjL j=1 to N) and nets with one or more cells belonging to 5(lyjL
l=1 to −1, and one or more cells are s(i
.

The net belonging to jL i=−M and j=1 to N is
It is subject to processing at the k level.

Also, in the target net, two or more cells are 5
(If LjL j= is included in +1 to M (that is, if two or more cells are included in the area excluding the window from the uncertain area), only one of these cells Find the approximate route between the cells d (k, j) and TJ's (k, j). Use the Manhattan length as an index when selecting cells, and s (k, j) t
The cell whose Manhattan length is closest to the cell belonging to j=1 to N (that is, the cell included in the window) is selected.

The Manhattan length referred to here is the length expressed as the sum of the lengths of the vertical and horizontal sides of a rectangle that has two cells at its vertices. When there are two or more cells with the same Manhattan length, the cell belonging to the small region with the shortest horizontal distance is selected from among these cells.

Next, details of each operation in this process will be described.

[Rough wiring operation 1] The rough route targeted by this operation is uniquely determined by the positional relationship of the cells to be connected. Next, a rough route is uniquely determined. Indicates the positional relationship of cells.

d(k, I).

Something that satisfies.

(a) I>n and m=k.

(b) Inn and m=k.

(c) I=n and m≧0 I=1-N and s(m, n) have the following relationship ・s(k,,
:+) and s (k, n) satisfy the following relationship.

(d) I<n.

(E)I)n.

For cells that meet the above conditions, a rough route of the pattern shown below is assigned. Examples of rough routes are shown in FIGS. 6 to 8.

(a) Schematic wiring between d (k, I) and s (m, n).

I) For n, m=: v(k, I) and h(k+j
A route passing through Lj=n+1~.

For I<n, m≦: v(k, I) and h(k, j
).

A route passing through j=I+1 to n (FIG. 7).

For I=n, m=: v(itIL Path passing through i=-n (FIG. 8).

(b) Schematic wiring between s (k, I) and s (k, n) (Fig. 6).

If I > n, h (k, j) l j=n +
A route passing through 1-I.

When I < n: h(k, j), path passing through j=■+1 to n.

[Outline wiring operation 2] This operation targets cells that were marked as unprocessed in [Outline wiring processing 1]. The rough route is not uniquely determined and has several patterns. The pattern is shown below.

Examples of schematic routes are shown in FIGS. 9 to 13.

(a) d (k, I) and s (i, n) + i
Schematic wiring between = and +1 to M.

・In the case of I > n (Figure 11): V(LIL v(k+1.I)+ ”・l V(1+I
L11(1+ILh (ilI-1), -1h(1,n
+1).

v(k, I), h(k, I), v(k+1.l-
1), v(k+2゜■-1) l ”' t V (
III-ILh(1*l-1)t h (1+l-2)
+ ”'v(k, I), h(k;I), h(k
,III),−,h(k,n+1).

v(k+1.n),..., a path passing through v(i,n). Generally, there are (n-1+1) types of general wiring patterns.

・When I < n: V(ktIL v(k+1.I)l−I V(itIL
h(ilILh bt'r + LL"'th(1+
n).

v(k, I), h(k, III), v(k+'l,
III), v(k+2.III),..., v
(i, III), h(i, I+2), h(i.

I+3), ... A route passing through t h (ien).

20 v(k, I), h(k, III), h(k, I
+2), ·=, h(k, n).

v (k +1 + n) +..., v (i, n
). Generally, there are (I-n+1) types of general wiring patterns.

(d) Schematic wiring between s (k, I) and s (itnL i =+t−M).

In the case of I>m (Fig. 10): v(k+1. ■)l"'t V(1,IL h(x,
I), h (x, l-1), ... e h (i, n+
1).

h(k, I), v(k+1.l-1), v(k+2
．． l-1), -, v(i, l-1), h(i, l-1
)l h(ill-2)l-=route passing through lh(iln+1).

h(k, I), h(k, l-1), ・=, h(k, m
+1), v(k+1゜nL...l V (iln)
A route that passes through. Generally, there are (n-1+1) types of general wiring patterns.

・If I < n: v(k+1.IL"'t v(4J)y h(x, I
), h (x + engineering + 1), ..., h A route passing through (i, n).

h(k, III), v(k+1.III), v(k+2
．． III).

−, v(i, III), h(i, 1+2), h(LI+
3), ·, a path passing through h(i, n).

h (k, I +1)-h (k, I + 2L□=-
h (k9m), v (k+1, n), ..., v
A path passing through (i, n). Generally, there are (1-n+1) types of general wiring patterns.

・When I=n (Figure 9): v(k+1.I), v(k+2.I), -, v(i,
I).

h(k, I), v(k+1.l-1), v(k+2
．． l-1), -, v(i, l-1), h(i, l-1
).

There are two types of patterns mentioned above.

(c) Schematic wiring between s(k, I) and s(k, I).

Wiring is done within the small region g(k, I) 21 (FIG. 12).

Wiring is done via the small area g(k, l-1) 22 (FIG. 13).

In [Rough wiring operation 2], the rough route is iteratively improved so as to minimize the following evaluation function.

The process ends when the evaluation function is no longer improved.

Rough wiring evaluation function: th (k, j): passes through h (Lj) and s (k, j
) total number of wires that do not connect to cells.

ch(ktj): Total number of wires passing through g(k,j).

Detailed placement〉 In this process, cell set s (ktjL j=1~
The detailed arrangement of N (that is, the set of cells within window W(k)), the insertion of through cells, and the assignment of through terminals to through wiring are performed. The purpose here is to configure cell rows within window W(k) that minimize the number of tracks used for wiring in each channel. The processing flow of this process is shown in FIG. The process of detailed placement is [Detailed placement operation 1], [Detailed placement operation 2]
, [Detailed arrangement operation 3].

Now, let us consider the case of performing k-level processing. Details of each operation are shown below.

[Detailed placement operation 1] This operation performs initial placement for later processing.

Processing is performed independently for each cell row in the window,
Correlation between cell rows is not considered.

23- Divide the cell set s(klj) into the following three sets and arrange them in cell rows.

(a) In the cell set s(k, j), let 5(klj) be the set of cells that are connected only to the wiring passing through v (k).

(b) In cell set 5(klj), the set of cells that are connected only to the wiring passing through v(k+1) is 5r(k,j
).

(c) From cell set s(k, j) 5i(k+xL 5r
Let the set excluding (ktj) be sm(k,j).

The above three sets are arranged as follows.

(a) Cell 5l(k,j) is in cell row 33r(k,
Place it to the left of j).

(b) Cell 5r(k,j) is arranged to the right of cell row r(Lj).

(c) Cell sm(k,j) is arranged so as to be located at the center of cell row r(Lj).

FIG. 14 shows the relative positional relationship of these cell sets. 5l(k,j) is at position 30, 5r(k,
j) is placed at position 31, and sm(Lj) is placed at position 32.

However, since the arrangement will be improved in the later [Detailed arrangement operation 3], the detailed X coordinate of each cell is easily determined.

[Detailed placement operation 2] In this operation, the through terminal 41 is connected to the through wiring 40.
and inserting through cells. The purpose here is to assign through terminals to through wiring so that a cell arrangement that uses fewer tracks when detailed wiring is done, and to assign through cells to through wiring as necessary. Insert into a row.

In the prior art, after the detailed arrangement of cells is completed, the process of determining the cell over which the through wiring passes and the process of inserting the through cell are performed. However, in the present invention, it is difficult to determine which cell the through wiring passes over, and
After determining in advance whether or not to insert through cells, detailed cell placement is performed. This makes it possible to prevent problems caused by shifts in cell positions due to the insertion of through cells, and also to enable cell arrangement that takes through wiring into consideration.

Here, the set consisting of cells satisfying the following condition is sn+'
(k, j). A cell belonging to the cell set S(k,j) has an area on the cell where a through wiring can pass, and the connecting wiring is V(k) and V(k+1
), and the total number of wires passing through V(k) is the same as the total number of wires passing through V(k+1).

The through terminal on the cell of sm' (k, j) will be referred to as ``'priority through terminal 42''.
The priority s
Cells belonging to m' (k, j) are in cell row r (klj
) does not change the track length used within the window. Therefore, it is only necessary to arrange the cells so that only the track length used by the through wiring connected to the through terminal is minimized. Simple examples are shown in FIGS. 17 and 18.

These are schematic diagrams representing two adjacent cell rows within a window. In this figure, 42 is a priority through terminal;
40 is a through wiring. In this case, the track length used within the window can be reduced simply by moving the cell position of 44 from the position shown in FIG. 17 to the position shown in FIG. FIGS. 15 and 16 show examples in which the through wiring is connected to the through terminal other than the priority through terminal. In this case, simply moving the 43 cells from the position shown in FIG. 15 to the position shown in FIG. 16 does not necessarily contribute to reducing the track length used within the window.

As shown in this example, when through terminals other than the priority through terminal are assigned to through wiring, the process of reducing the track length used within the window becomes complicated.

Processing is performed in the following steps (g) to (3).

■ Select one through wire.

■ Extract through terminals one by one from the cell rows through which the through wiring passes and assign them.

The allocation will be made under the following conditions:

(a) Priority - If there is an unused terminal among the terminals, it is assigned with priority. If there are no unused ones,
Allocate through cells on cells other than slI'(k,j). If there are no unused through terminals 7-, a through cell is inserted into the cell row r (k, j), and the through terminals on the through cells are assigned. After[
Since the placement position is improved in [Detailed placement operation 3], the X coordinate of the through cell is easily determined.

(b) Cell row r (ktj-1) or r(k, j+1)
The through terminal assigned to is not the priority through terminal,
If there is no unknown priority through terminal in r (k, j), a through cell is inserted into r (k, j), and the through terminal on the through cell is assigned. Since the placement position will be improved in the later [Detailed placement operation 3], the X coordinate of the through cell is easily determined.

(3) Register the through terminals assigned to through wiring as used and do not assign them to other through wiring. Perform the above process for all through wiring.

[Detailed placement operation 3] In this operation, cell placement is improved so as to minimize the virtual wiring length of the cell row within the window.

The virtual wiring length referred to here is 2 as shown in Figures 19 and 20.
8- This is the track length when one track is assigned to one wiring. Furthermore, since the through wiring is assigned to a virtual terminal in [Detailed placement processing 2], it is treated in the same way as general wiring.

The following is used as an evaluation function for placement improvement.

I (i, x): The process of improving the virtual line length and arrangement of the wiring X belonging to channel i is performed by moving cells so that this evaluation function is minimized. However, cells can only be moved within the same cell row. It does not move to a different cell row. Also, cell movement is closed within the window.

For example, Reference 2: ``Standard Cell VLSI Placement Method and Its Evaluation'', Tokinori Ozawa et al., Journal of the Institute of Electronics and Communication Engineers, '84
/10 Vol, J67 D N+110. pp,
In conventional placement improvements such as those shown in 1123-1130, each cell row is processed independently, and therefore wiring between cell rows cannot be evaluated. Normally, it would be possible to obtain better cell placement results by treating all cell rows at once and evaluating the wiring between cell rows, but since the problem becomes too large, It is difficult to handle rows at once. However, in the method of the present invention, only cells included in the window are handled at one time, so the problem does not become too great even if all cell rows are processed at the same time. Therefore, wiring between cell rows can also be taken into consideration.

In the present invention, the arrangement is improved by a method using the pair exchange method shown in the following ω~(0. The processing flow is shown in Fig. 25. Examples of the processing are shown in Figs. 19 and 20. 20 is a diagram showing an example in which the evaluation function is reduced by exchanging cell A50 and cell B51 shown in FIG.

■ Select a random cell column from among the cell columns in the window. Let the currently selected cell column be r (klj).

(21R Select two cells at random from (k, j). Let these cells be sl and s2.

■ Swap the positions of sl and s2. 79° (a) Calculate the evaluation function after cell exchange, assuming that the cell row after exchange is r'(ktj).

■ If the evaluation function decreases due to cell exchange, r
'(klj)→r(k,j). If it has increased, the positions of sl and 82 are returned to their original positions.

Processing from 0(1) to 0 is repeated until no improvement in the evaluation function is observed.

<Detailed wiring> In this process, wiring between cells within the window is performed. Since the through position within the window is determined by a "through positioning process," wiring can be performed independently for each channel. However, since the wiring to the left end of the window V(k) has been completed, channel wiring will be continued from V(k) to the right end of the window V(k+1). As a model, this is a wiring problem for an area where the terminal positions in three directions are fixed and the terminal positions in one direction are not fixed. Various wiring methods can be considered for such a region, but in this embodiment, a method called 1-'greedy' router is used. Details of this method can be found in Revest, R.L., an
d C, M, Fiduccia, A'greedy'
channel router in Proc,
19th Design Automation Con
f,, pp, 475-481. June 1982
．． is shown. The method in the above document targets one channel and performs wiring while moving the channel from left to right along a sweep line (while completing wiring in the area to the left of the sweep line).

Therefore, in the wiring within the window of the present invention, channel wiring is completed up to lk)15. That is, V (
Considering that the sweep line has finished moving up to k),
By considering moving the sweep line further up to V(k+1)16, we can create a 'greedy' router.
can be used.

〔Effect of the invention〕

As described above, according to the present invention, placement and wiring processing can be performed in parallel, and a layout result with a higher degree of integration can be obtained.

[Brief Description of the Drawings] 32- Fig. 1 is a diagram showing a processing flow of an embodiment of the present invention;
The figure is a diagram for explaining the layout design according to the present invention,
Figure 3 is a diagram showing a state in which the processing has progressed further than in Figure 2;
FIG. 4 is a diagram for explaining the division of the chip area, FIG. 5 is a diagram for explaining the small area, FIGS. 6 to 13 are diagrams for explaining the schematic wiring route, and FIG. is a diagram for explaining the initial arrangement, Figures 15 to 18 are diagrams for explaining the process of assigning through terminals to through wiring, and Figure 1 is a diagram for explaining the initial arrangement.
Figures 9 and 20 are diagrams for explaining virtual wiring between cells and cell placement improvement processing, Figure 21 is a diagram showing the processing flow of placement correction processing, and Figure 22 is a diagram showing the processing flow of general wiring processing. 23 is a diagram showing the processing flow of the iterative improvement unit in the general wiring process, FIG. 24 is a diagram showing the processing flow of the detailed placement process, and FIG. 25 is a diagram showing the processing flow of the iterative improvement unit in the detailed wiring process. FIG. In the figure, 10... Window, 11... Determined area, 1
2... Uncertain area, 13... Cut line,
14...Small area, 40...Through wiring, 41...Through one terminal, 42...Priority through one terminal.

Claims (1)

[Claims] A placement/routing determination area in which the placement/routing of the circuit element is determined within the chip area when placing circuit elements in a plurality of band-shaped areas within the chip area and determining wiring that satisfies connection requirements of circuit element terminals. and has an undetermined placement/routing area where the placement/wiring of circuit elements has not yet been determined, and
The placement/routing information is based on the placement/routing information of the wiring determination area.
modifying the general arrangement of circuit elements in the undetermined wiring area, and determining a planned placement/routing area that spans the plurality of strip areas in a direction perpendicular to the longitudinal direction of the strip area in the undetermined placement/routing area; The detailed placement of the circuit elements within this planned placement/routing area is determined, and the wiring between the circuit elements within the planned placement/routing area is determined, and the placement/routing determination area and detailed placement and wiring are determined. A layout design method characterized by registering and updating the planned placement/routing area as a new placement/routing determination area.