JPH06209043A - Automatically arranging method and device for functional cell in designing digital lsi - Google Patents

Abstract

PURPOSE:To obtain a desired characteristic against the delay of a signal by arranging functional cells existing on the flowing route of the signal in a logic circuit in the arrangeable area of functional cells on a layout model. CONSTITUTION:In step S1, the wiring delay restricting time of a route in a logic circuit is weighted and, in step S2, the shortest input-output routes between output terminals and input terminals on a network list is set to all output terminals. In step S3, the wiring routes of all shortest input-output routes are roughly decided on the two-dimensional grid graph corresponding to cell lines on a layout model and, in step S4, the arrangeable area of functional cells on the roughly decided wiring routes of the shortest input-output routes is decided. In step S5, the functional cell on each shortest input-output route is initially positioned in the decided arrangeable area and, in step S6, the final functional cell arranging positions are decided by initially arranging unarranged functional cells and modifying the positions of initially arranged functional cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement method and apparatus for digital LSI design.

[0002]

2. Description of the Related Art At present, in the layout design of a digital circuit, a part common to each functional product is made into one cell by increasing the size of the circuit mounted on the LSI and increasing the multifunction of the LSI.
A semi-custom method in which only a part peculiar to an individual product is newly designed as a (functional cell) in advance is widely used.

By the way, the automatic placement technique is an important technique for automatically designing a digital LSI by the above-mentioned semi-custom method, and its research has been conducted for a long time. In the automatic layout design of the digital LSI, the positions of the functional cells are determined (placement processing) and the connection between the functional cells is made.
(Wiring processing) is performed. Here, the placement process and the wiring process are originally a series, and it is difficult to consider them separately. This is because it is the goal of the layout to improve the accommodation capacity of the wiring that controls more than half of the chip area.

However, if the placement process and the wiring process are carried out as a unit, the problem becomes too complicated and the processing time becomes long. The current situation is that we are asking for each of these and wiring processing (for example, “BTPreas, PG
Karger "AUTOMATIC PLACEMENT A REVIEW OF CURRENTTE
CHNIQUES ”: 23rd Design Automation Conference, 198
6, pp.622-629 ”).

Recently, many layout methods in which electrical characteristics are taken into consideration have been proposed, and an arrangement method in which delay between elements is a constraint condition has been reported (A. Srinivasan, et a.
l, `` RITUAL: A Performance Driven Placement Algorit
hm for Small Cell ICs ”: Computer-Aided Design, 199
1, pp.48-51).

[0006]

Generally, in the automatic layout design of a digital LSI, the above layout processing and wiring processing are automatically performed. At that time, it is considered to handle a functional cell having the same width and an arbitrary length. Each functional cell has a terminal for connection. Further, the model in which the functional cells are arranged is such that a set of functional cells in which the functional cells are one-dimensionally arranged in the length direction (cell row) is spaced at a predetermined interval in the direction orthogonal to the length direction of the functional cells. It has a one-dimensional array structure. The arrangement area of the functional cells is a rectangular area including the array structure, and terminals for connecting to the outside are arranged around the rectangular area.

Here, the connection request in the logic circuit is given to the terminal of each function cell, and the arrangement position of each function cell is determined based on these connection requests in the arrangement process. is there.

In the method proposed so far, the functional cells are arranged based on the evaluation standard obtained from the distribution range of the terminals for which the connection request is issued. However, as the element manufacturing technology advances, the connection element between each functional cell influences the signal delay, and based on the evaluation standard obtained from the distribution range of terminals for which a connection request has been made as in the past. If you did the placement process and wiring process,
There is a problem that desired characteristics are often not obtained with respect to signal delay.

SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic placement method and its apparatus in a digital LSI design that can obtain desired characteristics with respect to signal delay.

[0010]

In order to achieve the above object, the automatic placement method in the digital LSI design of the first invention is a connection added in a logic circuit of a digital LSI prior to a placement process of functional cells. A path based on the flow of a signal is obtained using information, and the signal on the layout model showing the layout of the functional cell array structure on the chip based on the path information including at least the path length and the signal delay time of the obtained path. The general wiring route corresponding to the route based on the flow of the flow path and the preset possible placement area of the functional cell are set, and the functional cell on the route based on the signal flow in the logic circuit is set in the layout model. An automatic placement method in a digital LSI design, characterized by placing in a place where functional cells can be placed.

Further, the automatic placement apparatus in the digital LSI design of the second invention reads the connection information added to the logic circuit of the digital LSI and uses the read connection information based on the signal flow in a predetermined procedure. Route setting means for setting a route, and calculating a route length of the route based on the signal flow set by the route setting means, and based on route information including at least this route length and a preset signal delay time. Function cell allocable area setting means for setting a schematic wiring path corresponding to the path based on the signal flow and a allocable area of a functional cell on a layout model representing a layout of a functional cell array structure on a chip by a predetermined procedure. And a functional cell existing on the path set by the path setting means in the logic circuit, It is characterized by having a function cell placement means for placing the placement area of the functional cell which is set by the function cell arrangement area setting means on the Lee-out model.

[0012]

In the second aspect of the invention, the connection information added to the logic circuit of the digital LSI is first read out by the path setting means, and the path based on the signal flow is set by a predetermined procedure using this connection information. It Then, the functional cell allocable area setting means calculates the path length of the path based on the signal flow set by the path setting means. Then, based on the route information including at least the calculated route length and the preset signal delay time, it corresponds to the route based on the signal flow on the layout model showing the layout of the functional cell array structure on the chip. The general wiring route and the area where the functional cells can be arranged are set by a predetermined procedure.

Then, the functional cell arranging means sets the functional cells on the path set by the path setting means in the logic circuit on the layout model set by the functional cell allocable area setting means. It is placed in the placeable area of the functional cell.

In this way, the functional cells are arranged based on the path information including the signal delay time, whereby the functional cells are arranged by positively utilizing the electric delay information, and the obtained digital LSI is a signal. It also exhibits the desired characteristics for delay.

[0015]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a diagram showing a processing procedure by an automatic placement method in the digital LSI design of this embodiment.
FIG. 4 is a layout model diagram showing an example of the layout of the cell array structure handled in this embodiment.

In the layout of the digital circuit handled in this embodiment, a plurality of cell rows 2, 2, ... Are arranged in parallel in the standard cell block 1 as shown in FIG. 2 (a). And, in each cell row 2, a plurality of functional cells 3, 3, ... (Where only one is described) are arranged in a row at a predetermined interval.
Are arranged to form an array structure. The functional cell arrangement area is a rectangular area including the cell rows 2, 2, ... And terminals 4, 4, ... For connecting to an external circuit are formed around the rectangular area.

FIG. 2B is an enlarged view of the functional cell 3. The circuit structure of the functional cell 3 is, for example, a logic circuit (a NAND gate), and terminals 5 for connection are formed in the periphery. A connection request is given to each terminal 5 of the functional cell 3. Then, regarding the wiring of each functional cell, the on-cell wiring is performed using a two-layer wiring.

Next, the outline of the automatic placement method in the digital LSI design implemented in this embodiment will be described.

In the present embodiment, in addition to the connection relationship between the functional cells 3 in the logic circuit based on the connection request given to each terminal 5 of the functional cell 3, a route based on a signal flow is placed. By obtaining the characteristics in the stage before performing, and performing the arrangement by the path based on the obtained signal flow (that is, the arrangement using the electric delay information explicitly), the desired characteristics can be obtained even for the signal delay. The arrangement of the functional cells 3 included therein is obtained. Here, the path based on the signal flow is a path determined by obtaining the shortest path when searching for the connection relationship between the output terminals and the input terminals related to all the functional cells in the logic circuit. (Hereinafter, the shortest path based on this signal flow is simply called the shortest input / output path). At this time, as will be described later, the determined shortest input / output path is a path in which connection requests and functional cells appear alternately.

The distance from the input / output terminal of the shortest input / output path is defined by the number of functional cells included in the shortest input / output path. Also, when one functional cell exists on a plurality of shortest input / output paths, the degree of occupancy is defined by the number of shortest input / output paths passing through one functional cell.

The shortest input / output path obtained as described above corresponds to the path from the output terminal to the input terminal on the chip (that is, on the layout model as shown in FIG. 2). Therefore, before arranging the functional cell 3 on the layout model, the route on the layout model of the shortest input / output route is obtained.
At that time, the route length of the route on the layout model corresponding to each shortest input / output route is
/ Determine the route on the layout model so that the length corresponds to the distance from the output terminal.

The path determination order on the layout model is basically from the input / output terminal side of the shortest input / output path. In the case of the shortest input / output path related to a signal that conveys important information whose delay time influences the characteristics of the digital circuit in the logic circuit information, the input / output of the shortest input / output path as described above The order of determining the route on the layout model based on the distance from the output terminal is changed to perform the early processing.

After that, the area of the route on the layout model is divided. This is an index when actually determining the position of the functional cell 3, and is a schematic layout position (area) on the layout model of the functional cell 3.
Is calculated according to the distance from the input / output terminal 4 of each of the shortest input / output paths.

After the above processing, the functional cells on the shortest input / output path are arranged at the rough arrangement positions on the layout model. In this case, since attention is focused only on the functional cells on the shortest input / output path, all the functional cells in the logic circuit that are not on the shortest input / output path are not arranged. Become. Therefore, for unplaced functional cells as well, a route search is performed according to the connection request of the input terminal or output terminal starting from the unplaced functional cell, and the shortest route ending at the input / output terminal of the logic circuit or the already placed functional cell Ask for. After that, similarly to the case of the already-arranged functional cell, the arrangement position of the unarranged functional cell on the layout model is determined.

In this way, the layout positions of all the functional cells in the logic circuit on the layout model are determined, but the connection requests in the logic circuit that do not take into consideration the layout are connected. The presence / absence of the function cell locally replaces / moves the functional cell to determine the final relative functional cell position.

Hereinafter, the automatic placement method in the above-described digital LSI design will be described in detail for each step. Here, the list of connection requests (netlist) of the logic circuit, the size of each functional cell and the position of the terminal, the delay time of the signal path on the netlist and the delay time of the functional cell are input in advance and given. It is assumed that
FIG. 1 shows a processing procedure for allocating a functional cell 3 to each cell row 2 on the layout model by the automatic arrangement method.

The function cell allocation procedure will be described below with reference to FIG. In the weighting process for the designated route in step S1, the designer performs weighting with the wiring delay constraint time for the route in the designated logic circuit as the weight “δ _k ”. In the shortest input / output path activation process of step S2, the shortest input / output path from the output terminal to the input terminal in the net list is set for all output terminals. In the rough wiring process of the shortest input / output path in step S3, the rough wiring routes of all the shortest input / output paths determined in step S2 are determined on the two-dimensional grid graph corresponding to the cell row in the layout model. .
In the division processing into the distributable area in step S4, the disposable area of the functional cell on the rough wiring route of the shortest input / output path is determined. In the initial placement process of the functional cell in step S5, the functional cell on each shortest input / output path is initially placed in the assignable area determined above. In the arrangement improving process of all functional cells in step S6, the initial arrangement of unarranged functional cells and the arrangement improvement of the initially arranged functional cells are performed to determine the final arrangement position of the functional cells.

Next, the steps S2 to S6 will be described in more detail. (1) Step S2: <Shortest I / O path activation process> In this process, a functional cell is set as a node in a given netlist of a logic circuit, and a directional branch is set in accordance with a connection request for graphing. To do. 3 is an example of a circuit diagram of the input logic circuit, and FIG. 4 is a graph obtained as a result of graphing from the input logic circuit shown in FIG. 3 according to the following rules.

The terminal 5 of the functional cell 3 has attributes of input, output and input / output. And each terminal 5
Based on the connection request of 1, the directional branch having the weight σ _k (= wiring delay constraint time) is set from the output terminal of one functional cell to the input terminal of another functional cell. Then, the weights σ _k of the directional branches from the primary output to the primary input on the given netlist are added, and the chain of directional branches having the minimum total weight obtained is defined as the shortest input / output path. decide.

(2) Step S3: <Schematic Wiring Process of Shortest Input / Output Path> In this process, based on the cell array structure including the cell rows 2 in the layout model as shown in FIG. 2, 2 as shown in FIG. A two-dimensional grid graph is obtained, a rough wiring route is determined based on this two-dimensional grid graph, and rough wiring processing is performed.

The primary input and the primary output on the net list correspond to the external input terminal and the external output terminal of the terminals 4 in FIG.
It corresponds to the start point and end point of the shortest input / output path obtained in. Therefore, in this processing, the outline of the shortest input / output path between the external input and the external output on the chip is determined using the two-dimensional lattice graph.

The horizontal sides in the two-dimensional lattice graph shown in FIG. 5 correspond to the horizontal channels in the layout model shown in FIG. Then, since the chip length in the row direction in the standard cell block 1 is determined by the sum of the widths of the horizontal channels, in this processing, the evaluation function as shown in Expression (1) is defined.

[Equation 1] Here, Ch _ij : the number of routes passing through the horizontal side on the i-th row and the j-th column. In this process, the chip shape is reduced by determining the rough wiring route so as to minimize the evaluation function F _pgr . is there. The route search area at that time is limited to the minimum rectangle surrounding the input / output terminals.

(3) Step S4: <Division Processing into Placeable Areas> In this processing, each rough wiring route obtained in step S3 is set to the shortest input / output route length (number of nodes) obtained in step S2. By equally dividing, the arrangeable area near each division point of the wiring route is determined.

The k1-th division point (neighboring point where the functional cell is arranged) on a certain shortest input / output path is obtained by the equation (2).

[Equation 2] Here, L _{pe (k1)} : Euclidean distance of the wiring path from the input terminal to the k1th division point L _pet : Euclidean distance of the wiring path from the input terminal to the output terminal σ _k : (k-1) th Wiring delay constraint time from the functional cell to the kth functional cell

After determining all the route division points by the above processing, the functional cell allocable area is determined. This allocates an area of 4 functional cells (2 × 2) corresponding to the dividing point on the cell row 2 near the dividing point. still,
Here, it is assumed that the functional cell allocatable areas to be allocated are allowed to overlap.

FIG. 6 shows an example of an outline wiring route of a certain shortest input / output route (PI1 → PO1) set in the above step S3, and FIG. 7 is a functional cell determined based on the outline wiring route shown in FIG. An example of the possible arrangement area is shown. In FIG. 7, the schematic wiring route is divided into 9 routes, and the functional cell C4 allocable region 1 is arranged in the cell row 2 near the fourth (k1 = 4) division point from the input terminal PI1.
1 is assigned.

(4) Step S5: <Initial placement processing of functional cells> In this processing, the functional cells on the shortest input / output path obtained in step S2 are initially placed in the allocatable area obtained in step S4. To do. At that time, a plurality of functional cells are allowed to be overlapped in one allocable area. Then, after the initial placement processing is completed, the final placement position is determined by referring to the distribution positions of the function cells in order from the function cell with the lowest occupancy. Note that the functional cells are not overlapped when determining the final placement position. Also,
The position of each functional cell is determined so that the evaluation function F _pgr becomes small even when the functional cell is moved. When the functional cell is moved, the rough wiring route on the two-dimensional lattice graph used in step S3 is updated.

(5) Step S6: <Arrangement Improvement Processing of All Functional Cells> In this processing, arrangement processing and arrangement improvement processing of the functional cells not arranged in the above step S5 are performed. In the process in step S5, the functional cell which is not on the shortest input / output path is not arranged. Therefore, the placement processing of the unplaced functional cells is performed as follows.

First, with respect to all the functional cells that have not been placed on the netlist, the above step S is performed.
Find the shortest path to the functional cell on the shortest I / O path found in step 2. As the shortest path at that time, the shortest path from the search starting from an unplaced functional cell to reaching the already arranged functional cell, the input terminal or the output terminal is adopted. Next, the input / output terminals in the processes of steps S3 to S5 are replaced with the functional cell positions on the shortest path, and the processes are executed. At this time, the wiring route is determined by using the already-wired function cell as the start point or the end point. Furthermore, at the time of initial placement of the functional cells, each unplaced functional cell is placed in the vicinity of the route division so that the cell row width does not become uneven.

After the initial placement of all the functional cells is completed in this way, the placement is improved as follows. That is, in the above-mentioned initial placement, the processing is performed by considering only the net length included in the shortest I / O path on the netlist, whereas in the placement improvement processing, the net (connection request ) Is also evaluated.

That is, with all the functional cells arranged, the rough wiring on the rough wiring model used in step S3 is performed again. After that, select the functional cell and replace it so that the wiring density in each channel is reduced.
It moves and so on. In the evaluation for improving the layout of the functional cells, as shown in FIG.
Based on the connection request from the output terminal 11 of the functional cell C1
Virtual wirings L11-12, L1 to the input terminals of 2 to C14
1-13 and L11-14 are set. Then, as shown in FIG. 9, all the virtual wirings L11-12, L11-13,
A virtual half of the entire perimeter of a rectangle whose diagonal is a straight line connecting the output terminal and the input terminal in the combination of the output terminal of the functional cell C11 and the input terminals of the functional cells C12 to C14 in L11-14 Use the wiring length (evaluation function). In this way, the placement improving process is performed so that the virtual wiring length is shortened.

The functional cell layout improving process is performed by selecting functional cells from a region having a high linear density, a position where the wiring density is reduced, a position where the cell row lengths are made uniform, and the shortest path obtained in step S2 or step S6. Move to a position that complies with the wiring length constraint (delay time constraint value) corresponding to.

As is apparent from the above, in the present embodiment, prior to the placement of the functional cells, the weighting δ _k (wiring delay constraint time) on the netlist is referred to by referring to the connection request added to the terminal in the logic circuit. Find the shortest input / output path that minimizes the sum of). Then, the rough wiring route of this shortest input / output route is determined using the above two-dimensional lattice graph. Then, the functional cell allocable area on the layout model is determined based on the rough wiring path and the shortest input / output path, and the functional cells on the shortest input / output path are initially arranged in the functional cell allocable area. There is. Therefore, by arranging the electric delay information based on the signal flow explicitly, the desired digital LSI characteristic can be obtained even for the signal delay.

[0044]

As is apparent from the above, the automatic placement method in the digital LSI design of the first invention uses the connection information added in the logic circuit of the digital LSI to find the path based on the signal flow, Based on the route information including at least the route length of the determined route and the preset signal delay time, the general wiring route corresponding to the route based on the signal flow on the layout model and the allocable area of the functional cell Since the function cells on the path based on the signal flow in the logic circuit are set in the area where the function cells can be arranged on the layout model, the function cells are arranged based on the signal delay information. Be seen. Therefore, according to the present invention, desired digital LSI characteristics with respect to signal delay can be obtained.

Further, according to the present invention, it is possible to match the algorithm of the rough wiring process when setting the rough wiring route on the layout model with the algorithm of the wiring process, and the layout process and the wiring process can be performed. The problem of inconsistent optimal solutions is solved.

In the automatic placement device in the digital LSI design of the second invention, the route setting means sets the route based on the signal flow using the connection information read from the logic circuit of the digital LSI, and the functional cell allocable area is set. A general wiring route and a function corresponding to the route based on the signal flow on the layout model based on the route information including at least the route length of the route based on the signal flow and the preset signal delay time by the setting means. By setting the area where cells can be placed, by the function cell placement means,
Since the functional cells on the path based on the signal flow in the logic circuit are arranged in the area where the functional cells can be arranged on the layout model, the functional cells are automatically arranged based on the signal delay information. be able to.
Therefore, according to the present invention, it is possible to provide an automatic placement device in a digital LSI design that can obtain desired digital LSI characteristics even with respect to signal delay.

[Brief description of drawings]

FIG. 1 is a diagram showing a processing procedure of an automatic placement method in a digital LSI design of the present invention.

FIG. 2 is a layout model diagram showing an example of a layout of a cell array structure handled by the present invention.

FIG. 3 is a diagram showing an example of a circuit diagram of an input logic circuit.

FIG. 4 is a diagram showing a graph obtained from the logic circuit diagram shown in FIG. 3;

FIG. 5 is a diagram showing an example of a two-dimensional lattice graph.

FIG. 6 is a diagram showing an example of a schematic wiring path on a two-dimensional lattice graph.

FIG. 7 is a diagram showing an example of a region where functional cells can be arranged, which is determined based on the schematic wiring route shown in FIG. 6;

FIG. 8 is a diagram showing an example of virtual wiring set when improving the layout of functional cells.

9 is an explanatory diagram of a virtual wiring length based on the virtual wiring shown in FIG.

[Explanation of symbols]

1 ... Standard cell block, 2 ... Cell row, 3,
C1 to C9, C11 to C14 ... Functional cells, 4, 5 ... Terminals,
11 ... Area where functional cells can be arranged.

Claims (2)

[Claims] 1. A path based on a signal flow is obtained by using connection information added in a logic circuit of a digital LSI prior to a functional cell placement process, and at least a path length of the obtained path and a preset value are set. Based on the route information including the generated signal delay time, the rough wiring route corresponding to the route based on the signal flow on the layout model showing the layout of the functional cell array structure on the chip and the allocable region of the functional cell are set. An automatic placement method in a digital LSI design, wherein a functional cell on a path based on the signal flow in the logic circuit is placed in a placeable area of the functional cell on the layout model. 2. A route setting means for reading connection information added in a logic circuit of a digital LSI and setting a route based on a signal flow in a predetermined procedure using the read connection information, and the route setting means. A layout model that calculates the path length of the path based on the signal flow set by the above, and represents the layout of the functional cell array structure on the chip based on the path information including at least the path length and the preset signal delay time. The function cell allocable area setting means for setting the general wiring path corresponding to the path based on the signal flow and the allocable area of the function cell by a predetermined procedure, and the path setting means in the logic circuit. Set the function cell allocable area on the layout model by setting the function cells on the route Automatic placement apparatus in a digital LSI design, characterized by having a function cell placement means for placing the placement area of the set the functional cells by.