JPH0212856A - Wiring process of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To perform the efficient wiring process subject to no extra trunks and detours, thereby highly densifying the large scale logic integrated circuit chip by a method wherein the range of objective connections between subnets is expanded into a plurality of channels in the subnets to select a pair of trunks for minimizing the routing cost of wirings as to the whole assemblies of the trunks within the range. CONSTITUTION:In order to decide the wiring route in outline of nets to be passage-wired over the cell rows when a wiring pattern connecting the logic cells in a block comprising a plurality of rows arranged in the horizontal direction is formed, the terminal of the net required to pass over the cell rows are respectively divided into a plurality of subnets comprising the assembled terminals to be wired using no through wiring. Next, the wiring segments in the horizontal direction are sampled respectively from two subnets to be wiring- processed to cut a pair of wiring segments and then the passage-wiring over an imaginary cell row is alloted for the wiring segments to evaluate the routing cost of the wiring. Finally, said routing cost evaluation is repeated in pairs of the wiring segments to select and register the optimum assembly for the allotment of the passage-wiring over the cell row.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention is directed to arranging a large number of logic cells in a semiconductor chip and
The present invention relates to a method for processing wiring within a block in automatic layout using a computer of a semiconductor integrated circuit device having blocks formed by stacking the blocks.

(Prior Art) The standard cell method is known as a design method for semiconductor integrated circuit devices. This improves design efficiency by preparing a large number of standardized logic cells as a library and using them. Depending on the standardization style of logic cells, it can be divided into two types: polycell type and building block type. In the former method, cells with a constant height direction are registered in a library in principle, and these are arranged in regular rows, and multiple such cell rows are formed and integrated on a chip, and each cell is Desired circuit operation is achieved by wiring between the terminals. Standard cells at this time include NAND, NOR, flip-7
0 Tsubu etc. are used. On the other hand, the latter has no restrictions on the shape of cells used as libraries, and can also use large cells such as ROM and RAM (these are called macroblocks). Both the block and the block constructed using the polycell type described above are mounted on the same chip, and by wiring them, the desired circuit operation is achieved as a whole. This design method is particularly suitable for designing large-scale semiconductor integrated circuits.

FIG. 8 shows a schematic configuration of a general building block type standard cell type semiconductor integrated circuit chip. The device is composed of two functional blocks, an input/output circuit area 4 provided around the chip, and a wiring area 5 for laying wiring between these blocks.

FIG. 9 is an enlarged view of polycell type block 3, which is one of the three functional blocks in FIG. The block 3 is divided into a cell column 6 in which a large number of cells 8 are arranged and a wiring region (channel) 7. Channel 7 is
This is the area where wiring is laid to connect the input and output terminals of each cell. Two layers of metal wiring are normally used for the wiring, with first layer metal wiring and second layer metal wiring allocated in the horizontal and vertical directions, respectively. The height (width) of the channel is not fixed in advance, and is used only as needed for wiring. In addition, there is a place in the cell where the second layer metal wiring can pass through, and wiring that needs to span multiple cell rows (hereinafter referred to as "through wiring") can pass there. However, if there are insufficient locations within a cell that can accommodate through wiring for the required number of through wiring, cells dedicated to through wiring (feed through cells, hereinafter simply referred to as through cells) are used between adjacent cells in a cell column. The method used is to generate and insert a through wire to realize through wiring.

By the way, it is no longer possible to manually design wiring for such highly integrated and large-scale standard cells, and automatic wiring processing using a computer is usually used. Automatic wiring processing is broadly divided into global wiring processing, which determines the general wiring route, and channel wiring processing, which performs detailed wiring processing within each channel.In particular, from the perspective of integration level, global wiring processing occupies the largest share. An example of global wiring processing, which plays a large role, is JP-A-62
Examples include the technology described in No. 78572.

An outline of the processing flow will be explained with reference to FIG. Generally, one net is a collection of terminals (subnet) that can be connected without the need for through wiring that involves inserting through cells.
is composed of one or more subnets, and in the global wiring process, the wiring within the subnet is first performed (the 12th
Figures h1 to h3), then execute the wiring between each subnet (Figure 12 h4 to h6). In the wiring process within the subnet, connect terminals so that the wiring length is as short as possible without using through wiring. 6 Next, in connection processing between subnets, those that require a new trunk line for connection are called TYPEI) and those that do not require a new trunk line (this is called TYPEI).
Figure 12 h5),
In each case, the allocation position to the trunk channel and the allocation position to the through wiring are optimally selected.

After the global wiring process is completed, detailed wiring process is executed for each channel (h7 in FIG. 12).

The state of wiring resulting from the above processing will be explained by showing a specific example. Figure 10 shows that one net has three subnets S.
, S2, and S3, however,
The subscripts used here follow the notation defined in FIG. 7, that is, the main line within each subnet is named t ijk. 1 (1=1.2, 3, . . . ) is the subnet number, j is the channel number, and k is the trunk number in the j-th channel. The same applies to the drawings used below. In global wiring processing, first subnet S, sS3
After performing the connection processing within the subnet, the S 1S 2 between subnets
and performs connection processing of S 2 S s. In this example, the main line t11 in the channel facing S32
Since there is an overlap in the X coordinate between 1 and t2j1, if through wiring is performed within this range, connection processing can be performed without creating a new trunk line, so TYPE is used between 81 and 82.
Belongs to I[.

On the other hand, between S 2 S 3, the trunk line t 2i + 11 and t 3
There is no overlap in the X coordinate with No. 11, and it is necessary to generate a new trunk line for connection processing, so it is classified as TYPEI. The connection processing between subnets of TYPEI is realized by allocating through wiring within the overlapping section of the main line. For TY'PEI, all the nets that require a new trunk line are extracted at the same time, and the terminal located at the top or bottom of each subnet is extracted, and the trunk line is created so that the wiring length and channel congestion are not locally concentrated. Determine allocation channels and uniquely allocate through wiring to them.

In the above-described global wiring processing, the terminals targeted for wiring processing between subnets in the TYPEI wiring processing are limited to those within the channels at the top and bottom of the subnet. For this reason, when looking through one net as a whole, the wiring route often ends up having many detours.

FIG. 11 is a typical example where detour wiring occurs. Only the top terminal of Sl and the bottom terminal of 82 are selected for connection processing between subnet S S2,
The wiring results between the two subnets are largely meandering. ``This creates an extra trunk line, leading to an increase in the number of wiring tracks, resulting in a decrease in chip integration.

(Problems to be Solved by the Invention) As described above, in global wiring processing using the conventional building block method, extra trunk lines with many detours are created in connection processing between subnets, making it impossible to realize effective wiring. There was a problem.

An object of the present invention is to provide a wiring method for a building block type semiconductor integrated circuit device that solves such problems.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, in connection processing between subnets, the connection target range is not limited to the top and bottom of the subnets.
This is extended to multiple channels within the subnet, and the trunk pair with the minimum wiring route cost is selected for all combinations of trunks within that range.

At this time, at least the following two criteria are used as standards for wiring route costs.

1. Trunk overlap length in the two subnets selected as candidates for connection processing 2, predicted increase rate of block size calculated from routes taken as candidates for connection processing 1, those with long overlap lengths, and 2. Then, select the one with the smallest predicted increase rate of block size.

(Function) According to the present invention, since the connection process is performed by searching for duplication of existing trunk lines in the connection between subnets, there is no need to create new redundant trunk lines in the connection between subnets. The increase in is minimized, resulting in a smaller block height.

On the other hand, by expanding the connection processing to terminals in other channels, the number of through wiring locations increases, but most of them are TY
PEI is converted to TYPEI[, and the degree of freedom in the allocation position of through wiring increases by the overlapping range of trunk lines, so the increase in the number of inserted through cells can be suppressed to a minimum. Therefore, the increase in block width by the above means is only a slight increase.

(Embodiment) FIG. 1 shows a flowchart of the entire automatic wiring process according to an embodiment of the present invention. After the process starts, the process is the same as the conventional process for nets that have only a single subnet (1 to f4 in Figure 1), and for nets that have multiple subnets as a collection of terminals that can be connected without using through wiring. When the net is decomposed into multiple subnets, a wiring route is searched and determined to connect the subnets (Fig. 1f, f).The details of this process will be described later, but this When connecting subnets through processing, a wiring route with the minimum route cost is selected. This is done for all subnets that require connection. Next, for all nets that require through wiring, the allocation to trunk channels and the allocation position of through wiring are determined (7 in Figure 1). In 9, TYP
The net through wiring allocation position of EII is 5 in Figure 1.
Other than registering the result selected in , the conventional process (first
This is the same as Figure 2 h to h6). When global wiring processing is completed for all nets, detailed wiring processing for each channel (f1o in Figure 1) is subsequently executed to end (END) the wiring within the block.Channel wiring processing is different from the conventional method. The same is true.

Hereinafter, the search for inter-subnet wiring routes (5 in FIG. 1), which is a feature of the present invention, will be described in detail.

FIG. 2 is a processing flow showing the search and determination of the optimal inter-subnet wiring route, which is the core of the present invention. First, in this process, the terminals of the subnet with connection requests are extracted (
(g1 in Figure 2), the main line information possessed by the extracted terminal is labeled (g2 in Figure 2).
Perform as shown in the figure, that is, for subnet S, 32, 1ev for the main line indicated by the dashed line in the figure from the opposite channel toward the inside of each subnet.
The zero-line process called trunk lines for ell, 1eve12, and 1eve13 searches for wiring routes for these labeled trunk lines, and the upper limit number of labels is determined in advance. In this example, the upper limit is 16ve13,
Determine which 1 level main line to be targeted for connection processing (Fig. 2 g3).
).

This is because the number of existing channels in a subnet may be smaller than the upper limit of the label. Within this range, subnet s1. Trunk lines are extracted from each of S2, and trunk pairs that are candidates for connection are identified. In the example in Figure 3, S1
= + tllll, t121.

t1311 and S2 = + t271, t281,
A total of nine combinations are obtained from t291 +. Find the route cost of the inter-subnet wiring route for all these combinations (Fig. 2 g to g7), and finally select the combination that minimizes the route cost (Fig. 2 g8)
.

Up to this point, the connection process between one subnet is completed.

As shown in FIG. 1, a similar process is executed for all subnets for which connection is requested within the net, and one wiring of a net consisting of a plurality of subnets is completed.

The following two costs were used for the wiring route cost, which is particularly important in the process of g5 in FIG. 2. One is the overlapping length in the X-coordinate direction of the trunk pair selected from the subnet, and the other is the influence of the wiring route selected as a candidate on the block size. The former is obvious, and for the latter, we introduced the evaluation formula given below as the predicted increase rate of network size.

FIG. 4 shows a connection request between subnets S1 and 32. As shown in the figure, a new trunk line IT12 is required for the connection between the trunk line pair (t121, t241), and two through wirings are required. On the other hand, the trunk pair (tllll
, t241), no new main line is required, but three through wiring locations are required. Generally, adding a new main line creates a risk of increasing the height of the block, and increasing the number of cells routed through increases the risk of increasing the width of the block due to insertion of through cells.

The important factor for the former is the required trunk line equipment, and the important factor for the latter is the number of cell columns to pass through and the allowable amount of passing wiring on each cell column. The sum of these two effects gives the predicted increase rate of the block size due to the virtually allocated wiring route. That is, the cost C is: C=A-MAX(ra-a-FT<x)・LT.

0)-In +B-LT ・KH A, B, a: Constant FT(x): Allowable amount of passing wiring KW, KH nib block width and height increase coefficient r:
It can be expressed by the following evaluation formula: Number of passing cell rows L L Length of the second trunk line X: Horizontal coordinate value.

Next, we will introduce some common examples of applying the above method.

Figure 5 shows an example of a net consisting of two subnets S and S, where Sl has a main line of Ievell and 2, and S2 has a trunk of 1e.
vell, has a trunk line of 2.3.

Therefore, there are six main line pairs to which S2 and S2 are connected. In this example, the X-coordinate overlap of the main line is (t121
, t261), (t121, t271), (
tllll.

t251), ft111, and t261), of which (tllll, t251) is the largest. On the other hand, the number of through wiring is (t121, t251
> is the minimum combination. Now, as a result of evaluating the route cost for all six trunk pairs, (tl
ll.

t251) is the minimum. At this time, Sl.

The through wiring connecting S2 is allocated within the shaded area in the figure. In the example taken here, according to the conventional process, the pair of the top trunk line t121 of the subnet S1 and the bottom trunk line t251 of the subnet S2 is the connection target, and the connection process is TYPI14, which requires a new trunk line.

According to the process of the present invention, this is the main line pair (tllll,
t251) was selected, TYPEn
It has been converted to .

FIG. 6 is an example of a net consisting of three subnets S, S2, and S3. The connection process for subnets S and S2 is the same as that shown in Fig. 5, and (tllll, t2
51) is selected, in the next connection process between subnets S and 33, the main lines to be connected in S2 are only t251 and t261, and S, S
t241, which was targeted in the second opening, is excluded from the search range. This is to avoid duplication of vertical wiring line segments (referred to as branch lines). In this way, for nets consisting of three or more subnets or subnets consisting of fewer channels than the normal search range, the search range is determined (see Figure 2, g3).
), it is necessary to avoid duplication of branch lines.

As described above, according to the present invention, in connection between each subnet of a net consisting of multiple subnets, by effectively utilizing existing trunk lines within a subnet, the number of newly added trunk lines can be minimized. can be stopped. At this time, the number of through wiring locations increases, but since through wiring has a degree of freedom in the overlapping range of trunk lines, there is almost no insertion of through cells. Therefore, the degree of chip integration can be improved.

[Effects of the Invention] According to the present invention, in global wiring processing using the building block method, connection processing between subnets can be performed without creating extra trunk lines or detours as in the conventional method.
Efficient wiring can be realized, thereby achieving high integration of large-scale logic integrated circuit chips.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall processing flow of an embodiment of the present invention;
Figure 2 is a diagram showing the processing flow of the core connection process between subnets, Figure 3 is a diagram to explain the method of labeling trunk lines within a subnet, and Figure 4 is a diagram showing the process flow of connection processing between subnets. Figure 5 is a diagram for explaining the cost of a wiring route when connecting a wire, and Figure 6 is a diagram showing an example of application of the present invention to a net composed of two subnets.
The figure shows an example of application of this detail to a net composed of three or more subnets, Figure 7 is a diagram to explain symbols used in the specification and drawings, and Figure 8 is a building block diagram. Figure 9 is a schematic diagram of a polycell type block, Figure 10 is a diagram showing one net broken down into a number of subnets, Figure 11 12 is a diagram showing a wiring route selected by a conventional method in connection processing between subnets, and FIG. 12 is a diagram showing a conventional processing flow. 1.2...Macroblocks such as ROM-RAM-3.
... Polycell type block, 4... Input/output terminal and input/output circuit area, 5... Inter-block wiring area, 6...
・Cell column, 7... Intra-block wiring area (channel),
8...Cell. Applicant's Representative Patent Attorney Takehiko Suzue Figure 2 Figure 1 Figure 7 Figure 12

Claims (2)

[Claims] (1) In a semiconductor integrated circuit device having a block configured by arranging and integrating a plurality of cell rows in which logic cells are arranged horizontally on a semiconductor chip, a wiring pattern connecting logic cells in the block is defined. When determining the approximate wiring route for the net that needs to be routed through the cell array during formation, (a) determine the terminals of the net that must be routed over the cell array to terminals that can be connected to each other without using through wiring; (b) Extract horizontal wiring segments from each of the two subnets to be connected, create a pair of wiring segments, and create a pair of wiring segments between them. (c) Repeating the route cost evaluation of (b) for multiple pairs of wiring segments, assigning passing wiring on a virtual cell column to evaluate the route cost of this wiring; 1. A wiring method for a semiconductor integrated circuit device, comprising: means for selecting and registering an optimal combination for allocating; (2) As a standard for evaluating the cost of wiring between the virtually allocated subnets, connection processing should be performed.
2. The wiring method for a semiconductor integrated circuit device according to claim 1, wherein the overlapping length of horizontal wiring lines extracted from one subnet and an evaluation value estimating the influence of the wiring route on the block area are taken into consideration. .