JP3061172B2 - Semiconductor integrated device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device, and more particularly to a semiconductor integrated device having a multi-layer wiring structure having four or more signal wiring layers.

[0002]

2. Description of the Related Art As a conventional technique relating to channel wiring of a semiconductor integrated device, for example, DA Conference (1977), pp. 298-302 [DA Conf.
erence (1977) pp 298-302].

In this prior art, signal wiring is performed using four wiring layers.
Two types are used.

[0004] The form of wiring according to the prior art will be described below with reference to the drawings.

FIG. 8 is a view showing an example of a wiring form when the four-layer wiring according to the prior art is performed, and FIGS. 9 and 10 are views for explaining the drawing of the first-layer wiring to the fourth layer. FIGS. 11 to 13 are diagrams for explaining that unwiring occurs in the wiring according to the conventional technique. 8 to 13, reference numeral 1 denotes a terminal, 2 denotes a first layer wiring, 3 denotes a second layer wiring, 4 denotes a third layer wiring, 5 denotes a fourth layer wiring, 6 denotes a through hole, 7 denotes a cell column, 8 Is a through hole.

In general, a semiconductor integrated device has
A large number of cell columns constituting circuit elements such as gates are formed, and a wiring region having a plurality of wiring layers for wiring is provided between these cell columns. In this wiring region, terminals are connected to each other. Therefore, it is configured to include various functional circuits. The terminals provided in the cell row are usually
It is provided in the lowermost layer and is drawn out to a plurality of wiring layers and connected to each other.

[0007] In the above-mentioned prior art, generally, FIG.
The above-described inter-terminal connection is performed in the form illustrated in FIG.

FIG. 8A shows an example of type I in which terminals of adjacent cell rows 7 are connected to each other. In this case, the wiring from the terminal 1 is first connected to the first layer from both sides. To the second layer through the through hole 6 through the first layer wiring 2, and to the second layer wiring 3 in the second layer.
Are connected to each other.

FIGS. 8 (b) and 8 (c) show a connection from one terminal 1 of the illustrated cell row 7 to a terminal of another cell row, not shown, beyond the other adjacent cell row. Type I
Examples of type I and type III are shown. That is, in this example, the wiring from the terminal 1 is the first
After being drawn out to the second layer wiring 3 through the layer wiring 2 and the through hole 6, it is further drawn out to the third layer through the through hole 6, and is drawn through the third layer wiring 4 to another cell (not shown). Connected to columns and the like.

FIGS. 8 (d) and 8 (e) show examples of wiring types IV and V which pass through the wiring area shown and are connected to a cell column or the like in another part not shown. In the case of the type IV example, another area (not shown) is connected to the illustrated wiring area via the third-layer wiring 4, and the connection is made by the second-layer wiring 3 in this wiring area. In the case of type V, the wiring similarly reaches the illustrated wiring area via the third-layer wiring 4 and is connected by the fourth-layer wiring 5 in this wiring area.

As described above, the four-layered wiring according to the prior art can perform wiring in five types of wiring forms. However, in this prior art, since the terminals of the cell row are usually in the lower layer, In many cases, wiring is performed using layers, and the fourth layer wiring cannot be used effectively.
That is, in the example shown in FIG.
Only the fourth layer can be used.

In the prior art, since the lead-out wiring from the terminal 1 is the first layer, the connection between the terminals is established by the wiring form of the type V, that is, by the wiring form using the fourth-layer wiring 5. If you try to do this, as shown in FIG.
It is necessary to draw a wiring from a terminal to the third layer via the second-layer wiring 3 and connect the third-layer wiring 4 with the fourth-layer wiring 5. Therefore, the wirings of the second and third layers need to be connected. There is a problem that it increases.

In the case described above, the first layer wiring 2 to which the terminal 1 is connected to the fourth layer wiring 5 can be connected by a through through hole 8 as shown in FIG. This is because the through holes are stacked in three stages, and the structure is weakened, so that the yield at the time of manufacturing is reduced, which is not preferable. Therefore, the wiring from the lowermost layer to the uppermost layer as described above is generally performed sequentially over each wiring layer. Also, even if a through-hole is used, it is not preferable because the through-holes in the second and third layers hinder other wiring.

In the prior art, the vertical path of the wiring is determined without managing the usage rate of each wiring layer. Therefore, as shown in FIG.
If they are connected, the problem arises that the terminals A cannot be connected to each other.

That is, FIG. 11 shows a case where the wiring pulled up to the upper layer is not included in the distribution for each wiring layer in the x-direction.
This is a view showing that a chip is viewed from above, in which a wiring area is provided between cells.

In the example of FIG. 11, one 2
A layer pitch 9 and two four-layer pitches 10 are arranged,
The second layer wiring 3 and the fourth layer wiring 5 in the horizontal direction can be formed in each layer at this position. Then, as shown in FIG. 11, when the terminals B are connected to each other by the second layer wiring 3, the second layer wiring cannot be secured even though the fourth layer is vacant. Second wiring
It cannot be drawn out to the fourth layer in order through the layer wiring 3 and the third layer wiring 4, and connection between the terminals A becomes impossible unless through through holes are used, and unwiring 11 occurs. Become.

FIG. 12 shows an example of a wiring across a cell row according to the prior art. In FIG. 12, the vertical path in the y direction of the wiring connecting the terminals C is defined as the usage rate of each wiring layer in the horizontal direction as the x direction. The sum is over 100%, indicating that the terminals A in the same cell row cannot be connected to each other, and the unwiring 11 occurs.

In the case of this example, when the x-direction wiring layer of the wiring connecting the terminals C is the fourth layer and the y-direction wiring layer is the first layer, the wiring is bent at the second and third layers. Occurs,
The usage rate of the vertical wiring exceeds 100%.

FIG. 13 shows an example in which a wiring having a short wiring length in the x direction is allocated to the fourth layer to connect the terminals B and the terminals C according to the prior art. In this case, in order to draw many short wires to the fourth layer, the second layer,
Accordingly, the usage rate of the third layer is also increased, so that connection between the terminals A becomes impossible, and unwiring 11 is generated.

[0020]

As described above, in the prior art, the wiring in the wiring layer (hereinafter referred to as the upper layer) three or more layers away from the terminal layer is not sufficiently considered, and the upper layer is effectively used. In addition, there is a problem that it is impossible to use an upper layer remote from the terminal layer, and that the length of the lead wiring to the upper layer increases.

An object of the present invention is to solve the above-mentioned problems of the prior art, to minimize the extension of the length of the lead wiring to the upper layer remote from the terminal layer, and to reduce the length of the lead wiring to the upper layer remote from the terminal layer by other wiring. An object of the present invention is to provide a semiconductor integrated device which does not hinder wiring, enables high-density wiring in an upper layer, and eliminates non-wiring.

Another object of the present invention is to provide a semiconductor integrated device without local congestion for each wiring layer so that the usage rate of each wiring layer does not exceed 100%.

[0023]

According to the present invention, an object of the present invention is to provide a semiconductor integrated device in which a terminal layer is a lowermost layer and a wiring layer is composed of a plurality of wiring layers of four or more layers. This is attained by arranging each wiring from the upper wiring layer to the lower wiring layer in the plurality of wiring layers in order from the wiring having a substantially longer wiring length.

[0024] The object of the present invention is to make the wiring direction of each wiring layer of the plurality of wiring layers orthogonal to the wiring direction of the adjacent wiring layer, or to draw out the wiring to an upper layer. This is achieved by using a shortest fixed path from the terminal to lead the wiring to the upper layer for shortening the length.

The fixed path mentioned here is, for example,
For each cell unit, the wiring route from the terminal to the upper layer is fixedly registered in a library or the like, and when using this cell and extracting the wiring to the upper layer, refer to this library and always use the fixed The lead-out wiring to the upper layer is performed by a path, and the path of this wiring is called a fixed path.

By allocating the long wiring to the upper layer far from the terminal layer, the wiring density of the upper layer can be increased with a small number of wirings, and the upper layer can be effectively used with the minimum number of bends or the number of through holes. can do.
In this way, when the terminal is in the lowermost layer, it is possible to reduce the occurrence of bending at both ends of the wiring as shown in FIG. It is possible to reduce the use of through through holes as shown in FIG.

That is, in general, as shown in FIG. 7A, there is a relationship between the size and the number of the trunk line lengths of the horizontal wirings, the number decreases as the trunk line length increases. Therefore, by assigning α% of the trunk line having a large length to the upper layer, β% (α <β) of the total wiring length in the horizontal direction can be assigned to the upper layer as shown in FIG. 7B.
The upper layer can be effectively used.

In the case of raising the wiring to the upper layer, the bent wiring to the upper layer is prepared in advance as a fixed path of the shortest path, and this fixed path is used to minimize the length of the bent wiring. can do.

The advantage of using such a fixed path is as follows.
For example, since the wiring from the terminal to the upper layer is automatically developed and added from the library, the terminal is located on the uppermost layer from the viewpoint of the automatic wiring program. As a result, the automatic wiring program for creating the wiring of the semiconductor integrated device according to the present invention executes the conventional program as it is, performs wiring using the second, third, and fourth wiring layers, With some terminals left in one layer, the first,
The second and third layers of wiring may be performed, and as a result, the first to fourth layers of wiring can be performed using a conventional wiring algorithm.

Another advantage of using the fixed path is that the wiring to the upper layer can be defined by the shortest path, so that interference with other wiring channels can be minimized.

Further, when allocating the vertical route, the allocation is performed so that the usage rate is equalized while determining the usage rate distribution for each wiring layer, and the wiring layer of the vertical path is determined. In this case, as shown in FIG. 8, the wiring layer of the horizontal path is also determined, so that the wiring of the upper layer can be made dense.

[0032]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor integrated device according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a flowchart for explaining a processing operation for forming a wiring of a semiconductor integrated device according to an embodiment of the present invention, FIG. 2 is a view for explaining a relationship between a wiring direction and a wiring layer,
FIG. 3 is a view for explaining the drawing of the wiring to the fourth layer by the fixed path, and FIGS. 4, 5, and 6 are views showing examples of the wiring path of the semiconductor integrated device according to the embodiment of the present invention. 3 to 6, the reference numerals in the drawings are the same as those in FIGS. 8 to 13.

First, the relationship between the wiring direction and the wiring layer will be described with reference to FIG.

As shown in FIG. 2, the relationship between the wiring direction of the circuit and the layer in the semiconductor integrated device is, for example, as shown in FIG. The relationship that the wiring layers are provided so as not to overlap in the thickness direction, and the second and fourth wiring layers are provided in the vertical direction so that the wirings in these wiring layers do not overlap in the thickness direction. It is in.

Accordingly, when wiring is performed using all the first to fourth wiring layers in order to connect the points 901 and 908 in FIG. 2, first, the points 901 to 90
2. Next, go up to the second layer by the through hole, go to the points 902 to 903 in the second layer, go up to the third layer by the through hole,
The points 903 to 904 in the layer and the connection to the points 904 to 905 are performed in the fourth layer by going up to the fourth layer in the through hole,
Thereafter, wiring up to the point 908 is performed in the reverse order.

As can be understood from the above description, it is generally impossible to perform wiring directly rising from the first layer to the third layer, and similarly, it is also impossible to perform wiring directly rising from the second layer to the fourth layer. . However, when wiring an irregular path, there are cases where it is possible as an exception.

Next, under the above-described restrictions, the object of the present invention can be achieved, that is, a high-density upper-layer wiring can be provided without disturbing other wiring, or the number of through holes can be reduced. The processing operation for creating the wiring of the semiconductor integrated device according to the embodiment of the present invention, which minimizes the following, will be described with reference to the flowchart of FIG.

(1) First, without being aware of the wiring layer,
The approximate route of the wiring is determined by the macro coordinate system (step 501).

(2) Next, the wirings in the x direction are sorted in the order of the longest wiring length in the macro coordinate system, and the longest wirings are assigned to the upper wiring layers. At this time, allocation is considered so that the usage rate of each wiring layer does not exceed 100% (steps 502 and 503).

(3) After determining the wiring layers in the x direction, the usage rate of each wiring layer is updated, and it is determined whether or not the wiring layer assignment processing has been completed for all the wiring paths in the x direction (step 504). , 505).

(4) If it is determined in step 505 that all the allocation processing has not been completed, the processing from step 503 is repeated. If all the allocation processing has been completed, x is calculated for the general route in the y direction. The position of the vertical path is determined so that the usage rate of each wiring layer in the direction does not exceed 100% (step 506).

Note that the above-described allocation processing in step 503 may be performed so as to allocate the wiring to the lower wiring layer in ascending order of the wiring length.

The semiconductor integrated device according to one embodiment of the present invention is prepared by determining the wiring in the semiconductor integrated device by the above-described processing, and has a wiring pattern without unwiring as shown in FIGS. It will be.

That is, FIG. 4 shows FIG.
The wiring is performed by raising the second layer to the utilization rate for raising the wiring to the fourth layer at the time of forming the wiring, and also raising the wiring between the terminals B to the fourth layer at the time of forming the wiring. It is a thing.

According to the embodiment of the present invention, in this case, the wiring between the terminals A can be wired using the fourth-layer wiring 5, and the semiconductor integrated device having the wiring without any unwiring can be provided. Obtainable.

FIG. 5 corresponds to a wiring example when crossing a cell column shown in FIG. 12 according to the prior art. In the example shown in FIG. 5, in the example of FIG. 12, when the x-direction wiring layer is the fourth layer and the y-direction wiring layer is the first layer, the second and third layers are bent. Since the unwiring 11 has occurred,
In consideration of this, the path in the y direction of the wiring between the terminals C can be allocated to the third layer, whereby a semiconductor integrated device having no wiring can be obtained.

FIG. 6 is a diagram showing a conventional x x shown in FIG.
FIG. 6 shows an example in which a wiring having a short wiring length in the direction is allocated to the fourth layer and the terminals B are connected to each other to prevent the wiring between the terminals A from becoming the non-wiring 11. As shown in FIG.
By allocating the wiring between the terminals and between the terminals C to the fourth layer, a semiconductor integrated device without any wiring can be obtained.

The wiring of the semiconductor integrated device according to the embodiment of the present invention is configured as described above. However, in the embodiment of the present invention, the terminals of the cell row are formed in the upper layer by using a wiring with a preset fixed path. Withdrawal means can be used together.

FIG. 3 shows a state in which the terminals of the cell row are pulled out to the fourth layer by a fixed path. The terminal at the lowest layer is connected from the first layer to the fourth layer via the shortest via each layer therebetween. Have been pulled out by distance. Such a fixed path is set in advance in correspondence with each cell in the semiconductor integrated device and stored in a library, and can be used as needed at the time of wiring creation.

In the embodiment of the present invention described above, the wiring layer has four layers.
Although described as a layer, the present invention can also be applied to a multi-layered wiring layer having more layers.

According to the above-described embodiment of the present invention, when the present invention is applied to a master slice LSI, the chip path can be shortened, the number of unwired lines can be reduced, and a custom LSI can be used. Chip area can be reduced, and cost can be reduced.

[0053]

As described above, according to the present invention, the extension of the length of the lead wiring to the upper layer remote from the terminal layer is minimized, and the lead wiring to the upper layer remote from the terminal layer obstructs other wiring. In such a case, the wiring to the upper layer can be easily performed, and the wiring in the upper layer can be formed at a high density, and no wiring can be formed.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a processing operation for creating a wiring of a semiconductor integrated device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a relationship between a wiring direction and a wiring layer.

FIG. 3 is a diagram illustrating drawing of wiring to a fourth layer by a fixed path.

FIG. 4 is a diagram showing an example of a wiring path of the semiconductor integrated device according to the embodiment of the present invention.

FIG. 5 is a diagram showing an example of a wiring path of the semiconductor integrated device according to the embodiment of the present invention.

FIG. 6 is a diagram showing an example of a wiring path of the semiconductor integrated device according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating the relationship between the size and number of main line lengths of horizontal wirings and the total wiring length ratio.

FIG. 8 is a diagram illustrating an example of a wiring configuration of a four-layer wiring according to the related art.

FIG. 9 is a diagram illustrating an example for explaining how to draw a first-layer wiring to a fourth layer;

FIG. 10 is a diagram showing another example for explaining the drawing of the first layer wiring to the fourth layer.

FIG. 11 is a diagram illustrating an example for explaining that a non-wiring occurs in a wiring according to the related art.

FIG. 12 is a diagram illustrating another example for explaining that a non-wiring occurs in a wiring according to the related art.

FIG. 13 is a diagram showing another example for explaining that a non-wiring occurs in a wiring according to the conventional technique.

[Explanation of symbols]

 Reference Signs List 1 terminal 2 first layer wiring 3 second layer wiring 4 third layer wiring 5 fourth layer wiring 6 through hole 7 cell row 8 through through hole 11 unwired

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Katsuyoshi Suzuki, Inventor 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. Kanagawa Plant (56) References JP-A-1-144649 (JP, A) JP-A-2- 222072 (JP, A)

Claims (4)

(57) [Claims] In a semiconductor integrated device in which a terminal layer is a lowermost layer and a wiring layer is composed of a plurality of wiring layers of four or more layers, an upper wiring layer having the same wiring direction in the plurality of wiring layers. From the lower wiring layer, each wiring is allocated in order from the wiring in which the wiring length of the linear portion of the wiring is substantially long , and the drawing wiring from the terminal layer to the upper layer is
Shortest path from terminal layer to upper layer through each wiring layer between them
In a semiconductor integrated device, characterized by being set. 2. The semiconductor integrated device according to claim 1, wherein the wiring direction of each of the plurality of wiring layers is different from the wiring direction of an adjacent wiring layer. 3. The semiconductor integrated device according to claim 1, wherein the wiring direction of each wiring layer of said plurality of wiring layers is orthogonal to the wiring direction of an adjacent wiring layer. 4. A semiconductor device comprising: a terminal for connecting a plurality of cells; and four or more wiring layers for connecting the terminals to each other, wherein the plurality of wiring layers have wirings in a plurality of directions. In a semiconductor integrated device in which a lower wiring layer is a terminal layer, a wiring length of a linear portion of the wiring is substantially changed from an upper wiring layer to a lower wiring layer in the plurality of wiring layers having the same wiring direction. Each wiring is allocated in order from the longest wiring, and the lead wiring from the terminal layer to the upper layer is
Shortest path from terminal layer to upper layer through each wiring layer between them
In a semiconductor integrated device, characterized by being set.