JPH0815184B2 - Wiring method for semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method for a semiconductor integrated circuit, and more particularly to an automatic wiring method.

[0002]

2. Description of the Related Art In a conventional wiring method for a semiconductor integrated circuit,
The entire chip is divided into several wiring areas, and a general wiring design for deciding which wiring area to pass through and a detailed wiring design for deciding the layout of the wiring in the wiring area are performed. Was there.

For example, as one wiring method,
In a generally known channel wiring method, a region sandwiched between cell rows is set as a wiring channel for a semiconductor integrated circuit configured by a plurality of cell rows arranged in a chip. Here, first, of the terminals connected to the same net, the terminals to be wired in the same wiring channel are determined by the schematic wiring design, and together with that, the drawing direction of each terminal is determined.

9 to 11 are layout diagrams showing the wiring method of a conventional semiconductor integrated circuit in the order of steps.

First, as shown in FIG. 9, terminals b1-b2 are provided.
The net between terminals, the net between terminals c1 and c2, the net between terminals d1 and d2, the net between terminals e1 and e2, and the net between terminals f1 and f2 all appear in only one wiring channel. The c1-c2 net is the wiring channel 21, the d1-d2 net is e1-e.
The two-net and the f1-f2 net are assigned to the wiring channel 22. Next, cell terminals a1, a2, a3, a
The net connecting 4, a5 and a6 is a wiring channel 21.
Therefore, the process of allocating the wiring of each terminal to two wiring channels is required. In this case, since six terminals are connected, these are a1-a2 and a2-a.
4, a4-a5, a5-a3, a5-a6. The connection request in this state is, as shown in FIG. 10, a connection between a1 and a2, a connection between a2 and a4, a
The connection between 5-a3 appears only in the wiring channel 21, and a5
Since the connection between -a6 appears only in the wiring channel 22,
It will be assigned to each wiring channel. Therefore, a1-a2, a2-a4, a5-a3, a5
-A6, b1-b2, c1-c2, c3-c4, d1-
The wirings between d2, e1-e2, and f1-f2 are assigned to the wiring channels as shown in FIG.
1, 32, 34, 39, 36, 35, 38, 37, 40
Is set as follows. However, the connection between a4 and a5 is
It is possible to do either of the wiring channels 21 or 22. In this case, the number of line segments assigned to the wiring channel 21 is two at the most concentrated position and the number of line segments is three at the wiring channel 22, so that it is assigned to the line segment 33 of the wiring channel 21 in order to avoid wiring congestion. Further, the drawing directions 51 to 67 are set for the respective terminals according to the allocation to the wiring channels.

Next, the detailed wiring layout is determined for each wiring channel by the detailed wiring design in accordance with the allocation to the wiring channels and the terminal drawing direction. Usually, in this detailed wiring design, different wiring layers are used so that horizontal wirings called trunk lines and vertical wirings called branch lines can intersect each other. For example, consider a case where the first wiring layer is used for the main wiring and the second wiring layer is used for the branch wiring. here,
In FIG. 10, paying attention to the terminal e1 and the terminal a6, since the terminal e1 exists immediately above the terminal a6, the trunk line connected to the branch line drawn from the terminal e1 is the branch line drawn from the terminal a6. Must be wired above the main line connecting to. Such restrictions on the allocation of trunk lines are called upper and lower restrictions, and in the channel wiring method, trunks are allocated according to the upper and lower restrictions. However, focusing on the connection between the terminals a2 and a4 of the wiring channel 21 and the connection between the terminals b1 and b2, since the terminal a2 exists immediately above the terminal b2, the main line between the terminals a2 and a4 is It is necessary to wire above the trunk line between b1 and b2. On the other hand, since the terminal b1 is immediately above the terminal a4, the trunk line between the terminals b1 and b2 needs to be wired above the trunk line between the terminals a2 and a4. Therefore, there is a contradiction in the upper and lower constraints. In such a case, it is necessary to divide one of the two main lines to resolve the contradiction of the vertical constraint, and the detailed wiring result as shown in FIG. 11 is obtained.

As a result, if one of the trunk lines is divided and wired in this way, one more wiring track is required.

[0008]

In such a conventional semiconductor integrated circuit wiring method, as shown in FIG. 11, when there is a contradiction in the upper and lower restrictions of terminals in the wiring channel, one trunk line is divided. Then, the contradiction of the upper and lower constraints is resolved, and the wiring is performed, which requires a large number of wiring tracks in the wiring channel region, which causes a problem of increasing the chip area.

[0009]

A wiring net for connecting cells of a semiconductor integrated circuit having a plurality of cell rows arranged on a semiconductor substrate and wiring channels provided between the cell rows is provided. A means for allocating in the wiring channel by a schematic wiring design, a means for searching for a loop that causes a vertical constraint by the wiring net, and a wiring net allocation by changing the lead terminal of the vertical constraint loop to the adjacent wiring channel side A means for changing, a means for comparing the congestion degree of the wiring in the wiring channel with the congestion degree before the allocation change, and when the congestion degree is increased by the comparison means, the detailed wiring design is performed by the wiring net before the allocation change, When the congestion degree does not change, a means for performing detailed wiring design by the wiring net after the allocation change is included.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a process diagram for explaining a first embodiment of the present invention, and FIGS. 2 to 5 are layout diagrams showing a process sequence for explaining the first embodiment of the present invention.

First, as shown in FIG. 2, cell columns 11 and 1
The wiring request for the arrangement having the wirings 2 and 13 and the wiring channels 21 and 22 is assigned to the wiring channel of each net and the drawing direction of each terminal is determined by the schematic wiring design 101 shown in FIG. This schematic wiring design 101 can be processed by a generally known method. That is,
In FIG. 2, a net between terminals b1 and b2, terminals c1 and c1
Net between two, net between terminals d1-d2, terminals e1-e
Since the net between two and the net between terminals f1 and f2 both appear in only one wiring channel, they are respectively b1 and b2.
Between the net and the net between c1 and c2 is on the wiring channel 21,
d1-d2 net, e1-e2 net, f1-f2
The internet is assigned to the wiring channel 22. Next, since the net connecting the cell terminals a1, a2, a3, a4, a5, a6 extends over the wiring channels 21 and 22, it is necessary to assign the wiring of each terminal to the two wiring channels. In this case, since six terminals are connected, they are connected to a1-a2, a2-a4, a4-a5, a5-a.
It is divided into 5 two-terminal pairs of 3, a5-a6. As shown in FIG. 3, the connection request in this state is such that the connection between a1 and a2, the connection between a2 and a4, and the connection between a5 and a3 appear only in the wiring channel 21, and the connection between a5 and a6 is the wiring channel. It will only appear at 22 and will be assigned to each wiring channel. Therefore, a1-a2, a2-
a4, a5-a3, a5-a6, b1-b2, c1-c
2, c3-c4, d1-d2, e1-e2, f1-f2
The wiring between the wiring channels is assigned to the wiring channels as shown in FIG.
Line segment 31, 32, 34, 39, 36, 35, 3 shown in
It looks like 8, 37, 40. However, the connection between a4 and a5 can be made in either of the wiring channels 21 or 22. In this case, the number of line segments assigned to the wiring channel 21 is two at the most concentrated position, and the number of line segments is three at the wiring channel 22, so that the line segment is assigned to 33 in order to avoid wiring congestion. Further, according to the allocation to the wiring channels, the drawing directions 51 to 67 are set for the respective terminals.

Next, with respect to the allocation to the wiring channels set by the rough wiring design 101, the upper and lower constraint loop search 102 of FIG. 1 searches the respective wiring channels 21 and 22 for the main line in which the vertical constraint conflicts. If there is a main line in which a vertical constraint is inconsistent in the wiring channel, a terminal connected to the main line is extracted. Of these terminals, it is determined whether or not a net having the same potential exists in the adjacent wiring channel region. If there is a net of the same potential, the terminal extraction direction change 103 changes the terminal extraction direction to the adjacent wiring channel side. Further, the wiring net assignment change 104 changes the assignment of the nets to the wiring channels in accordance with the direction in which the terminals are pulled out. For example, referring to FIG. 2, since there is a vertical constraint between the trunk line between the terminals a2 and a4 and the trunk line between the terminals b1 and b2, is there a net of the same potential in the adjacent wiring channel 22? As a result, a net having the same potential as that of a2-a4 exists, so that the drawing direction of the terminal a4 is changed to the adjacent wiring channel 22 side. Due to this change, the allocation of each trunk line is changed as shown in FIG.

Next, according to the wiring congestion degree evaluation 105, it is compared whether or not the maximum wiring congestion portion in each wiring channel is larger than that before the wiring net allocation is changed. Channel area allocation is adopted, and the detailed wiring design 106 determines the detailed wiring shape for each wiring channel according to the allocation to the wiring channel and the terminal drawing direction. This detailed wiring can also be performed by a conventionally known method. That is, as shown in FIG. 5, in the wiring channel 21, the main line between the terminals a2-a5 is the terminal b1- in accordance with the vertical constraint.
Wiring above the main line between b2 and wiring channel region 2
In 2, the trunk line between the terminals e1 and e2 is wired above the trunk line between a5 and a6, and the trunk line between a5 and a6 and the trunk line between a4 and a5 are wired above the trunk line between fa1 and f2.

When the wiring congestion degree evaluation 105 shows that the wiring congestion degree of the wiring channel increases, the wiring net before the allocation change is adopted to perform the detailed wiring design.

FIG. 6 is a process diagram for explaining the second embodiment of the present invention, and FIG. 7 is a layout diagram for explaining the second embodiment of the present invention.

As shown in FIG. 6 and FIG. 7, in the present embodiment, not only the means for changing the drawing direction of the terminal of the cell in the process of the first embodiment, but also the equipotential terminals in the cell are adjacent to each other. A means 107 is added to the wiring channel for selecting a terminal from which a wire can be drawn out and changing the drawing direction. By this means, a terminal whose wire drawing direction determined by a rough wiring design is not in an adjacent wiring channel is added. On the other hand, if there is a terminal that can be pulled out to an adjacent wiring channel that is equipotential to that terminal, the allocation to the wiring channel area can be changed to avoid an increase in the wiring channel caused by a contradiction of vertical restrictions. it can.

FIG. 8 is a layout diagram obtained by a conventional wiring method without using the wiring method of this embodiment.
If you divide the main line so as to eliminate the contradiction of the upper and lower constraints,
It can be seen that the wiring length becomes longer than that of the present embodiment.

[0019]

As described above, according to the present invention, it is possible to avoid an increase in area due to a vertical constraint when wiring to a wiring channel, and it is possible to reduce a chip area of a semiconductor integrated circuit. Further, it is possible to prevent an increase in the wiring length due to the wiring of the main line being divided, and to shorten the wiring length.

[Brief description of drawings]

FIG. 1 is a process drawing for explaining a first embodiment of the present invention.

2A and 2B are layout diagrams showing the order of steps for explaining the first embodiment of the present invention.

3A and 3B are layout diagrams showing the order of steps for explaining the first embodiment of the present invention.

FIG. 4 is a layout diagram showing the order of steps for explaining the first embodiment of the present invention.

FIG. 5 is a layout diagram showing the order of steps for explaining the first embodiment of the present invention.

FIG. 6 is a process drawing for explaining the second embodiment of the present invention.

FIG. 7 is a layout diagram for explaining the second embodiment of the present invention.

FIG. 8 is a layout diagram according to a conventional wiring method for comparison with the second embodiment of the present invention.

FIG. 9 is a layout diagram showing the order of steps for explaining a conventional semiconductor integrated circuit wiring method.

FIG. 10 is a layout diagram showing the order of steps for explaining a conventional semiconductor integrated circuit wiring method.

FIG. 11 is a layout diagram showing the order of steps for explaining a conventional semiconductor integrated circuit wiring method.

[Explanation of symbols]

11, 12, 13 Cell rows 21, 22 Wiring channels 31, 32, 33, 34, 35, 36, 37, 38, 3
9,40 Wiring channel assignment line segments 51, 52, 53, 54, 55, 56, 57, 58, 5
9, 60, 61, 62, 63, 64, 65, 66, 67
Terminal lead-out direction 71 First layer wiring 72 Second layer wiring 73 First layer-second layer through hole

Claims (1)

[Claims] 1. A wiring net for connecting the cells of a semiconductor integrated circuit having a plurality of cell rows arranged on a semiconductor substrate and a wiring channel provided between the cell rows is designed by a schematic wiring design. Means for allocating within the wiring channel, means for searching for a loop that causes a vertical constraint by the wiring net, and means for changing the wiring net allocation by changing the lead terminal of the vertical constraint loop to the adjacent wiring channel side. , A means for comparing the congestion degree of the wiring in the wiring channel with the congestion degree before the allocation change, and when the congestion degree is increased by the comparison means, the detailed wiring design is performed by the wiring net before the allocation change so that the congestion degree does not change. And a means for performing detailed wiring design by the wiring net after the allocation change, the semiconductor integrated circuit wiring method.