JPH0571137B2 - - Google Patents

Info

Publication number
JPH0571137B2
JPH0571137B2 JP18815785A JP18815785A JPH0571137B2 JP H0571137 B2 JPH0571137 B2 JP H0571137B2 JP 18815785 A JP18815785 A JP 18815785A JP 18815785 A JP18815785 A JP 18815785A JP H0571137 B2 JPH0571137 B2 JP H0571137B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP18815785A
Other versions
JPS6247148A (en
Inventor
Akihiro Sueda
Hitoshi Kondo
Original Assignee
Tokyo Shibaura Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co filed Critical Tokyo Shibaura Electric Co
Priority to JP18815785A priority Critical patent/JPH0571137B2/ja
Publication of JPS6247148A publication Critical patent/JPS6247148A/en
Publication of JPH0571137B2 publication Critical patent/JPH0571137B2/ja
Anticipated expiration legal-status Critical
Application status is Expired - Lifetime legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
JP18815785A 1985-08-27 1985-08-27 Expired - Lifetime JPH0571137B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18815785A JPH0571137B2 (en) 1985-08-27 1985-08-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18815785A JPH0571137B2 (en) 1985-08-27 1985-08-27

Publications (2)

Publication Number Publication Date
JPS6247148A JPS6247148A (en) 1987-02-28
JPH0571137B2 true JPH0571137B2 (en) 1993-10-06

Family

ID=16218750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18815785A Expired - Lifetime JPH0571137B2 (en) 1985-08-27 1985-08-27

Country Status (1)

Country Link
JP (1) JPH0571137B2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007043049A (en) 2004-12-20 2007-02-15 Matsushita Electric Ind Co Ltd Cell, standard cell, placement method using standard cell, standard cell library, and semiconductor integrated circuit
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
SG10201608214SA (en) * 2008-07-16 2016-11-29 Tela Innovations Inc Methods for cell phasing and placement in dynamic array architecture and implementation of the same
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same

Also Published As

Publication number Publication date
JPS6247148A (en) 1987-02-28

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term