JP2001127162A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a layout method of a semiconductor integrated circuit for reducing influences of a cross talk. SOLUTION: A minimum interval is made so as to pass only one wiring therebetween, and power supply (VDD, VSS) wirings at a minimum line width are disposed in a vertical axial direction in n layers and in a horizontal axial direction in (n+1) layers to form a lattice-like shield, which is wired with a signal line. Furthermore, when (n-1) layers and (n+2) layers are used in a multilayer wiring of three layers or more, the power supply wiring is disposed in the signal line of the (n+1) layer, to shield vertically. Incidentally, a wiring may be made in the (n+1) and (n-1) layers in the vertical direction and in the n and (n+1) layers in the horizontal direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a layout of a semiconductor integrated circuit for preventing interference between signal lines.

[0002]

2. Description of the Related Art In a parallel wiring, if the parallel running distance between adjacent signal lines becomes longer, the signal lines are more likely to be interfered by adjacent signal lines and crosstalk occurs. By surrounding it, interference was prevented.

[0003]

In today's deep sub-micron world, the distance between the wirings is becoming narrower, so that even if the length of the parallel wirings is not very long, the adjacent wirings are strongly affected by interference. There is a tendency.

On the other hand, in general, a design method (Back Annota) that extracts delay information from layout data, performs an actual delay simulation, and feeds back to the design.
(hereinafter, abbreviated as BA)), but the influence of the narrowing of the wiring interval has appeared.

Here, as a general signal line, there is a wiring between buffers in a block diagram shown in FIG. ba1, b
a2, bb1, bb2, bc1, bc2 are buffers, and wires w1, w2, w3 connected from ba1 to ba2, bb1 to bb2, and bc1 to bc2 are parallel wires having a long wire length. Buffers ba1, bb of this input stage
1, (b) the opposite phase signal and (b) the same phase signal as shown in FIG. FIG. 9 shows the result of examining the transmission time of the signal from bb1 to bb2. The vertical axis is the signal transmission time, the horizontal axis is the interval between the wirings, (A) gives the opposite phase signal, (B) gives the same phase signal, and (C) shows FIG. 7 (b). As shown in the block diagram of FIG. 8, a fixed potential wiring is inserted between three signal lines w1, w2, and w3, and the opposite phase signal of FIG. 7A is a simulation result based on delay information obtained from layout data of the circuit of the block diagram illustrated in FIG.

In the graph of FIG. 9, while there is a large difference between the measurement results of (A) and (B) and the simulation result of (D), when a fixed potential wiring is inserted between the signal lines of (C), A value very close to (D) is obtained. This is because, in the actual delay simulation, the delay information is extracted as the delay information due to the resistance component and the capacitance component of the wiring, and the delay due to the dynamically changing crosstalk is not reflected. If the delay time varies depending on the input signal pattern as described above, it does not hold as BA, and the operation of the actual circuit cannot be guaranteed as before.

For these reasons, a layout which is not affected by delay time fluctuation due to crosstalk, or a new B
A method needs to be constructed.

However, if the wiring width and the wiring interval are increased to solve this problem, the merit of miniaturization is small, and the shield wiring using the fixed potential wiring is effective in preventing interference between the wirings. Is one factor that increases

[0009]

In order to solve this problem, a semiconductor integrated circuit according to the present invention prevents interference from an adjacent wiring by sandwiching one signal line between a power supply and a ground wiring. Is used as a power source.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the invention according to claim 1, wherein the vertical wirings 100 to 102, 110 and 111 are, for example, one-layer metal, and the horizontal wirings 200 to 202 and 21
0, 211, and 212 are, for example, two-layer metals, and 500
Reference numerals 507 indicate vias connecting the first-layer metal and the second-layer metal. Here, the wirings 110, 111, 210 to 212 are signal lines, and the signal lines are separated by a minimum distance, and the power supply wirings 100, 102, 200, 202 having the minimum line width and the ground wiring 10 are formed.
1, 201 are alternately wired, and one signal line is always sandwiched between a power supply line and a ground line. As described above, the power supply wiring, the signal wiring, the ground wiring, the signal wiring, and the power supply wiring are repeated in one direction, and the signal lines are surrounded by the three-dimensional mesh-shaped power supply and ground wirings, thereby preventing interference between the signal lines. . It is to be noted that the wiring may be made of a two-layer metal in the vertical direction and a one-layer metal in the horizontal direction. In addition, the width of the power supply wiring and the ground wiring, and the distance between the power supply wiring and the signal wiring are arbitrary.

FIG. 2 is a block diagram of the invention according to claim 3, which is obtained by adding one wiring layer to FIG. 150,
151, 160, 161 are, for example, one-layer metal, 250,
251, 260 and 261 are, for example, two-layer metal, 350,
351, 360 and 361 are, for example, three-layer metals,
60, 161, 260, 261, 360, and 361 are signal lines; 151, 251, and 351 are power supply lines;
Reference numerals 0 and 350 are ground wirings. Like the first and second layers, the three layers are formed by repeating power supply lines, signal lines, and ground lines. In addition, one layer of power supply wiring or ground wiring is disposed below the three layers of signal lines so as to prevent interference between upper and lower wirings. In the four-layer structure, the power supply wiring, the signal line, and the ground wiring are similarly repeated in the vertical direction of three layers, and the power supply wiring or the ground wiring is arranged below the signal line. This repetition corresponds to at least three or more layers. Note that wiring may be performed in two or four layers in the vertical direction and one or three layers in the horizontal direction. In addition, the width of the power supply wiring and the ground wiring, and the distance between the power supply wiring and the signal wiring are arbitrary.

Next, as a second embodiment of the present invention, an example of application to inter-block wiring will be described.

FIG. 3 shows an arrangement of mesh-like fixed potential wirings between blocks. Where 600-608
Are, for example, power supply wirings, and 700 to 707 are, for example, ground wirings, each of which is connected by a via to form a mesh-shaped fixed potential wiring network. A broken line 800 between the fixed potential wirings
The connection between the blocks is made using .about.815.

FIG. 4 is a flow chart of a process for producing a semiconductor integrated circuit for preventing interference between signal lines due to mesh-like fixed potential wiring.
It comprises four steps: provisional placement of functional blocks, automatic wiring of signal lines, generation of mesh-like fixed potential wiring, and compaction processing.

First, provisional arrangement of functional blocks created in advance is performed (1). At this time, the functional blocks are sufficiently opened to secure a wiring area. Next, automatic wiring of signal lines is performed in the space between the functional blocks at a wiring pitch twice as large as the minimum wiring pitch determined by the design rule (2). This secures a space in which wiring can be added between signal lines. Next, wiring of, for example, one layer of aluminum in the x-axis direction and wiring of, for example, two layers of aluminum in the y-axis direction are arranged between the signal lines at a wiring pitch of four times the minimum wiring pitch, and vias are formed at intersections of each other. Perform wiring in a mesh form (3). This is connected to the main power supply wiring. In addition, since wiring is performed at four times the wiring pitch, the space on both sides of the signal line is in a state where only one of the spaces is buried. Similarly, a mesh-like wiring is formed so as to fill the space, and the signal line is surrounded by a mesh-like fixed potential wiring by connecting to a main ground wiring. Thereafter, compaction is performed on the obtained layout at a pitch determined by a design rule to reduce the distance between the functional block and the wiring and optimize the layout area (4).

FIG. 5 is a layout diagram when the wiring efficiency is prioritized. A signal line whose delay is predicted to be large is specified in advance, and wiring is first performed from the specified signal line to an appropriate position between blocks, for example, a center between blocks, and is surrounded by a fixed potential wiring network. Thereafter, other unspecified signal lines are routed in the vacant wiring regions WA1 to WA3 outside the mesh-shaped fixed potential wiring network, so that the area can be reduced.

FIG. 6 shows a configuration of a logic circuit using the layout configuration of the present invention. Here, the logic circuit 1 constitutes an inverter, and the logic circuit 2 constitutes a buffer. The logic circuit component is constituted by a single-layer metal, and connections between cells are wired in two or more layers. Further, the positions of the input / output terminals, input 1, output 1, input 2, and output 2 raised to the two-layer metal are arranged at positions where one or more fixed potential wirings enter between the input / output terminals. If the number of fixed potential wirings between input and output is two or more, one
Leave enough space for the signal lines to pass through. That is, when n fixed potential wirings and (n-1) signal lines (where n is 1 or more) pass between the input / output terminals and are arranged in parallel, when one cell is placed in parallel, one cell is placed between cells. The cell width is determined so that the fixed potential wiring passes. If a standard cell is created with such a configuration and a block layout is performed using this cell library, a mesh-like fixed potential wiring network can be formed on the cell, so that the power supply can be more stabilized throughout the semiconductor integrated circuit. Can do it.

[0019]

According to the present invention, since one signal line is sandwiched between a power supply line and a ground line, interference between adjacent signal lines can be prevented and a dynamic delay factor can be suppressed. The operation of a real circuit can be guaranteed by simulation without being established.

Further, although it contributes to an increase in the area similarly to the conventional shield, unlike the conventional shield using a single fixed potential wiring, the power supply wiring and the ground wiring are used. Since the number of ground wirings increases, the internal power supply voltage can be stabilized.

The wiring direction is fixed in one direction, and the power supply line, the signal line, the ground line, the signal line, and the power supply line are repeated, and the number of layers is increased so that the lines intersect vertically. By providing a shield, the internal power supply voltage can be stabilized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a mesh-shaped fixed potential wiring according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a multilayer mesh fixed potential wiring according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of inter-block wiring and mesh-shaped fixed potential wiring;

FIG. 4 is a flow chart of generating a mesh-shaped fixed potential wiring.

FIG. 5 is a configuration diagram of inter-block wiring and mesh-shaped fixed potential wiring when wiring efficiency is prioritized.

FIG. 6 is a configuration diagram of a cell that facilitates insertion of a fixed potential wiring.

FIG. 7 is a circuit diagram having a general parallel wiring;

FIG. 8 is a diagram showing a signal transmission time of the circuit of FIG. 6;

FIG. 9 is a table showing correspondence between input signal patterns and graphs.

[Explanation of symbols]

100 to 102, 110, 111, 150, 151, 1
60, 161 n-layer metal wiring 200 to 202, 210, 211, 250, 251, 2
60,261 n + 1 layer metal wiring 500-507 Via 350,351,360,361 n + 2 layer metal wiring B1-B3 Functional block 600-608,650-657 Power supply wiring 700-707,750-756 Ground wiring WA1-WA3 Wiring area ba1, ba2, bb1, bb2, bc1, bc2 Buffer w1 to w3 Signal line

Claims (3)

[Claims] In a semiconductor integrated circuit having at least two or more wiring layers, a single power supply line, a signal line, a ground line, a minimum wiring width in one direction, and a minimum wiring interval at equal intervals in one wiring layer. A semiconductor having a layout structure in which signal lines are repeatedly arranged, and one power supply wiring, signal line, ground wiring, and signal line are repeatedly arranged in another wiring layer in the vertical direction. Integrated circuit. 2. The semiconductor integrated circuit according to claim 1, wherein in a semiconductor integrated circuit having at least three or more wiring layers, a power supply wiring, a signal line, and a ground wiring are vertically repeated in an upper layer with respect to a lower wiring layer. circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the distance between the signal lines and the power supply and ground lines and the line width are changed.