JP2006179554A - Semiconductor circuit device and its design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor circuit device where enlargement of a transition time difference of gate output with installation of shield wiring to signal wiring can be suppressed. <P>SOLUTION: A ratio βp/βn of a gain coefficient of pMOS and nMOS of a drive CMOS inverter 10 is set to a large value exceeding 1.0. Both shield wirings are installed in parallel to signal wiring LO at an installation mode having deviation so that wiring length Ll of low potential shield wiring SL becomes long and wiring length Lh of high potential shield wiring SH becomes short. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor circuit device having a complementary output transistor and having a drive gate for driving a signal wiring provided with a shield wiring, and a design method thereof.

  A semiconductor circuit device constituted by a CMOS (Complementary Metal Oxide Semiconductor) logic circuit includes a logical product (AND), a logical sum (OR), an inverter (negative: NOT), an exclusive logical product (NAND), and an exclusive logical sum ( NOR), a CMOS gate such as a flip-flop is formed as a basic structural unit. That is, the semiconductor circuit device is mainly composed of various CMOS gates and signal wirings connecting the gates. The CMOS gate includes a CMOS transistor which is a complementary transistor in which a pMOS which is a first conductivity type field effect transistor and an nMOS which is a second conductivity type field effect transistor are combined.

  Each CMOS gate arranged in the CMOS logic circuit generally has substantially the same transition time of rising / falling of its output potential Vout, and its logic threshold Vinv (potential at which the input potential Vin and the output potential Vout are equal). ) Is set in the vicinity of an intermediate potential ((Vdd−Vss) / 2) between the high potential Vdd and the low potential Vss. Normally, with such a setting, the transition time of the output potential Vout of the CMOS gate is the fastest, and the noise resistance at the logic level is also maximized.

  Incidentally, the driving capability (gain) of the MOS transistor with respect to the load is generally represented by a gain coefficient β. The gain coefficient β is expressed by the following equation using the channel width W, channel length L, gate oxide film dielectric constant ε, gate oxide film thickness tox, and carrier mobility μ of the MOS transistor.

[Equation 1]

β = μ · (W / L) · (ε / tox)

Electrons that are carriers of nMOS and vacancies that are carriers of pMOS have different carrier mobility μ, and the carrier mobility of nMOS is usually about 2 to 3 times the carrier mobility of pMOS. If the channel length L is the same, the gate width Wp of the pMOS needs to be 1.5 to 2 times the gate width Wn of the nMOS in order to make the rise / fall transition times substantially equal. become. The ratio βp / βn of the pMOS gain coefficient βp and the nMOS gain coefficient βn of such a CMOS transistor is in the range of 0.5 to 1.0. FIG. 8 shows the DC transfer characteristics of a typical CMOS inverter having such a setting.

  By the way, along with miniaturization and high speed operation of semiconductor circuit devices, problems such as delay fluctuations and malfunctions due to the influence of crosstalk noise between signal wirings connecting CMOS gates have become problems. Conventionally, as a countermeasure against such crosstalk noise, a shield wiring having a fixed potential is provided alongside a signal wiring of a basic gate.

Although the installation of such shield wiring is certainly effective in reducing the influence of crosstalk noise, the parasitic capacitance of the signal wiring increases in accordance with the installation. Further, the increase in the parasitic capacitance of the signal wiring may increase the transition time difference between the rise and fall of the gate output.

  For example, when the potential of the shield wiring is set to the low potential Vss, the potential difference between the signal wiring and the shield wiring is enlarged when the gate output potential transitions (starts up) from the low potential Vss to the high potential Vdd. The wiring load increases due to the parasitic capacitance between the wirings. On the other hand, at the transition (falling) of the gate output potential from the high potential Vdd toward the same potential (low potential Vss) as the shield wiring, there is no increase in wiring load due to the parasitic capacitance. For this reason, there is a difference in wiring load between when the gate output is raised and when it is lowered. Therefore, even if the CMOS gate is designed so that the transition time difference is within an allowable range by itself, there is a possibility that a transition time difference that cannot be allowed may occur when connected to a signal wiring with a shield wiring. .

  The present invention has been made in view of such a situation, and a problem to be solved is a semiconductor circuit device capable of suppressing an increase in a transition time difference of a gate output accompanying installation of a shield wiring to a signal wiring. It is to provide.

  Hereinafter, means for solving the above-described problems and the operation thereof will be described.

<Means>
The invention according to claim 1 is a semiconductor circuit device, wherein a ratio βp / βn between a gain coefficient βp of the first conductivity type field effect transistor and a gain coefficient βn of the second conductivity type field effect transistor is A drive gate for driving a signal wiring having a complementary output transistor set to exceed 1.0, and a gate connected to the signal wiring and held at a potential higher than the logic threshold of the output transistor A high-potential shield line, and a low-potential shield line that is also provided alongside the signal line and held at a potential lower than the logic threshold, and a parasitic between the high-potential shield line and the signal line Both shield wirings are arranged in a biased manner so that the capacitance Cp is smaller than the parasitic capacitance Cg between the low potential shield wiring and the signal wiring. And of the subject matter.

  According to a second aspect of the present invention, in the semiconductor circuit device according to the first aspect, a complementary input transistor provided in a driven gate driven together with the signal wiring by the drive gate is replaced with an electric field of the first conductivity type. The gist is that the ratio βpi / βni between the gain coefficient βpi of the effect transistor and the gain coefficient βni of the second conductivity type field effect transistor is less than 0.5.

  The invention according to claim 3 is a semiconductor circuit device, wherein the ratio βp / βn between the gain coefficient βp of the first conductivity type field effect transistor and the gain coefficient βn of the second conductivity type field effect transistor is A driving gate having a complementary output transistor set to be less than 0.5 and driving a signal wiring; and a driving gate that is provided adjacent to the signal wiring and is held at a potential higher than a logical threshold value of the driving gate. A high-potential shield line, and a low-potential shield line that is also provided alongside the signal line and held at a potential lower than the logic threshold, and a parasitic between the high-potential shield line and the signal line That the shield wirings are arranged in a biased manner so that the capacitance Cp is larger than the parasitic capacitance Cg between the low potential shield wiring and the signal wiring. And effect.

According to a fourth aspect of the present invention, there is provided the semiconductor circuit device according to the third aspect, wherein a complementary input transistor provided in a driven gate driven by the drive gate together with the signal wiring is connected to an electric field of the first conductivity type. The gist is that the ratio βpi / βni between the gain coefficient βpi of the effect transistor and the gain coefficient βni of the second conductivity type field effect transistor exceeds 1.0.

  According to a fifth aspect of the present invention, there is provided a drive gate having a complementary output transistor for driving a signal wiring, and a shield wiring provided along with the signal wiring, the potential being higher than a logic threshold value of the output transistor of the driving gate. And a low-potential shield wiring that is also a shield wiring and held at a potential lower than the logic threshold value, the method comprising: The ratio βp / βn between the gain coefficient βp of the first conductivity type field effect transistor and the gain coefficient βn of the second conductivity type field effect transistor, and the parasitic capacitance Cp between the high potential shield wiring and the signal wiring The gist is to set the parasitic capacitance Cg between the low-potential shield wiring and the signal wiring in correlation with each other.

  According to a sixth aspect of the present invention, there is provided a drive gate having a complementary output transistor for driving a signal wiring, and a shield wiring provided along with the signal wiring, the potential being higher than a logic threshold value of the output transistor of the driving gate. And a low-potential shield wiring that is also a shield wiring and held at a potential lower than the logic threshold value, the method comprising: The ratio βp / βn of the gain coefficient βp of the first conductivity type field effect transistor and the gain coefficient βn of the second conductivity type field effect transistor is set to exceed 1.0, and the high potential shield wiring Both parasitic capacitances Cp between the signal wirings are smaller than parasitic capacitances Cg between the low potential shield wirings and the signal wirings. As its gist that to have a bias in the arrangement mode of Rudo wiring.

  According to a seventh aspect of the present invention, in the method for designing a semiconductor circuit device according to the sixth aspect, a complementary input transistor provided in a driven gate driven together with the signal wiring by the drive gate is used as the first conductive. The gist of the invention is to set the ratio βpi / βni between the gain coefficient βpi of the type field effect transistor and the gain coefficient βni of the second conductivity type field effect transistor to be less than 0.5.

  According to an eighth aspect of the present invention, there is provided a drive gate having a complementary output transistor for driving a signal wiring, and a shield wiring provided along with the signal wiring, the potential being higher than a logic threshold value of the output transistor of the driving gate. And a low-potential shield wiring that is also a shield wiring and held at a potential lower than the logic threshold value, the method comprising: The ratio βp / βn of the gain coefficient βp of the first conductivity type field effect transistor and the gain coefficient βn of the second conductivity type field effect transistor is set to be less than 0.5, and the high potential shield wiring Both parasitic capacitances Cp between the signal wirings are larger than the parasitic capacitances Cg between the low potential shield wirings and the signal wirings. As its gist that to have a bias in the arrangement mode of Rudo wiring.

  According to a ninth aspect of the present invention, in the method for designing a semiconductor circuit device according to the eighth aspect, a complementary input transistor provided in a driven gate driven by the drive gate together with the signal wiring is provided with a first conductive property. The gist of the invention is to set the ratio βpi / βni between the gain coefficient βpi of the type field effect transistor and the gain coefficient βni of the second conductivity type field effect transistor to exceed 1.0.

<Action>
In the configuration according to claim 1 and the design method according to claim 6, the complementary output transistor of the drive gate that drives the signal wiring has the gain coefficient βp of the first conductivity type field effect transistor and the second output transistor. The ratio βp / βn to the gain coefficient βn of the conductive field effect transistor is set to a large value exceeding the normal setting range (0.5 to 1.0). In such an output transistor, the output potential rises quickly and falls slowly.

  On the other hand, a high-potential / low-potential shield line is provided alongside a signal line driven by a drive gate having such an output transistor. Parasitic capacitance is generated between the signal wiring and shield wiring arranged close to each other, but here, by arranging both shield wirings in a biased manner, the high potential shield wiring side and the low potential are arranged. The parasitic capacitance is different from the shield wiring.

  When the output potential of the drive gate is raised, the wiring load is increased due to the parasitic capacitance Cg on the low potential shield wiring side, and when it is lowered, the wiring caused by the parasitic capacitance Cp on the high potential shield wiring side is generated. An increase in load will occur. Here, since the parasitic capacitance Cp on the high potential shield wiring side is smaller than the parasitic capacitance Cg on the low potential shield wiring side, the wiring load at the time of raising the output potential of the drive gate is larger, and the wiring at the time of falling is set. The load becomes smaller. Therefore, the delay due to the wiring load increases when the output potential at which the output transistor operates at high speed is increased, and the delay due to the wiring load decreases when the output potential at which the output transistor operates at low speed is decreased. Therefore, the influence of the output characteristics of the output transistor and the influence of the parasitic capacitance of the shield wiring are interpolated with each other on the rise / fall transition time, and the transition time difference is reduced as a whole. become.

  Further, in the configuration according to claim 2 and the design method according to claim 7, the output from the output transistor of the drive gate in which the gain coefficient ratio βp / βn is set to a large value exceeding 1.0 as described above. However, the gain coefficient ratio βpi / βni is set to a small value lower than 0.5 and is input to the complementary input transistor of the driven gate.

  Here, in the CMOS transistor in which the gain coefficient ratio βp / βn (βpi / βni) is a large value exceeding 1.0, the logic threshold is biased to the low potential side, so that the noise margin on the high potential side is large. The noise margin on the low potential side is reduced. On the other hand, in the CMOS transistor in which the gain coefficient ratio βp / βn (βpi / βni) is set to a small value lower than 0.5, the logic threshold is biased to the high potential side, so that the noise margin on the high potential side is small. The noise margin on the low potential side increases.

  Here, since the noise margin of the output transistor is large on the high potential side, the fluctuation of the output potential input as noise to the input transistor does not occur much. On the other hand, since the noise margin of the output transistor is small on the low potential side, the output transistor may cause a large output potential fluctuation with respect to a slight fluctuation of the input potential.

  In that respect, in the above configuration and design method, the noise margin on the low potential side where the output potential fluctuation of the output transistor that is input as noise is likely to occur is increased, and the noise margin on the high potential side that is not so is increased. A gain coefficient ratio βpi / βni is set. Therefore, the noise resistance of the inter-gate wiring structure including the driving gate, the driven gate, and the signal wiring is effectively improved.

  In the configuration according to claim 3 and the design method according to claim 8, the gain coefficient ratio βp / βn of the output transistor of the drive gate for driving the signal wiring is set to the normal set range (0.5 to 1). 0.0) is set to a small value. In such an output transistor, the output potential falls quickly and rises slowly.

On the other hand, here, the parasitic capacitance Cp on the high potential shield wiring side is made larger than the parasitic capacitance Cg on the low potential shield wiring side, and the wiring load when the output potential of the drive gate is lowered is larger. The wiring load is made smaller. Therefore, when the output potential at which the output transistor operates at a high speed falls, the delay due to the wiring load increases, and when the output potential at which the output transistor operates at a low speed increases, the delay due to the wiring load decreases. Therefore, even in the above configuration and design method, the influence of the output characteristics of the output transistor and the influence of the parasitic capacitance of the shield wiring are interpolated with each other with respect to the rise / fall transition time. Will reduce the transition time difference.

  In the configuration according to claim 4 and the design method according to claim 8, the output transistor of the drive gate in which the gain coefficient ratio βp / βn is set to a small value lower than 0.5 as described above is low. The noise margin is increased on the potential side, and the output potential does not vary much. On the other hand, since the noise margin is small on the high potential side, the output potential of the output transistor is likely to fluctuate.

  In that respect, in the above configuration and design method, the noise margin on the high potential side where the output potential fluctuation of the output transistor that is input as noise is likely to occur is increased, and the noise margin on the low potential side that is not so small is decreased. A gain coefficient ratio βpi / βni is set. Therefore, the noise resistance of the inter-gate wiring structure including the driving gate, the driven gate, and the signal wiring is effectively improved.

  As described above, the influence of the output characteristics of the output transistor and the influence of the wiring load of the signal wiring on the rise / fall transition time interact, and the gates including the drive gate and signal wiring As a whole wiring structure, preferable transition time characteristics can be obtained. Therefore, as in the design method according to claim 5, by setting the gain coefficient ratio βp / βn of the output transistor and the parasitic capacitances Cp and Cg of both shield wirings in association with each other, each can be set independently. Thus, a semiconductor circuit device having suitable characteristics that cannot be obtained can be configured.

  According to the semiconductor circuit device and the design method of the present invention, it is possible to suppress an increase in the transition time difference of the gate output accompanying the installation of the shield wiring on the signal wiring.

  Hereinafter, an embodiment embodying the present invention will be described in detail with reference to FIGS.

  FIG. 1 shows an example of an inter-gate wiring structure provided in the semiconductor circuit device of this embodiment. Here, a case will be described as an example where the driving side and driven side gates are both CMOS inverters composed of CMOS transistors which are complementary transistors.

  As shown in the figure, on both sides of the signal wiring LO connecting the driving CMOS inverter 10 and the driven CMOS inverter 11 driven thereby, the high potential shield wiring SH held at the high potential Vdd and the low potential Vss are provided. The held low potential shield wiring SL is also provided. In this inter-gate wiring structure, the high potential shield wiring SH is disposed on the side close to the driving CMOS inverter 10, and the low potential shield wiring SL is disposed on the side close to the driven CMOS inverter 11. Here, the arrangement of both shield lines is biased so that the wiring length Lh of the high-potential shield wiring SH is shorter than the wiring length Ll of the low-potential shield wiring SL (Lh <Ll). Yes.

FIG. 2A shows a circuit diagram of the driving CMOS inverter 10. As shown in the figure, the drive CMOS inverter 10 is configured as a very general CMOS inverter. That is, the drive CMOS inverter is configured to include two MOS transistors, pMOS and nMOS. The pMOS gate Gp and the nMOS gate Gn are connected to each other as an input of the inverter, and the pMOS drain Dp and the nMOS drain Dn are connected to each other as an output of the inverter. Further, the source Sp of the pMOS is connected to the voltage wiring of the high potential Vdd, and the source Sn of the nMOS is connected to the voltage wiring of the low potential Vss. Incidentally, the driven CMOS inverter 11 has the same basic structure as that of the driving CMOS inverter 10.

  Since such a CMOS inverter has a single-stage CMOS structure composed entirely of one CMOS transistor, the relationship of “CMOS inverter” = “input transistor” = “output transistor” is established.

  In the drive CMOS inverter 10 employed in the inter-gate wiring structure, the ratio βp / βn of the gain coefficient βp of the pMOS and the gain coefficient βn of the nMOS has a setting range (0.5 to 1.. 0), which has a biased output characteristic (for example, βp / βn≈2.0). Such a gain coefficient ratio βp / βn can be set by making the gate width of the pMOS sufficiently larger than that of the nMOS side. It can also be carried out by a manufacturing process method such as channel doping, or by increasing the logic threshold of the pMOS by applying a bias voltage to the substrate or well.

  FIG. 2B shows the DC transfer characteristics of the drive CMOS inverter 10. As shown in the figure, the logic threshold value Vinv of the drive CMOS inverter 10 is a potential biased toward the low potential Vss side from the intermediate potential (= (Vdd−Vss) / 2) between the high potential Vdd and the low potential Vss. In such a driving CMOS inverter 10, the output potential Vout from the high potential Vdd to the low potential Vss falls slowly, and the output potential Vout from the low potential Vss to high potential Vdd rises at a high speed. That is, the drive CMOS inverter 10 is formed so that the gate output transition time difference is increased.

  The characteristics of the drive CMOS inverter 10 and the biases of the wiring lengths Lh and Ll of the high potential shield wiring SH and the low potential shield wiring SL described above are set in correlation with each other. Details of such settings will be described below.

  FIG. 3 shows the relationship between the input potential Vin and the output potential Vout of the drive CMOS inverter 10 in the inter-gate wiring structure configured as described above. In the figure, a state where the signal wiring LO is not connected, that is, an input / output relationship of a single gate and a state where the signal wiring LO is connected, that is, an input / output relationship including wiring, are shown together.

  Parasitic capacitance is generated between the signal line LO and the high potential shield line SH and the low potential shield line SL provided adjacent to each other. The parasitic capacitance Cg between the signal line LO on the side of the low-potential shield line SL having a longer wiring length Ll is the parasitic capacity Cp between the signal line LO on the side of the high-potential shield line SH having a shorter wiring length Lh. (Cp <Cg).

  Here, when the output potential Vout of the driving CMOS inverter 10 rises, the wiring load is increased by the parasitic capacitance Cg on the low potential shield wiring SL side where the potential difference from the signal wiring LO is enlarged. When the output potential Vout is lowered, the wiring load is increased by the parasitic capacitance Cp on the high potential shield wiring SH side where the potential difference from the signal wiring LO is increased. As described above, in this inter-gate wiring structure, the parasitic capacitance Cg is larger than the parasitic capacitance Cp (Cg> Cp). For this reason, the wiring load becomes larger when the output potential Vout is raised than when the output potential Vout is lowered.

On the other hand, as shown in the figure, in the drive CMOS inverter 10 alone, the output potential Vou
The transition time is shorter at the time of start-up than when t is lowered. Therefore, the operation of the drive CMOS inverter 10 has a greater delay due to the wiring load when the output potential Vout is raised at high speed, and the transition time Thl at the rise and the transition time Thl at the fall The difference is reduced. Here, if the gain coefficient ratio βp / βn and the parasitic capacitances Cp and Cg on the high potential shield line SH side and the low potential shield line SL side are appropriately adjusted, the transition time difference between the rise and fall of the output potential Vout ( (Thl−Tlh) can be within an allowable range.

  As described above, according to the present embodiment, the gain coefficient ratio βp / βn and the parasitic capacitance Cp of each shield wiring are reduced while reducing the influence of the crosstalk noise through the installation of the high potential shield wiring SH and the low potential shield wiring SL. , Cg are set in correlation with each other, the expansion of the transition time difference of the gate output accompanying the installation is suitably suppressed. Incidentally, in the case where a CMOS gate constituted by a plurality of stages of CMOSs is employed as the drive gate of the inter-gate wiring structure instead of the drive CMOS inverter 10, if the output characteristics of the output transistor are set similarly, Similar effects can be obtained.

  By the way, if the gain coefficients βp and βn of both the pMOS and nMOS are increased in order to increase the speed and drive capability, the leakage current increases. On the other hand, in the inter-gate wiring structure, only the gain coefficient βp of the pMOS of the drive CMOS inverter 10 is increased to increase the speed, and the nMOS side has a low leakage current. In a CMOS having a common gate, if either the pMOS side or the nMOS side has a low leakage current, the overall leakage current can be kept low. Therefore, in the inter-gate wiring structure, an increase in leakage current can be suppressed while speeding up.

  In the inter-gate wiring structure, noise resistance is improved by setting the output characteristics of the driven CMOS inverter 11 in accordance with the output characteristics of the driving CMOS inverter 10 as described above.

  When the gain coefficient ratio βp / βn is large, the logic threshold Vinv is biased toward the low potential Vss, so that the noise margin on the high potential Vdd side of the CMOS transistor is large and the noise margin on the low potential Vss side is small (see FIG. 2 (B)). On the contrary, when the gain coefficient ratio βp / βn is small, the logic threshold Vinv is biased toward the high potential Vdd side, the noise margin on the high potential Vdd side of the CMOS transistor is small, and the noise on the low potential Vss side is small. The margin increases (FIG. 4).

  Therefore, in the drive CMOS inverter 10 in which the gain coefficient ratio βp / βn is set to be large, there is a possibility that the output potential Vout may fluctuate due to a slight noise input when it is at the low potential Vss with a small noise margin.

  Further, in the inter-gate wiring structure, when the wiring length L1 of the low potential shield wiring SL is long and the potential of the signal wiring LO is the high potential Vdd, the wiring load is high and the propagation of noise in the signal wiring LO is high. Will be suppressed. For this reason, when the potential of the signal line LO is the high potential Vdd, noise is less likely to be input to the driven CMOS inverter 11 than when the potential is the low potential Vss.

Therefore, in the driven CMOS inverter 11, a noise margin is intentionally made small on the high potential Vdd side where noise is hardly input, and a noise margin on the low potential Vss side where the output potential Vout of the driving CMOS inverter 10 is likely to fluctuate. If it is increased, the noise resistance can be effectively increased. That is, in the inter-gate wiring structure, the ratio βpi between the pMOS gain coefficient βpi and the nMOS gain coefficient βni of the driven CMOS inverter 11.
/ Βni is set to a value lower than 0.5 where the noise margin on the low potential Vss side is expanded. Incidentally, in the case where a CMOS gate constituted by a plurality of stages of CMOSs is employed as the driven gate of the inter-gate wiring structure instead of the driven CMOS inverter 11, if the output characteristics of the input transistor are set similarly, Noise resistance can be effectively improved.

  The same function as that of the inter-gate wiring structure can also be obtained by the inter-gate wiring structure configured as shown in FIG.

  The inter-gate wiring structure shown in the figure includes a drive CMOS inverter 10 ′ in which the gain coefficient ratio βp / βn is set to a small value (for example, 0.3) lower than 0.5. In this case, the logic threshold Vinv of the driving CMOS inverter 10 ′ is a potential biased toward the high potential Vdd side from the intermediate potential ((Vdd−Vss) / 2) between the high potential Vdd and the low potential Vss. In the driving CMOS inverter 10 ′, the output potential Vout from the high potential Vdd to the low potential Vss falls rapidly, and the output potential Vout from the low potential Vss to the high potential Vdd rises slowly.

  In such a case, the wiring length Lh of the high potential shield wiring SH is made longer than the wiring length Ll of the low potential shield wiring SL (Lh> Ll), and the parasitic capacitance Cp on the high potential shield wiring SH side is reduced to the low potential shield wiring. By making it larger than the parasitic capacitance Cg on the SL side, the same function as the inter-gate wiring structure of FIG. 1 can be achieved. That is, the delay due to the wiring load of the signal wiring LO becomes larger when the output potential Vout falls faster, and the delay due to the wiring load of the signal wiring LO becomes smaller when the output potential Vout rises slower. The increase in the transition time difference of the output potential Vout due to the installation of the shield wiring is similarly suppressed.

  In such a case, the gain coefficient ratio βpi / βni of the driven CMOS inverter 11 ′ is set to the drive CMOS inverter 10 ′ in which the gain coefficient ratio βp / βn is set to a small value lower than 0.5. By setting it to a large value exceeding 1.0, noise resistance can be improved in the same manner.

  Incidentally, in this inter-gate wiring structure, the pMOS side of the drive CMOS inverter 10 ′ has a configuration in which the leakage current is lower than that of the nMOS side. Therefore, also in such an inter-gate wiring structure, it is possible to suppress an increase in leakage current while achieving high speed.

  According to this embodiment described above, the following effects can be obtained.

  (1) By setting the gain coefficient ratio βp / βn of the driving CMOS inverter and the parasitic capacitances Cp and Cg of the shield wirings in correlation with each other, the influence of the crosstalk noise is reduced while the shield is reduced. Expansion of the transition time difference of the gate output accompanying the installation of the wiring can be suitably suppressed. In addition, a signal can be transmitted at a higher speed than when only a shield wiring that is held at a high potential Vdd or a low potential Vss is provided.

  (2) Noise tolerance can be effectively improved by setting the gain coefficient ratio βpi / βni of the driven CMOS inverter in accordance with the gain coefficient ratio βp / βn of the driving CMOS inverter.

  (3) Since the speed is increased by increasing the gain coefficient of only one of the pMOS and nMOS of the driving CMOS inverter, an increase in leakage current can be suppressed.

  The above embodiment can also be implemented with the following modifications.

  In the above embodiment, the noise resistance of the entire inter-gate wiring structure is improved by setting the gain coefficient ratio βpi / βni of the driven CMOS inverter in accordance with the gain coefficient ratio βp / βn of the driving CMOS inverter. . Even if such setting is not performed, if sufficient noise tolerance is ensured, the setting of the gain coefficient ratio βpi / βni on the driven CMOS inverter side can be omitted. Even in this case, if the ratio βp / βn of the drive CMOS inverter and the parasitic capacitances Cp and Cg of the shield wiring are set appropriately in correlation with each other, the transition time difference of the gate output accompanying the installation of the shield wiring is increased. Can be suitably suppressed.

  In the above embodiment, the magnitude relationship between the parasitic capacitances Cp and Cg on the high potential shield wiring SH side and the low potential shield wiring SL side is set by making the wiring lengths Lh and Ll of both shield wirings different. The setting can also be performed by other methods.

  For example, the magnitude relationship between the parasitic capacitances Cp and Cg can be set by adjusting the fixed potential of each shield wiring. In the inter-gate wiring structure shown in FIG. 6, the drive CMOS inverter 10 and the driven CMOS inverter 11 have the same configuration as that in FIG. In other words, the drive CMOS inverter 10 has a large gain coefficient ratio βp / βn exceeding 1.0, and is an inverter that can operate at high speed when the output potential Vout rises.

  Here, in this inter-gate wiring structure, the high potential shield wiring SH and the low potential shield wiring SL are similarly disposed on both sides of the signal wiring LO. That is, here, the wiring lengths of both shield wirings are the same. However, in this inter-gate wiring structure, the high potential shield wiring SH is set to a potential Vhigh (Vdd> Vhigh> Vinv) lower than the high potential Vdd. By lowering the potential of the high potential shield wiring SH, the parasitic capacitance Cp on the high potential shield wiring SH side is reduced. Therefore, even in such a case, an increase in the transition time difference of the gate output accompanying the installation of the shield wiring is similarly suppressed.

  In addition, the magnitude relationship between the parasitic capacitances Cp and Cg can be determined by biasing the interval between the signal wiring and the high-potential / low-potential shield wiring or by changing the material characteristics of both shield wirings. Can be set.

  In the above embodiment, the gain coefficient ratio βp / βn and the parasitic capacitances Cp and Cg are correlated by setting gates other than inverters such as AND, OR, NAND, NOR, and flip-flops on the driving side and the driven side. The same can be applied to the inter-gate wiring structure provided in either one or both. In short, if the inter-gate wiring structure having a complementary output transistor and a drive gate for driving the signal wiring, by applying the correlation setting in a manner similar to or equivalent to the above-described embodiment, Expansion of the transition time difference of the gate output accompanying the installation of the shield wiring can be suitably suppressed.

(Other configuration examples)
The above-described correlation setting of the gain coefficient ratio βp / βn and the parasitic capacitances Cp and Cg can also be used for purposes other than reducing the transition speed difference between the rise and fall of the output potential Vout.

For example, the above correlation setting can be used for the purpose of speeding up only one of the rising / falling of the output potential Vout. To increase the speed by specializing only the rise of the output potential Vout, the gain coefficient ratio βp / βn of the output transistor of the drive CMOS inverter is set to a large value exceeding 1.0, as shown in FIG. In addition, this can be realized by making the parasitic capacitance Cp on the high potential shield wiring side sufficiently larger than the parasitic capacitance Cg of the low potential shield wiring. Also, specializing only the fall of the output potential Vout,
The gain coefficient ratio βp / βn of the output transistor of the driving CMOS inverter is set to a small value less than 0.5, and the parasitic capacitance Cp on the high potential shield wiring side is compared with the parasitic capacitance Cg of the low potential shield wiring. This can be achieved by making it sufficiently small. That is, the magnitude relationship between the parasitic capacitances Cp and Cg so that the wiring load on the speed-up side becomes smaller through the setting of the biased gain coefficient ratio βp / βn of the rise and fall of the output potential Vout. If this is set, it is possible to further speed up the speed-up side.

  In this way, the influence of the output characteristics of the output transistor and the influence of the wiring load of the signal wiring on the rise / fall transition time interacts, so that the gates including the drive gate and the signal wiring are connected. It is possible to obtain preferable transition time characteristics as the entire wiring structure. In other words, by setting the output transistor gain coefficient ratio βp / βn and the parasitic capacitances Cp and Cg of both shielded wirings in association with each other, it has suitable characteristics that cannot be obtained by setting each of them alone. A semiconductor circuit device having an inter-gate wiring structure can be configured.

The schematic diagram which shows the inter-gate wiring structure about one Embodiment of this invention. The circuit diagram which shows the (A) circuit structure of the drive CMOS inverter of the wiring structure between the gates, and the graph which shows (B) direct-current transfer characteristic. The time chart which shows the operation | movement aspect of the CMOS inverter. The graph which shows the direct-current transfer characteristic of the CMOS inverter which has a characteristic contrary to a drive CMOS inverter. The schematic diagram of the other structural example of the wiring structure between gates of the embodiment. The schematic diagram of the further another structural example of the wiring structure between gates of the embodiment. The schematic diagram which shows the wiring structure between the gates about another structural example. The graph which shows the direct-current transfer characteristic of a general CMOS inverter.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10,10 '... Driving CMOS inverter (driving gate having complementary output transistor) 11, 11' ... Driven CMOS inverter (driven gate having complementary input transistor), LO ... Signal wiring, SH ... High potential shield Wiring, SL: Low potential shield wiring, Cp: Parasitic capacitance between high potential shield wiring and signal wiring, Cg: Parasitic capacitance between low potential shielding wiring and signal wiring, βp: Gain coefficient of pMOS of driving CMOS inverter, βn ... NMOS gain coefficient of the driving CMOS inverter, βpi... PMOS gain coefficient of the driven CMOS inverter, .beta.ni... NMOS gain coefficient of the driven CMOS inverter.

Claims (9)

A complementary output transistor in which the ratio βp / βn of the gain coefficient βp of the first conductivity type field effect transistor and the gain coefficient βn of the second conductivity type field effect transistor exceeds 1.0 is provided. A driving gate for driving the signal wiring;
A high-potential shield wiring that is provided alongside the signal wiring and held at a potential higher than the logic threshold of the output transistor;
A low potential shield wiring that is also provided in the signal wiring and held at a potential lower than the logic threshold;
With
Arrangement method in which both shielded wirings are biased such that a parasitic capacitance Cp between the high potential shield wiring and the signal wiring is smaller than a parasitic capacitance Cg between the low potential shield wiring and the signal wiring. A semiconductor circuit device comprising: Complementary input transistors provided on the driven gate driven by the drive gate together with the signal wiring are represented by a gain coefficient βpi of the first conductivity type field effect transistor and a gain coefficient of the second conductivity type field effect transistor. 2. The semiconductor circuit device according to claim 1, wherein a ratio [beta] pi / [beta] ni to [beta] ni is set to be less than 0.5. A complementary output transistor in which the ratio βp / βn of the gain coefficient βp of the first conductivity type field effect transistor and the gain coefficient βn of the second conductivity type field effect transistor is set to be less than 0.5 A driving gate for driving the signal wiring;
A high-potential shield wiring that is provided alongside the signal wiring and held at a potential higher than a logical threshold value of the gate;
A low potential shield wiring that is also provided in the signal wiring and held at a potential lower than the logic threshold;
With
Arrangement in which both shield wirings are biased so that the parasitic capacitance Cp between the high potential shield wiring and the signal wiring is larger than the parasitic capacitance Cg between the low potential shield wiring and the signal wiring. A semiconductor circuit device, wherein the semiconductor circuit device is arranged in an aspect. Complementary input transistors provided on the driven gate driven by the drive gate together with the signal wiring are represented by a gain coefficient βpi of the first conductivity type field effect transistor and a gain coefficient of the second conductivity type field effect transistor. 4. The semiconductor circuit device according to claim 3, wherein a ratio [beta] pi / [beta] ni to [beta] ni is greater than 1.0. A driving gate having a complementary output transistor for driving the signal wiring; a shield wiring provided alongside the signal wiring; and a high-potential shield wiring held at a potential higher than the logic threshold value of the output transistor; A method of designing a semiconductor circuit device comprising a low-potential shield wiring that is a wiring and is held at a potential lower than the logic threshold,
A ratio βp / βn between a gain coefficient βp of the first conductivity type field effect transistor of the output transistor and a gain coefficient βn of the second conductivity type field effect transistor, and the high potential shield wiring and the signal wiring And a parasitic capacitance Cp between the low-potential shield wiring and the signal wiring is set in correlation with each other. A driving gate having a complementary output transistor for driving the signal wiring; a shield wiring provided alongside the signal wiring; and a high-potential shield wiring held at a potential higher than the logic threshold value of the output transistor; A method of designing a semiconductor circuit device comprising a low-potential shield wiring that is a wiring and is held at a potential lower than the logic threshold,
The ratio βp / βn between the gain coefficient βp of the first conductivity type field effect transistor of the output transistor and the gain coefficient βn of the second conductivity type field effect transistor is set to exceed 1.0, and There is a bias in the arrangement of both shield wirings so that the parasitic capacitance Cp between the high potential shield wiring and the signal wiring is smaller than the parasitic capacitance Cg between the low potential shield wiring and the signal wiring. A method for designing a semiconductor circuit device, comprising: Complementary input transistors provided on the driven gate driven by the drive gate together with the signal wiring are represented by a gain coefficient βpi of the first conductivity type field effect transistor and a gain coefficient of the second conductivity type field effect transistor. 7. The method of designing a semiconductor circuit device according to claim 6, wherein the ratio βpi / βni to βni is set to be less than 0.5. A driving gate having a complementary output transistor for driving the signal wiring; a shield wiring provided alongside the signal wiring; and a high-potential shield wiring held at a potential higher than the logic threshold value of the output transistor; A method of designing a semiconductor circuit device comprising a low-potential shield wiring that is a wiring and is held at a potential lower than the logic threshold,
The ratio βp / βn between the gain coefficient βp of the first conductivity type field effect transistor of the output transistor and the gain coefficient βn of the second conductivity type field effect transistor is set to be less than 0.5, and There is a bias in the arrangement of both shield wirings so that the parasitic capacitance Cp between the high potential shield wiring and the signal wiring is larger than the parasitic capacitance Cg between the low potential shield wiring and the signal wiring. A method for designing a semiconductor circuit device, comprising: Complementary input transistors provided on the driven gate driven by the drive gate together with the signal wiring are represented by a gain coefficient βpi of the first conductivity type field effect transistor and a gain coefficient of the second conductivity type field effect transistor. 9. The method for designing a semiconductor circuit device according to claim 8, wherein the ratio βpi / βni with respect to βni is set to exceed 1.0.

Images