JP2007180671A - Level shifter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shifter circuit which converts a signal Vin of a low voltage power supply system into a signal Vout of a high voltage power supply system, and which has transistor elements of compact size and therefore consumes low power, and also is hardly affected by power noises. <P>SOLUTION: The level shifter circuit comprises a MOS inverter 1 connected between a high voltage power supply VDD and a ground GND of the high voltage power supply system and receiving the signal Vin of the low voltage power supply system and a feedback circuit 2 connected to an output Vout of the MOS inverter 1, and the feedback circuit 2 is characterized in that the feedback circuit 2 is connected to a high voltage system ground GND voltage when an output of the MOS inverter 1 changes to a low level signal and the feedback circuit 2 reaches a high impedance when the output of the MOS inverter 1 changes to a high level signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a repel shifter circuit in a CMOS semiconductor integrated circuit.

  FIG. 3 shows an example of a CMOS repel shifter circuit that has been widely used in semiconductor integrated circuits. The source terminals of the two P-type MOS transistors P1 and P2 are connected to the power supply voltage VDD2, and the source terminals of the two N-type MOS transistors N1 and N2 are connected to the ground GND2. Among these transistors, the drains of a pair of P-type and N-type MOS transistors P1 and N1 are connected to each other, and further connected to the gate of another PMOS transistor P2. Further, the drains of another set of P-type and N-type MOS transistors P2 and N2 are connected to each other, and are connected to the gate of the PMOS transistor P1 of the set of transistors. An input signal of the level shifter circuit is supplied to the gate of the NMOS transistor N1 through a non-inverting buffer that operates with another power supply (voltage VDD1, ground GND1), and with an inverting buffer that operates with another power supply (voltage VDD1, ground GND1). To the gate of another NMOS transistor N2. In this example, the drains of the other pair of P-type and N-type MOS transistors P2 and N2 serve as outputs, and an output voltage is supplied to the outside through an inverter composed of P-type and N-type MOS transistors P3 and N3. ing.

  The operation of the level shifter circuit will be described. When the input signal of the circuit is at "L" level, the crossed pair transistors N1 and P2 are turned off and the transistors N2 and P1 are turned on, so that the output is "L". On the other hand, when the input signal is at “H” level, N1 and P2 of the transistor pair are turned on and N2 and P1 of the transistor pair are turned off, so that the output is “H”. As a result, the signals in the power supply systems VDD1 and GND1 are level-shifted to output signals in the power supply systems VDD2 and GND2. The reason why the output voltage is supplied to the outside from the output signal via the inverter is to eliminate the influence on the level shifter circuit from the outside.

  In general, a P-type transistor is cross-coupled in this way and used as an active load. The cross-coupled portion constitutes a positive feedback, and the input is level-converted and output by increasing the gain in this portion.

  In a general circuit, when the number of constituent elements increases, in order to invert the cross-coupled output, an N-type transistor that receives an input needs to have a large driving capability. That is, the ability to move a large amount of charge in a short time is required. For this reason, an increase in element size (area) and an increase in current consumption have been problems. In addition, due to the cross coupling, the characteristics when the power supply voltage is lowered tend to deteriorate because the transistor does not invert suddenly at a certain power supply voltage. Regarding the noise, there is a problem that the N-type transistor for inverting the output is easily affected by power supply noise, the drain-source voltage is lowered, and the output malfunctions.

Known documents are shown below.
Japanese Patent No. 3592262 Japanese Patent No. 3058387

  An object of the present invention is to provide a level shifter circuit in which the size of a transistor element is small, power consumption is small, and it is difficult to be affected by power supply noise.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and the invention according to claim 1 is a level shifter circuit for converting a low voltage power supply system signal into a high voltage power supply system signal, and grounding the high voltage power supply and the high voltage power supply system. It consists of a MOS inverter that inputs a low-voltage power supply signal connected in between and a feedback circuit connected to the output of the MOS inverter. The feedback circuit is high when the output of the inverter changes to a low-level signal. The level shifter circuit is characterized in that it is connected to the voltage system ground voltage and becomes high impedance when the output of the inverter changes to a high level signal.

  According to a second aspect of the present invention, in a level shifter circuit for converting a low voltage power supply system signal into a high voltage power supply system signal, a first P-type MOS transistor having a source connected to the high voltage power supply and the high voltage power supply An inverter formed by connecting the drain of the first N-type MOS transistor whose source is connected to the ground voltage of the system to which the signal of the low voltage power supply system is gate-inputted, and a gate connected to the output of the inverter and the source The drain of the second P-type MOS transistor connected to the high-voltage power supply is connected to the drain and gate of the second N-type MOS transistor, and the source of the second NMOS transistor is set to the ground voltage of the high-voltage power supply system. The gate of the third NMOS transistor connected to the drain of the inverter is connected to the drain of the second PMOS transistor. The source of the third NMOS transistor is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected to the ground voltage of the high voltage system, and the low voltage power supply system is connected to the gate of the fourth NMOS transistor. The level shifter circuit is characterized by comprising a feedback circuit to which the above signal is input.

  The invention according to claim 3 of the present invention is the level shifter circuit according to claim 2, wherein the first PMOS transistor and the first NMOS transistor forming the inverter are cascode-connected. is there.

  A fourth aspect of the present invention is the level shifter circuit according to the second or third aspect, wherein the second PMOS transistor is cascode-connected.

  Since the level shifter circuit of the present invention is configured as described above, it can be a level shifter circuit in which the size of the transistor element is small, the power consumption is low, and the power supply noise is hardly affected.

  The best mode for carrying out the present invention will be described below.

  FIG. 1 is a circuit diagram showing an example of a level shifter circuit of the present invention. The level shifter circuit of the present invention is premised on a level shifter circuit that converts a signal of a low voltage power supply system into a signal of a high voltage power supply system. A feedback circuit 2 connected to the output of the MOS inverter and a MOS inverter 1 for inputting a signal Vin of the low voltage power supply system connected between the high voltage power supply VDD and the ground GND of the high voltage power supply system. The circuit 2 is connected to the high voltage system ground voltage GND when the output of the inverter 1 changes to a low level signal, and becomes high impedance when the output of the inverter 1 changes to a high level signal.

  When the input signal Vin is a low level signal “L”, the output of the inverter is a high level signal “H”. When Vin changes from L to H, the output of the inverter tries to change from H to L. At this time, the output is connected to GND by the feedback circuit. For this reason, the output becomes L even if the ground voltage of the inverter fluctuates due to noise or the like. Or since Vin is a low-voltage power supply system, even if the elements constituting the inverter are turned on at the same time, the output is similarly L. Therefore, the size of the inverter element connected to the ground can be reduced as compared with the prior art. When the input signal changes from H to L, the output of the inverter is H and the feedback circuit is high impedance, so that the output is held at H.

  FIG. 2 is a circuit diagram showing another example of the level shifter circuit of the present invention. The level shifter circuit of the present invention is premised on a level shifter circuit that converts a signal of a low voltage power supply system into a signal of a high voltage power supply system. The level shifter circuit includes an inverter 3 and a feedback circuit 4.

  The inverter 3 includes a first P-type MOS transistor (cascode connection of MP1 and MP2) whose source is connected to the high-voltage power supply VDD and a first N-type MOS whose source is connected to the ground voltage GND of the high-voltage power supply system. The drains of the transistors (cascode connection of MN1 and MN2) are connected to each other, and a low-voltage power supply system signal Vin is input to each gate.

  In the feedback circuit 4, the drain of the second P-type MOS transistor (cascode connection of MP3 and MP4) whose gate is connected to the output of the inverter 3 and whose source is connected to the high-voltage power supply is the second N-type MOS transistor. The drain and gate of MN3 are connected, the source of the second NMOS transistor MN3 is connected to the ground voltage GND of the high voltage power supply system, and the gate of the third NMOS transistor MN4 whose drain is connected to the output of the inverter 1 is the first. 2 connected to the drains of the PMOS transistors MP3 and MP4, the source of the third NMOS transistor MN4 is connected to the drain of the fourth NMOS transistor MN5, and the source of the fourth NMOS transistor MN5 is the high-voltage ground voltage GND. Connected to the gate of the fourth NMOS transistor MN5 Signal Vin of the voltage power supply system is inputted.

  In this example, the first PMOS transistors (MP1, MP2), the first NMOS transistors (MN1, MN2), and the second PMOS transistors (MP3, MP4) forming the inverter are respectively cascode-connected. Yes.

  When the input signal Vin is a low level signal “L”, the first PMOS transistors (MP1, MP2) are turned on (conductive state), and the first NMOS (MN1, MN2) transistors are turned off (high impedance state). The output of the inverter is a high level signal “H”. In the feedback circuit, the second P-type MOS transistor (cascode connection of MP3 and MP4) is turned off, and the fourth NMOS transistor MN5 is turned off, so that the impedance between the power supply and the ground becomes high with respect to the output of the inverter. Yes.

  When the input signal Vin changes from L to H, the output of the inverter changes to become L. In this case, in the feedback circuit, the second P-type MOS transistor is turned on quickly because the gate changes to L, and H (power supply voltage) is supplied to the drain and gate of the second NMOS transistor MN3. Then, the third NMOS transistor MN4 whose gate is connected to this line is turned on, and the fourth NMOS transistor MN5 whose Vin is input to the gate is turned on. Then, the ground voltage is immediately connected to the output of the inverter. Therefore, even if the output of the first NMOS (MN1, MN2) transistor of the inverter does not immediately become L due to noise or the like, this can be achieved. As a result, it is not necessary to increase the size of the first NMOS as in the prior art, and the current consumption can be reduced.

  As another example, when the input signal Vin changes from L to H and the output of the inverter changes to become L, Vin is a low-voltage power supply system, and therefore, the first PMOS transistor (MP1, MP2) and The first NMOS (MN1, MN2) transistors are turned on simultaneously, and a through current may flow. In this case as well, the feedback circuit has an effect of suppressing current consumption and noise, but the effect of suppression is further increased by cascode connection of the inverter. That is, as a result of the cascode connection, the through current decreases with respect to the same power source. If the ground voltage varies due to noise, the output of the inverter also varies. In this case, since the first PMOS transistor is on, a large variation current flows through the first NMOS transistor. . However, since the first NMOS (MN1, MN2) transistors are in cascode connection, the fluctuation current can be suppressed. The same applies to the third and fourth NMOS transistors of the feedback circuit, and the fluctuating current can be suppressed synergistically.

  When the second P-type MOS transistors are cascode-connected, the current when they are turned on to drive the second and third NMOS transistors can be suppressed.

  As described above, in the level shifter circuit of the present invention, the element size can be reduced, the current consumption can be reduced, and the influence of power supply noise can be reduced. In the above example shown in FIG. 2, it has been confirmed by simulation that the through current of the order of several mA is suppressed to ½ or less. The total circuit element size was reduced to about 2/3 as compared with the conventional example shown in FIG. Further, in the conventional method, it is necessary to increase the N-type transistor size of N1 and N2 in FIG. 3, but in FIG. 2 having an output feedback loop, the N-type transistor size is about 1/3 as compared with this. We were able to. In addition, since no cross-couple is used, operation with a lower power supply voltage than in the conventional type is possible. In addition, since the influence of power supply noise is reduced, there is an effect that malfunction can be prevented. In the simulation, a noise reduction effect of about 8 to 10 dB was confirmed.

It is the circuit diagram which showed one example of the level shifter circuit of this invention. It is the circuit diagram which showed the other example of the level shifter circuit of this invention. It is an example of the conventional repel shifter circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Inverter 2 ... Feedback circuit 3 ... Inverter 4 ... Feedback circuit

Claims (4)

  In a level shifter circuit for converting a low voltage power supply system signal into a high voltage power supply system signal, a MOS inverter for inputting a low voltage power supply system signal connected between the high voltage power supply and the ground of the high voltage power supply system, and a MOS inverter The feedback circuit is connected to the high voltage system ground voltage when the inverter output changes to a low level signal, and the inverter output changes to a high level signal. A level shifter circuit characterized by high impedance. In a level shifter circuit that converts a low voltage power supply system signal to a high voltage power supply system signal,
A low voltage power supply system formed by connecting a drain of a first P-type MOS transistor having a source connected to a high voltage power supply and a first N-type MOS transistor having a source connected to a ground voltage of the high voltage power supply system An inverter to which the signal of
The drain of the second P-type MOS transistor whose gate is connected to the output of the inverter and whose source is connected to the high-voltage power supply is connected to the drain and gate of the second N-type MOS transistor, and the second NMOS transistor The source is connected to the ground voltage of the high voltage power supply system, the gate of the third NMOS transistor whose drain is connected to the output of the inverter is connected to the drain of the second PMOS transistor, and the source of the third NMOS transistor is the first NMOS transistor. A feedback circuit that is connected to the drain of the fourth NMOS transistor, the source of the fourth NMOS transistor is connected to the ground voltage of the high voltage system, and the signal of the low voltage power supply system is input to the gate of the fourth NMOS transistor;
A level shifter circuit comprising:   3. The level shifter circuit according to claim 2, wherein the first PMOS transistor and the first NMOS transistor forming the inverter are cascode-connected.   4. The level shifter circuit according to claim 2, wherein the second PMOS transistor is cascode-connected.

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