JP6007806B2 - CMOS comparator - Google Patents

Description

  The present invention relates to a CMOS comparator that prevents chattering from occurring.

  The comparator is a circuit that compares two inputs and generally outputs a binary value of a high voltage (H) and a low voltage (L). Even if these two inputs are very small, they are amplified and the difference between the high voltage (H) and the low voltage (L) is a large value at the output. The differential amplifier has a maximum amplification level, and the comparator does not negatively feed back the output. For this reason, chattering is likely to occur. Therefore, preventing chattering of the comparator is an extremely important matter. Conventionally, a comparator is provided with a hysteresis function, which is essential. Of the two inputs, one is generally used as an input voltage and the other is used as a reference voltage. However, a comparator that does not ensure hysteresis has a reference voltage or input voltage of (1) external noise, (2) Potential fluctuations occur due to noise from other blocks. The potential fluctuation causes chattering in the output of the comparator as shown in FIG.

  FIG. 9 is an explanatory diagram showing an example of a conventional CMOS comparator. FIG. 9A shows a CMOS comparator using a differential amplifier circuit having an inverting input INN and a non-inverting input INP, and FIG. An input voltage Vin causing a potential fluctuation due to noise and an output voltage Vout of a comparator in which chattering has occurred are shown over time. The figure shows how chattering occurs due to the up and down changes with respect to the reference voltage Vref due to the fluctuation of the input voltage Vin applied to the inverting input INN as the rise and fall of the output voltage Vout.

  FIG. 10A is an explanatory diagram showing an example of a conventional CMOS comparator that prevents chattering. FIG. 10B is an explanatory diagram schematically showing a hysteresis phenomenon that occurs between the input voltage Vin and the output voltage Vout. In order to prevent such chattering, a hysteresis circuit is added in which a resistor R1 is inserted between the input voltage Vin and the non-inverting input INP, and a resistor R2 is inserted between the non-inverting input INP and the output Vout. Yes.

  In FIGS. 10A and 10B, when the input voltage of the comparator changes from the low voltage L to the high voltage H, the detection voltage (threshold value) of the input voltage Vin changes from Vth and from the high voltage H to the low voltage L. The detection voltage (threshold value) of the input voltage Vin is Vtl. If the current flowing from the input terminal to the resistor R1 is I, the input impedance of the differential amplifier is maximal, so the current flowing to the resistor R2 is also I. In addition, since the amplification degree is maximum, the non-inverting input INP becomes the reference voltage Vref.

When the comparator changes from the low voltage L to the high voltage H, the currents that flow immediately before are I = (Vth−Vref) / R1 = (Vref−L) / R2 for the resistors R1 and R2, respectively.
It becomes. Therefore,
Vth = (1 + R1 / R2) Vref− (R1 / R2) L
It becomes.

Similarly, the current that flows immediately before the comparator changes from the high voltage H to the low voltage L is as follows: I = (Vtl−Vref) / R1 = (Vref−H) / R2 for the resistors R1 and R2.
It becomes. Therefore,
Vtl = (1 + R1 / R2) Vref− (R1 / R2) H
From now on, the hysteresis width is
(Vth−Vtl) = (R1 / R2) (HL)
It becomes.

Using this, in order to calculate specifically, VDD of the comparator in FIG. 10A (equal to the above H) = 3.00V, VSS (equal to the above L) = 0.00V, Vref = 1 .50V, R1 = 1 kΩ, R2 = 10 kΩ.
The hysteresis voltage width of the comparator is
Hysteresis voltage width = R1 / R2 * (VDD−VSS)
Calculated to be 0.3V. The detection voltage of “Low” → “Hi” and “Hi” → “Low”
“Low” → “Hi” detection voltage = Vref + 0.3V / 2 = 1.65V
“Hi” → “Low” detection voltage = Vref−0.3V / 2 = 1.35V
It becomes.

JP-A-5-291899

  Thus, in the comparator shown in FIG. 10, the detection (threshold) voltage of Low ”→“ Hi ”and“ Hi ”→“ Low ”is different (has a hysteresis width), so that the detection voltage is secured while ensuring hysteresis. Cannot be used if you want to set the same value for Low "⇒" Hi "and" Hi "⇒" Low ".

  In addition, it is difficult to assume the potential fluctuation width of the reference voltage or input voltage of the comparator, and the hysteresis fluctuation width of the comparator is often set by estimating the potential fluctuation width based on many years of experience of designers. Therefore, when the potential fluctuation range is larger than expected, if the hysteresis voltage width is exceeded as shown in FIG. 11, chattering occurs, circuit correction / layout correction is necessary, and mask correction for the CMOS wafer process is necessary. As a result, the design cost increases.

  The CMOS comparator of the present invention solves such a problem, and an object thereof is to provide a CMOS comparator having the same detection voltage and no chattering.

The present invention has been made in view of the problems, and the invention of claim 1
In a CMOS comparator including a differential amplifier circuit having an inverting input and a non-inverting input, the non-inverting input has a terminal for an input signal via a pull-up element and a switch that is turned OFF and ON corresponding to the output voltage level. The inverting input is a CMOS comparator characterized in that a pull-down element and a reference voltage terminal are connected via a switch that is turned OFF and ON corresponding to the level of the output voltage. is there.

The invention of claim 2 of the present invention
In a CMOS comparator including a differential amplifier circuit having an inverting input and a non-inverting input, the non-inverting input includes a pull-down element and a terminal of an input signal through a switch that is turned ON / OFF corresponding to the output voltage level. The inverting input is a CMOS comparator characterized in that a pull-up element and a reference voltage terminal are connected via a switch that is turned ON / OFF corresponding to the output voltage level. is there.

The invention of claim 3 of the present invention
The constant current MOS transistor of the differential amplifier circuit is connected to the ground via an NMOS transistor element that is turned on by an activation signal, and the output terminal is grounded via an NMOS transistor element that is turned on by an inverted activation signal. The CMOS comparator according to claim 1, wherein the CMOS comparator is connected to.

The invention of claim 4 of the present invention
The constant current MOS transistor of the differential amplifier circuit is connected to the ground via an NMOS transistor element that is turned on by an activation signal, and the output terminal is powered via a PMOS transistor element that is turned on by an inverted activation signal. The CMOS comparator according to claim 2, wherein the CMOS comparator is connected to.

Claim 5 of the present invention
A CMOS comparator according to claim 3 and a CMOS comparator according to claim 4, wherein the input signal and the reference voltage of both CMOS comparators are the same signal, and the activation signals are different signals. This is a CMOS comparator characterized by the above.

The invention of claim 6 of the present invention
6. The CMOS comparator according to claim 1, wherein the pull-up element and the pull-down element are resistance elements.

The invention of claim 7 of the present invention
6. The CMOS comparator according to claim 1, wherein the pull-up element and the pull-down element are MOS transistor elements that are turned on at an output voltage or an inverted output voltage.

The invention of claim 8 of the present invention
8. The CMOS comparator according to claim 1, wherein the switch is a transfer gate in which an NMOS transistor element and a PMOS transistor element are connected in parallel.

The invention of claim 9 of the present invention
9. The CMOS comparator according to claim 1, wherein an operational amplifier is used instead of the differential amplifier circuit.

  Since the CMOS comparator of the present invention has such a configuration, it can be a CMOS comparator having the same detection voltage and no chattering.

It is explanatory drawing which shows 1st embodiment of the CMOS comparator of this invention. 2A and 2B are diagrams for explaining the operation of the circuit according to the first embodiment of the present invention, in which FIG. 1A shows the time change of the input voltage, and FIG. 2B shows the time change of the output voltage. It is explanatory drawing which shows 2nd embodiment of the CMOS comparator of this invention. It is explanatory drawing which showed the example of the pull-up element of the CMOS comparator of 1st embodiment of this invention, and a pull-down element. It is explanatory drawing which shows 3rd embodiment of the CMOS comparator of this invention. It is explanatory drawing which shows 4th embodiment of the CMOS comparator of this invention. It is explanatory drawing which shows 5th embodiment of the CMOS comparator of this invention. It is explanatory drawing which shows operation | movement of the comparator shown in FIG. It is explanatory drawing which showed an example of the conventional CMOS comparator, (a) is a CMOS comparator by a differential amplifier circuit, (b) is explanatory drawing which shows an input voltage and the output voltage of the comparator in which chattering generate | occur | produced in time passage. It is. It is explanatory drawing which showed an example of the conventional CMOS comparator which prevented chattering. It is explanatory drawing which showed an example of the chattering which generate | occur | produced exceeding the hysteresis voltage width.

  Hereinafter, modes for carrying out the present invention will be described.

  The CMOS comparator of the present invention includes a basic differential amplifier circuit having an inverting input and a non-inverting input.

  FIG. 1 is an explanatory view showing a first embodiment of the CMOS comparator of the present invention. In the figure, a node A of a non-inverting input has a pull-up element (pull-up resistor in the figure) R1, a terminal of an input signal Vin via a switch SW1 that is turned OFF and ON according to the level of the output voltage Vout, The node B of the inverting input is connected to the pull-down element (pull-down resistor in the figure) R2 and the terminal of the reference voltage Vref via the switch SW2 that is turned off and on in accordance with the level of the output voltage Vout. Has been. An example of the switch is a transfer gate in which an NMOS transistor element and a PMOS transistor element are connected in parallel. As shown in FIG. 1B, an output voltage is applied to the PMOS transistor element, and an output voltage is applied to the NMOS transistor element via the inverter, so that the output voltage Vout is turned on and off according to the level of the output voltage Vout. It can be a switch.

The operation of the circuit of the first embodiment will be described. 2A and 2B are explanatory diagrams showing the time change of the input / output of this circuit. FIG. 2A shows the time change of the input voltage, and FIG. 2B shows the time change of the output voltage. When the input voltage Vin is low and lower than the reference voltage Vref (when the operation timing (1) Vin ≦ Vref in the figure), the output voltage Vout is also low, so both the switches SW1 and SW2 are in the ON state. . Therefore, the input voltage Vin is supplied to the node A, and the reference voltage Vref is supplied to the node B. As shown in FIG. 2A, when the input voltage Vin rises from this state, the output voltage Vout becomes the high voltage VDD when the input voltage Vin exceeds the reference voltage Vref. Once the state changes in this way, since the output voltage Vout is the high voltage VDD, both the switches SW1 and SW2 are turned off and disconnected. Since a pull-up resistor is connected to the node A, a high voltage state is maintained, and since a pull-down resistor is connected to the node B, a voltage equal to or lower than the reference voltage is maintained. Therefore, in this state, as shown in FIG. 2A, even if the input voltage or the reference voltage fluctuates and chattering occurs, the output voltage is kept at the high voltage VDD.

  In the first embodiment, it can be detected when the input voltage changes from a low voltage to a high voltage, but the second embodiment can be detected when the input voltage changes from a high voltage to a low voltage. FIG. 3 is an explanatory view showing a second embodiment of the CMOS comparator of the present invention. In the figure, a node A of a non-inverting input is connected to a pull-down element (pull-down resistor in the figure) R3 and a terminal of an input signal Vin via a switch SW3 that is turned on and off according to the level of the output voltage Vout. The node B of the inverting input is connected to the pull-up element (pull-up resistor in the figure) R4 and the terminal of the reference voltage Vref via the switch SW4 that is turned on and off according to the level of the output voltage Vout. Has been. An example of the switch is a transfer gate in which an NMOS transistor element and a PMOS transistor element are connected in parallel. As shown in FIG. 3B, an output voltage is applied to the NMOS transistor element, and an output voltage is applied to the PMOS transistor element via the inverter, so that the output voltage Vout is turned on and off according to the level of the output voltage Vout. It can be a switch.

  The operation of the circuit of the second embodiment will be described. When the input voltage Vin is high and higher than the reference voltage Vref, both the switches SW3 and SW4 are in the ON state because the output voltage Vout is also high. Therefore, the input voltage Vin is supplied to the node A, and the reference voltage Vref is supplied to the node B. When the input voltage Vin drops from this state, the output voltage Vout becomes the low voltage VSS when the input voltage Vin drops below the reference voltage Vref. Once the state changes in this way, the output voltage Vout is the low voltage VSS, so both the switches SW3 and SW4 are turned off and disconnected. Since a pull-down resistor is connected to the node A, a low voltage state is maintained, and since a pull-up resistor is connected to the node B, a high voltage is maintained. Therefore, in this state, even if the input voltage or the reference voltage fluctuates and chattering occurs, the output voltage is kept low.

  As the pull-up element and the pull-down element in the above embodiment, the pull-up resistor and the pull-down resistor have been described as examples. However, a MOS transistor element that is turned on at the output voltage or the inverted output voltage can also be used. This is illustrated below.

  FIG. 4 is a circuit in which the pull-up element and the pull-down element of the CMOS comparator of the first embodiment are constituted by MOS transistor elements MOS2 and MOS3, respectively. The MOS transistor element MOS2 as a pull-up element receives a signal obtained by inverting the output voltage at the gate. This is because the switch SW1 is disconnected when the output voltage becomes high, so that the MOS2 is pulled up at that time, and when the output voltage is low, the MOS2 is inactive OFF. The MOS transistor element MOS3 as a pull-down element has an output voltage input to the gate. This is because the switch SW2 is disconnected when the output voltage becomes high, so that the MOS3 is pulled down at that time, and when the output voltage is low, the MOS3 is inactive OFF. Therefore, when the switches SW1 and SW2 are ON, no excess current flows, which is more advantageous than when a resistor is used. The second embodiment can be used similarly.

  FIG. 5 is an explanatory diagram showing a third embodiment of the CMOS comparator of the present invention. In the present embodiment, the constant current MOS transistor MOS1 of the differential amplifier circuit is connected to the ground VSS via the NMOS transistor element MOS4 that is turned ON by the activation signal EN1, with respect to the CMOS comparator of the first embodiment. The output terminal Vout1 is connected to the ground VSS via the NMOS transistor element MOS5 that is turned ON by the inversion activation signal. The pull-up element and pull-down element of the CMOS comparator are composed of MOS transistor elements MOS2 and MOS3, respectively.

  When the activation signal EN1 is input in such a circuit, the NMOS transistor elements MOS4 and MOS5 are turned on and off, respectively, and are equal to the circuit of the first embodiment, so that the input voltage Vin changes from a low voltage to a high voltage. Thus, the output voltage Vout1 has a function of changing to a high voltage. When the inverted activation signal is input after the input voltage and the output voltage become high voltage, that is, when the activation signal EN1 is inverted, the NMOS transistor elements MOS4 and MOS5 are turned off and on, respectively, and the output voltage Vout1 becomes the ground voltage VSS. descend. Also, the constant current source is disconnected and the differential pair is in a floating state. The switches SW1 and SW2 are turned on and reset. Therefore, when the activation signal EN1 is input again, the output voltage V1 changes from a low voltage to a high voltage and the output voltage V1 changes to a high voltage.

  Thus, in the present embodiment, the activation signal can be switched from standby to active state and active state to standby state. That is, the detection voltage of the comparator can be returned to the initial state at any time.

  FIG. 6 is an explanatory diagram showing a fourth embodiment of the CMOS comparator of the present invention. In the present embodiment, the constant current MOS transistor MOS6 of the differential amplifier circuit is connected to the ground VSS via the NMOS transistor element MOS9 that is turned on by the activation signal EN2, with respect to the CMOS comparator of the second embodiment. The output terminal Vout2 is connected to the power supply VDD via the PMOS transistor element MOS10 that is turned ON by the inversion activation signal. The pull-up element and pull-down element of the CMOS comparator are composed of MOS transistor elements MOS8 and MOS7, respectively.

  In such a circuit, when the activation signal EN2 is input, the NMOS transistor element MOS9 is turned on, and the PMOS transistor element MOS10 is turned off, which is equal to the circuit of the second embodiment, so that the input voltage is changed from a high voltage to a low voltage. So that the output voltage changes to a low voltage. When the inverted activation signal is input after the input voltage and the output voltage become low, that is, when the activation signal EN2 is inverted, the NMOS transistor element MOS9 is turned off and the PMOS transistor element MOS10 is turned on, and the output voltage is set to the power supply voltage VDD. Boost to. Also, the constant current source is disconnected and the differential pair is in a floating state. The switches SW3 and SW4 are turned on and reset. Accordingly, the input of the activation signal EN2 again has a function of changing from a high voltage to a low voltage and changing the output voltage Vout2 to a low voltage.

  Thus, in the present embodiment, as in the third embodiment, the activation signal can be switched from standby to active state and active state to standby state. That is, the detection voltage of the comparator can be returned to the initial state at any time.

  FIG. 7 is an explanatory view showing a fifth embodiment of the CMOS comparator of the present invention. The CMOS comparator of this embodiment has the CMOS comparator (1) of the third embodiment and the CMOS comparator (2) of the fourth embodiment, and the input signal Vin and the reference voltage Vref of both CMOS comparators are Are the same signals, and the activation signals EN1 and EN2 are different signals.

  In the first to fourth embodiments of the present invention, the comparator input voltage can be detected only on one side (Low → Hi or Hi → Low). As shown in FIG. 7, the present embodiment has two comparators (1) and (2), so that both sides can be detected.

  The operation of the comparator of this embodiment will be described. The operation of the comparator shown in FIG. 7 is shown in FIG.

  First, the activation signals EN1 and EN2 input to the CMOS comparator (1) of the third embodiment and the CMOS comparator (2) of the fourth embodiment are both set to the low voltage VSS.

  At this time, in the CMOS comparator (1), the MOS 4 is OFF, the differential pair is floated, the MOS 5 is ON, and the output voltage Vout1 becomes the low voltage VSS. As a result, both the switches SW1 and SW2 are turned on, the node A is connected to the input voltage Vin, and the low voltage and the node B are at the reference voltage Vref.

  In the CMOS comparator (2), the MOS 9 is OFF, the differential pair is floated, the MOS 10 is ON, and the output voltage Vout2 is high. As a result, the switches SW3 and SW4 are both turned on, the node C is connected to the input voltage Vin, and the node D is at the reference voltage Vref.

Next, the activation signal EN1 of the CMOS comparator (1) is set to a high voltage to make it active. Thereafter, the input voltage Vin is increased. In the CMOS comparator (1), the operation is the same as that of the third embodiment in the transition state from the low voltage to the high voltage, and the output voltage Vout1 becomes a high voltage when the input voltage Vin and the node A exceed Vref. . In node B, the pull-down element transistor MO3 is turned ON, and the voltage drops from the reference voltage. The node A is maintained at a high voltage by the pull-up element MOS2. In the CMOS comparator (2), since the activation signal EN2 remains at a low voltage, the node C becomes a high voltage according to the change of the input voltage Vin, but the comparator is still in an inactive state and is in a standby state.
Next, the activation signal EN1 is inverted to a low voltage, the activation signal EN2 is set to a high voltage, and the input voltage starts to decrease. The CMOS comparator (1) immediately enters the standby state, the MOS4 is OFF, the differential pair is floated, the MOS5 is ON, and the output voltage Vout1 becomes the low voltage VSS. The switches SW1 and SW2 are both turned ON, the node A is connected to the input voltage Vin, and the low voltage, and the node B returns to the reference voltage Vref. The CMOS comparator (2) is in the active state, the MOS 9 is ON, the differential pair is connected, the MOS 10 is OFF, and the output voltage Vout2 is maintained at a high voltage. As a result, the switches SW3 and SW4 are both kept ON. In this state, since the input voltage Vin is connected to the node C, the voltage gradually becomes low, and when the voltage falls below the reference voltage, the output voltage Vout2 becomes low. Node D is pulled up to a high voltage.

  Next, the activation signal EN2 is set to a low voltage to return to the initial state.

  Thus, the input voltage Vout1 is adopted when the input rises (“Low” → “Hi”), and the output voltage Vout2 is adopted for the fall (“Hi” → “Low”). A CMOS comparator corresponding to voltage rising and falling changes (“Low” → “Hi”, “Hi” → “Low”) can be provided.

  In the CMOS comparator of the present invention, as exemplified above, the pull-up element and the pull-down element can be used as resistance elements. Alternatively, a MOS transistor element that is turned on at the output voltage or the inverted output voltage can be used. In this case, in the standby state, the current to the pull-up element and the pull-down element is cut off, which is advantageous.

  Further, in the CMOS comparator of the present invention, the above operation and effect can be obtained by using a configuration using an operational amplifier instead of the differential amplifier.

As described above, the CMOS comparator of the present application has the input rising edge (“Low” → “Hi”).
“)”, Falling (“Low” → “Hi”), or both changes (“Low” → “Hi”, “Hi” → “Low”) can be prevented from chattering. The rise of the input ("Low" ⇒ "Hi"), the fall ("Low" ⇒ "Hi"), or both changes ("Low" ⇒ "Hi", "Hi" ⇒ "Low The detection voltage of “)” can be set to the same value.

Vin ... Input voltage Vref ... Reference voltage Vout ... Output voltage Vbias ... Bias voltage INP for constant current ... Non-inverting input INN ... Inverting input VDD ... Power supply voltage VSS ... Grounding R1, R2 ... Resistor SW1, SW2 ... Switch

Claims (9)

In a CMOS comparator including a differential amplifier circuit having an inverting input and a non-inverting input,
The non-inverting input is connected to a pull-up element and a terminal of an input signal through a switch that is turned OFF and ON corresponding to the output voltage level. The inverting input is connected to a pull-down element and the output voltage level. A CMOS comparator characterized in that a reference voltage terminal is connected via a corresponding switch that is turned OFF and ON. In a CMOS comparator including a differential amplifier circuit having an inverting input and a non-inverting input,
The non-inverting input is connected to a pull-down element and a terminal of an input signal through a switch that is turned ON / OFF corresponding to the output voltage level, and the inverting input is connected to a pull-up element and the output voltage level. A CMOS comparator characterized in that a reference voltage terminal is connected via a corresponding switch that is turned on and off.   The constant current MOS transistor of the differential amplifier circuit is connected to the ground via an NMOS transistor element that is turned on by an activation signal, and the output terminal is grounded via an NMOS transistor element that is turned on by an inverted activation signal. The CMOS comparator according to claim 1, wherein the CMOS comparator is connected to the CMOS comparator.   The constant current MOS transistor of the differential amplifier circuit is connected to the ground via an NMOS transistor element that is turned on by an activation signal, and the output terminal is powered via a PMOS transistor element that is turned on by an inverted activation signal. The CMOS comparator according to claim 2, wherein the CMOS comparator is connected to.   A CMOS comparator according to claim 3 and a CMOS comparator according to claim 4, wherein the input signal and the reference voltage of both CMOS comparators are the same signal, and the activation signals are different signals. CMOS comparator characterized by   The CMOS comparator according to claim 1, wherein the pull-up element and the pull-down element are resistance elements.   6. The CMOS comparator according to claim 1, wherein the pull-up element and the pull-down element are MOS transistor elements that are turned on at an output voltage or an inverted output voltage.   8. The CMOS comparator according to claim 1, wherein the switch is a transfer gate in which an NMOS transistor element and a PMOS transistor element are connected in parallel.   9. The CMOS comparator according to claim 1, wherein an operational amplifier is used instead of the differential amplifier circuit.

Images