JP3119197B2 - Automatic wiring method considering crosstalk - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for automatically wiring a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, in the development of semiconductor integrated circuits, the process has been miniaturized, and higher integration and higher performance have been increasingly achieved. Under such circumstances, an ASIC is an automatic design method using a library of a plurality of standard cells, gate array cells, or functional block cells having logic functions.
(Application Specific IC)
Has been adopted.

[0005] Multi-bit signal lines or internal bus lines of a data bus of a CPU are tens of lines in parallel with a minimum pitch in order to severely restrict delay time in circuit functions and achieve high integration. Often done.

At this time, a problem is crosstalk noise. The crosstalk noise is as follows: (a) the longer the length of parallel adjacent wiring between signals, the shorter the spacing between wirings (b), (c) the larger the output impedance, (d) the smaller the capacitance between the substrates, e) The smaller the load capacitance, the greater the noise.

In general, the adjacent wiring capacitance C and the crosstalk noise V _o have the following relations (1) and (2), respectively.

[0006]

(Equation 1)

Here, ε: dielectric constant, W: wiring width, L: wiring length, d: wiring interval or insulating interlayer thickness.

[0008]

(Equation 2)

Where C ₁ is the coupling capacitance of the adjacent wiring, C _{T is} the total capacitance of the wiring receiving noise, and V ₁ (t) is the drive-side drive voltage after time t of the wiring that is the noise source. is there.

FIG. 6 is a plan view of a general semiconductor integrated circuit chip. In FIG. 6, 61 to 64
Is a functional block having a desired function, 66 is an electrode pad for extracting a signal, and a wiring 67 is a wiring connecting the blocks 61 to 64 and satisfying a desired function. The wiring 67 is an example in which four wirings are provided in parallel. In FIG. 6, other wirings are omitted for simplification of description.

In FIG. 6, four broken lines 67 are indicated by broken lines AB. 7 (a) and 7
(B) is an enlarged plan view of AB in FIG. 6 and AB in FIG.
It is sectional drawing of a line.

The four wires 1-4 have a minimum pitch (distance d)
23), wiring is performed in the lowest layer. In the following,
From the lowest wiring layer to the upper layer, they are called a first wiring layer, a second wiring layer, and an n-th wiring layer.

The wiring capacitance of each wiring and the substrate is Cl,
The wiring capacitance between adjacent wirings is denoted by C11.

With the miniaturization, the spacing between wirings becomes smaller, and the minimum pitch d23 becomes smaller. That is, the capacitance C11 tends to increase.

In such a data bus wiring and the like, since each wiring delay time is the same and a short time is desirable, parallel wiring is apt to occur. Therefore, the length L of the adjacent wiring capacitance C11 is a problem. Come. On the other hand, the interlayer insulation film between the wiring and the substrate is hardly scaled, and the wiring capacitance C1 with the substrate does not change so much only by the difference in the material.

FIG. 8 shows the first countermeasures shown in FIGS.
3 is a semiconductor chip plane for describing the related art of the present invention.
9A and 9B are an enlarged plan view taken along a line AB in FIG. 8 and a cross-sectional view taken along the line AB in FIG.

Referring to FIG. 8 and FIG. 9, this prior art is such that the parallel wiring is extended to twice the minimum pitch d23. In the case of automatic wiring, such a method is the most common and simplest. .

The adjacent wiring capacitance C22 is C22 <C11.
If the capacitance C1 with the substrate is the same, this reduces crosstalk noise, and does not cause a problem.

In FIG. 9, wires 91 to 94 correspond to wires 1 to 4 in FIG. Lines 95 to 97 run wires used for other desired functions.

A second prior art is a method of shortening the length L of the adjacent wiring. A reference value L1 of a line length which does not cause a problem in crosstalk is determined, and after automatic wiring, each wiring satisfying L <L1 is redrawn.

[0021]

As described above, FIG.
The first conventional technique described with reference to FIG. 9 has a problem that the wiring pitch is doubled and the degree of integration is reduced.

On the other hand, in the second prior art in which the length of the adjacent wiring is shortened, it is difficult to make the delay time of each wiring the same, and the variation of the delay time of each wiring becomes large. come.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to convert the coupling capacitance of an adjacent wiring in the same layer to a capacitance by converting a part of the adjacent wiring to another layer. It is an object of the present invention to provide an automatic wiring method for reducing crosstalk noise without reducing the integration degree.

[0024]

According to the present invention, there is provided an automatic wiring method, comprising: automatically arranging a plurality of standard cells, gate array cells, or functional block cells having a logical function; Connects and performs automatic wiring with a netlist that satisfies the desired logical function as input,
In a layout of a semiconductor integrated circuit having a multilayer wiring structure, after automatic wiring, each wiring capacitance is calculated, a crosstalk reference value by an adjacent wiring is set, and the adjacent wiring in the same layer is set.
A part of the wiring whose coupling capacitance exceeds the reference value is converted to another layer and re-automatic wiring is performed, and the space between the wiring converted to another layer after the re-wiring and the wiring of the original layer is re-determined. A step of making the distance larger than the distance between the adjacent wirings before wiring.

[0025]

Embodiments of the present invention will be described below. In a preferred embodiment of the automatic routing method according to the present invention, referring to FIG. 1, (a) Step 1 of automatically placing a netlist satisfying a desired logic function as an input, and (b) Step of performing automatic routing 2 and
(C) After the automatic wiring, the capacitance data is extracted from the wiring result,
Step 3 of calculating each wiring capacitance, (d) Step 4 of extracting an adjacent wiring length for each wiring to calculate the influence of crosstalk noise and calculating coupling capacitance for each wiring, and (e). (5) comparing a predetermined delay time delay due to crosstalk noise and a reference value causing a malfunction with the coupling capacitance obtained in step (d); and (f) exceeding the reference value. If there is a wiring, it is necessary to change the wiring, and the wiring exceeding the reference value is peeled off, and if necessary, the wiring of the channel necessary for the rewiring is peeled off.
And (g) converting a part of the adjacent wiring to another layer to reduce the coupling capacitance.
If the coupling capacitance is within the reference value, the process proceeds to the next step such as delay verification and timing verification. Each of the above steps is implemented by a program executed by a computer.

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

[Embodiment 1] FIG. 1 is a flowchart for explaining an embodiment of an automatic wiring method in consideration of crosstalk according to the present invention. Referring to FIG. 1, a netlist satisfying a desired logic function is automatically placed as an input (step 1), and automatic wiring is performed (step 2).

After the automatic wiring, capacitance data is extracted from the wiring result, and each wiring capacitance is calculated (step 3). at the same time,
In order to check the degree of influence of crosstalk noise, the length of the adjacent wiring for each wiring is extracted, and the coupling capacitance for each wiring is calculated (step 4).

Next, a predetermined delay time delay due to crosstalk noise and a reference value that causes malfunction are compared with the coupling capacitance obtained in step 4 (step 5), and the coupling capacitance is within the reference value. If so, the process proceeds to the delay verification and the timing verification (step 6), and if there is no problem, the process ends.

On the other hand, if there is any wiring exceeding the reference value in step 5, it is necessary to change the wiring, and the wiring exceeding the reference value is peeled off, and the wiring of the channel necessary for rewiring is also peeled off (step 5). 7). And
In step 8, a process of converting a part of the adjacent wiring to another layer is performed to reduce the coupling capacitance.

That is, in this embodiment, as a method for reducing the coupling capacitance, a part of the parallel adjacent wiring in the same layer is converted to another layer.

A specific example will be described below with reference to FIGS. FIG. 2 shows an example in which, out of the four parallel wirings 1 to 4 of the first wiring layer, the wirings 2 and 4 are converted to another second wiring layer. FIG. 2A is a plan view before conversion, and FIG.
2B is a cross-sectional view taken along the line AB in FIG. 2A, and FIG. 2C is a cross-sectional view after another layer conversion.

Referring to FIG. 2C, wiring 2 → 12
(The second wiring layer), the wiring is converted to the position of the wiring 4 → 14 (the second wiring layer), and the wiring is performed again. Note that the distance d1 is the distance between the substrate and the first wiring layer. 16 and 17 are wirings 2 before conversion,
4 is shown.

With miniaturization, the minimum distance between wirings in the same wiring layer has become smaller than the distance between the upper and lower wiring layers. Therefore, assuming that the minimum distance between wirings in the same layer is d11 and the distance between the first and second wiring layers is d2, d11 <d2 and the capacitance is C
11> C2.

The capacitance C22 between the wiring 11 (original wiring 1) and the wiring 13 (original wiring 3) is a certain capacitance before conversion. If the adjacent wiring lengths are the same, the difference between the capacitances of C11 and C2 is obtained. The coupling capacity is reduced.

Similarly, FIG. 3 is a diagram showing a configuration in a case where the wiring can be used up to the fourth wiring layer.
The wiring 2 is converted to a second wiring layer (22), the wiring 3 is changed to a third wiring layer (23), and the wiring 4 is changed to a fourth wiring layer (24).

The wiring capacitance between the upper and lower layers in each of the upper and lower layers is determined by the dielectric constant and the thickness of the material of each insulating interlayer film. If the dielectric constant is the same, it is determined by the distances d2 to d4.

Here also, C11> C2, C3, C4 holds, and the coupling capacitance decreases for each wiring.
26 indicates the position of the wiring 2.

FIG. 4 shows an example in which the original wiring of the first wiring layer is converted to an upper second wiring layer as in FIG. 2, but is converted to another layer by shifting the wiring pitch by half the wiring pitch. It is a thing.

Referring to FIG. 4, the original wirings 1 and 3 (see FIG. 2B) are unchanged at 31 and 33, and
Are converted into the second wiring layers 32 and 34 shifted by a half pitch. When paying attention to the wiring 32 that receives noise, the coupling capacitance between the lower wirings 31 and 33 becomes a problem. That is, the capacitance C25 for the lower wiring 31 and the capacitance C25 for the lower wiring 33 are problematic, and FIG.
Although the significant difference cannot be generally discussed with the example shown in FIG. 2, the capacitance C11> C25 between adjacent wirings is satisfied,
The coupling capacity tends to decrease.

In FIG. 4, reference numerals 36 and 37 indicate the positions of the wirings 2 and 4, respectively. C24 is the capacitance between the wiring 32 and the wiring 34.

Embodiment 2 A second embodiment of the present invention will be described below. 5A and 5B are diagrams showing a case where the layer to be converted is not an adjacent upper layer as a second embodiment of the present invention. FIG. 5A is a plan view, and FIG. A
It is sectional drawing of the -B line.

Normally, the automatic wiring corresponding to the multi-layer includes the first, third,
2i-1 (i = 1, 2, 3,...) Wiring layer and second, fourth,
2i,... The wiring layer is an orthogonal wiring method. For example, if the first, third, and 2i-1 (i = 1, 2, 3,...) Wiring layers are in the x-axis direction, the second, fourth, 2i,.

In this case, when the wiring layer is converted as in the first embodiment, it is necessary to remove a large number of existing wirings for other signals, and the number of automatic wirings thereafter increases, which takes time. For example, if another signal wiring passes through the second wiring layer portion of the wiring focused on the first wiring layer, the wiring must be peeled off and the second wiring layer is wired in parallel with the first wiring layer and the upper and lower layers. become unable. This can be avoided by setting that part as a prohibited area in advance. Therefore, in this case, it is easier to replace the layer to be converted with a wiring layer that enters in the same direction.

The positions of the wirings 1 to 4 in FIG.
46, 43, and 47.

Referring to FIG. 5B, 1, 3 → 41,
At 43, the wiring is converted to the third wiring layer of 2 → 42, 4 → 44 and wired. A broken line portion 48 indicates the second wiring layer.

Thus, the distance d25 between the wirings 41 and 42 is equal to the film thickness of the 1-2 wiring interlayer film and the 2-3 wiring interlayer film, and the coupling capacitance C27 is C11>C2> C27. It can be ignored.

In FIG. 5B, C 26 indicates the adjacent capacitance between the wiring 42 and the wiring 44.

Therefore, the present embodiment has better wiring properties and smaller capacity than the first embodiment.

In the example shown in FIG. 5, the third wiring layer and the first wiring layer have the same pitch, but this is not necessary.

[0051]

As described above, according to the present invention,
In a layout of a semiconductor integrated circuit having a multilayer wiring structure in which a netlist satisfying a desired logic function is input and an automatic wiring is performed, each wiring capacitance is calculated after the automatic wiring, and a crosstalk reference value by an adjacent wiring is set. The configuration in which a part of the wiring exceeding the value is converted to another layer and re-automatic wiring is performed has an effect of eliminating delay time delay and malfunction due to crosstalk noise without reducing the degree of integration.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow of an embodiment of an automatic wiring method in consideration of crosstalk according to the present invention.

FIG. 2 is a diagram for explaining one embodiment of the present invention;
(A) is a plan view, (b) is a cross-sectional view taken along line AB of (a),
(C) is a diagram showing a cross section after conversion to a second wiring layer.

FIG. 3 is a diagram for explaining one embodiment of the present invention;
FIG. 14 is a diagram illustrating a cross section when conversion is performed using up to a fourth wiring layer.

FIG. 4 is a diagram for explaining one embodiment of the present invention;
FIG. 11 is a diagram illustrating a cross section of another example in which conversion is performed using the second wiring layer.

FIG. 5 is a view for explaining another embodiment of the present invention, and is a view showing a cross section when conversion is performed using the same-direction wiring.

FIG. 6 is a plan view showing a general LSI chip.

7A is a partially enlarged view taken along a line AB in FIG. 6, and FIG.
FIG. 7 is a diagram schematically illustrating a cross section taken along line AB in FIG. 6.

FIG. 8 is a plan view of a conventional LSI chip for which crosstalk noise is prevented.

9A is a partially enlarged view taken along a line AB in FIG. 8, and FIG.
FIG. 9 is a diagram schematically showing a cross section taken along line AB in FIG. 8.

[Explanation of symbols]

1-4 Parallel wiring 1-14, 21-24, 31-34, 41-44, 91
~ 94 Wiring after considering crosstalk dx distance (x is an integer) cy capacitance (y is an integer)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 27/118

Claims (3)

(57) [Claims] 1. A plurality of standard cells, gate array cells, or function block cells having a logic function are automatically arranged, and automatic wiring is performed by connecting the plurality of cells and inputting a netlist satisfying a desired logic function as an input. In a layout process of a semiconductor integrated circuit having a multi-layer wiring structure, each wiring capacitance is calculated after automatic wiring, a crosstalk reference value by an adjacent wiring is set, and the power of the adjacent wiring in the same layer is set.
If Ppuringu capacity exceeds the crosstalk reference value
Then, part of the adjacent wiring is converted to another layer and re-wired,
2. The automatic wiring method according to claim 1, wherein an interval between the wiring converted into another layer after the rewiring and the wiring of the original layer is larger than an interval between the adjacent wirings before the rewiring. 2. A step of automatically arranging a netlist satisfying a desired logic function as an input, a step of performing automatic wiring, and a step of extracting capacitance data from a wiring result after the automatic wiring.
(D) calculating the coupling capacitance for each wiring by extracting an adjacent wiring length for each wiring to check the influence of crosstalk noise; and (e) calculating the coupling capacitance for each wiring. Comparing the delay time delay due to the crosstalk noise and the reference value that causes a malfunction with the coupling capacitance obtained in step (d). (F) The coupling capacitance due to the adjacent wiring in the same layer is If there is a wiring exceeding the reference value, it is necessary to change the wiring, the wiring exceeding the reference value is peeled off, and if necessary, the wiring of the channel required for rewiring is peeled off, and the coupling capacitance is removed. Some adjacent wiring is converted to another layer to reduce the wiring, and re-wiring is performed.The space between the wiring converted to the different layer after the re-wiring and the wiring of the original layer is reduced by The step of larger than spacing of contact wires, (g) On the other hand, if the coupling capacitance is within the reference value, the process proceeds to the next step, such as delay verification and timing verification, automatic wiring method comprising the above steps. 3. A process for automatically placing a netlist satisfying a desired logic function as an input, a process for performing automatic routing, and a process for extracting capacitance data from a routing result after automatic routing.
(D) a process of calculating the coupling capacitance for each wiring by extracting an adjacent wiring length for each wiring to check the degree of influence of crosstalk noise, and (e) calculating a coupling capacitance for each wiring. Delay time caused by crosstalk noise and a reference value causing malfunction, and the above processing (d)
And (f) if there is a wire whose coupling capacitance due to an adjacent wire in the same layer exceeds the reference value, it is necessary to change the wire, and the value exceeds the reference value. The wiring is peeled off, and if necessary, the wiring of the channel required for the rewiring is peeled off, and some adjacent wirings are converted to another layer to reduce the coupling capacitance and redistributed. A process of setting the distance between the wiring converted into the different layer and the wiring of the original layer to be larger than the distance between the adjacent wirings before rewiring; (g) On the other hand, if the coupling capacitance is within a reference value For example, processing for proceeding to the next step such as delay verification and timing verification, and the above-described respective processings (a) to (g) are executed by a computer to record a program for performing automatic wiring in consideration of crosstalk. Medium.