JP2007207301A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of increasing operational performance and operational speed and also reducing current consumption by facilitating timing control and matching the timing with optimal timing in data transfer between a large-capacity memory circuit and a plurality of arithmetic operation circuits, and data transfer in each circuit. <P>SOLUTION: In the semiconductor memory device, each memory bank is provided with a plurality of local word lines connected to lines corresponding to memory cells, and a driver for driving each local word line according to a control signal transmitted through a global word line shared by the memory banks. Each global line is arranged so that loads are equal at a space where two or more local word lines arranged. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device used for an image processor or the like that processes a large amount of image data.

  In recent years, in order to process a large amount of data such as image data, a semiconductor device that uses a processor and a memory on the same chip and performs high-speed processing as a dedicated processing system has been used. In particular, a SIMD (Single Instruction Multiple Data) processor operates a memory circuit and a plurality of arithmetic circuits mounted on the same chip in parallel with one instruction, and performs various image processing by repeatedly executing this. Realized.

  In order to process such a large amount of data, a large-capacity memory circuit and a plurality of arithmetic circuits for processing the data are required. In a large-capacity memory circuit, if a large number of memory cells are connected to one word line, the load on the word line becomes very large. A method of dividing memory blocks (hereinafter referred to as “memory banks”) is used, in which a memory cell array is divided into a plurality of memory banks and these memory banks are connected by a plurality of global word lines. 5 shows a configuration example of a conventional semiconductor memory device employing this method, as shown in FIG. 5, each memory bank 102 includes a plurality of global word lines GWL0 to GWLm (m is a positive number). In addition, each memory bank 102 has a local word line W for each row of memory cells. 5, each local word line corresponds to one global word line in the configuration example shown in FIG. When driving a memory cell (bit cell) connected to the word line WL0, a predetermined control signal output from a decoder (not shown) is transmitted to each memory bank 102 by the corresponding global word line GWL0, The local word line WL0 in each memory bank 102 is activated, and the same applies to the other local word lines WL1 to WLm.

  In the configuration example shown in FIG. 5, when an SRAM (Static RAM) is used as a memory cell, in recent years, a split word line (SWL) as shown in FIG. System layout shapes have begun to be used. The bit cell has a length of about ½ in the bit line (BL) direction as compared with the shape shown in FIG.

  On the other hand, in a DRAM (Dynamic RAM) memory cell array in which the cell pitch in the bit line direction is originally small, one main word line is assigned to a plurality of sub word lines, and sub word selection lines and main word lines arranged in the bit line direction. A method of selecting a sub-word line by combining with is often used. FIG. 7 shows a configuration example of a semiconductor memory device that realizes such a method. In the semiconductor memory device shown in FIG. 7, one main word line is assigned to x + 1 (x is an integer of 1 or more) sub word lines. Here, an arbitrary main word line MWLk (k = 0 to x) among (x + 1) main word lines MWL0 to MWLx will be described. (X + 1) sub word lines SWLk0 to SWLkx with respect to the main word line MWLk. Each of the sub word lines SWLk0 to SWLkx has a one-to-one correspondence with (x + 1) sub word selection lines SL0 to SLx in the bit direction. In such a semiconductor memory device, a desired sub word line is selected by a combination of main word lines MWL0 to MWLx and sub word selection lines SL0 to SLx, and a bit cell connected to the sub word line is driven.

  In some conventional semiconductor memory devices, two subword drivers share a transistor for keeping an unselected subword line at an L level in order to reduce the area of the subword driver that drives the subword line. (For example, refer to Patent Document 1).

  In another conventional semiconductor memory device, there is a device that speeds up an operation by reducing a signal delay by reducing a ratio of a long side to a short side of a chip (see, for example, Patent Document 2). .)

  Furthermore, in another conventional semiconductor memory device, a subword selection signal is divided into two signals, and a circuit portion to be energized according to each signal is divided to distribute the load applied to each signal, thereby selecting a subword. Some have reduced the load on the wire (for example, see Patent Document 3).

Furthermore, in another conventional semiconductor memory device, in order to improve noise resistance, an output data line, which is a data read data line that is likely to cause a malfunction due to noise, is placed in a read state or a data holding state. In some cases, there is a shield with an input data line which is a data write data line set so as not to perform the operation (see, for example, Patent Document 4).
JP 2000-187978 A JP 2001-060671 A Japanese Patent Laid-Open No. 2004-071023 JP 2004-247666 A

  However, in recent years, the number of processor elements (PE) that perform simultaneous processing in image processors that process image data has been increasing, and the wiring resistance of global word lines is an important issue that affects operating performance. It has become. In other words, as the wiring resistance increases, the wiring delay increases, and not only the operation speed is affected by the direct wiring delay, but also the influence of the timing variation between the control signals due to the variation in the manufacturing process becomes more prominent. Has occurred. For example, in the configuration as shown in FIG. 5, it is necessary to arrange a driver having a buffer for amplifying a control signal for each memory bank, so that the global word line length becomes long and wiring resistance increases. I was invited. Further, the shape of the bit cell of FIG. 6A, which has recently been adopted, has a length in the bit line (BL) direction of about 1/2 compared to the shape shown in FIG. Since the length in the word line (WL) direction is increased accordingly, there is a problem that the wiring resistance in the word line direction is increased. In particular, an SRAM memory circuit used in a processor intended for high-speed operation has a larger cell size than a DRAM memory circuit, so that the wiring resistance in the word line direction is a greater problem.

  In order to reduce the wiring resistance of the global word line, it is conceivable to widen the wiring width. However, the shape shown in FIG. 6A is reduced in the BL direction. There is a limit to widening, and further, there is a problem that the wiring capacity is increased due to the narrow pitch in the BL direction. In order to reduce the wiring resistance of the word line in the memory cell structure as shown in FIG. 6B, the problem can be avoided by widening the wiring width. However, the memory shown in FIG. In the cell structure, there is a problem that it is difficult to even increase the width of the word line.

  Since the memory cell array shown in FIG. 7 uses the sub word selection lines SL0 to SLx, the wiring load in the word line direction is reduced. However, when the wiring load of the sub word selection lines SL0 to SLx is large, the sub word selection line In some cases, variations in selection time due to wiring delay occur on the SL0 to SLx side. In such a case, the main word lines MWL0 to MWLx must be selected after the activation and deactivation of all the sub word selection lines SL0 to SLx are determined. This fixed time affects the operating frequency of the semiconductor memory device. When the fixed time is long, it is necessary to adjust the timing for each signal line in the word line direction and the bit line direction. Therefore, it has been difficult to apply the configuration example shown in FIG. 7 to an image processor or the like that requires high-speed operation.

  When a semiconductor memory device is applied to a SIMD processor, it is necessary to process a predetermined number of data at a time. Therefore, each control for controlling the memory circuit is simultaneously performed while reducing the load in the word line direction. It is required to match the operation timing of the lines. If the operation timings of the respective control lines do not coincide with each other, a delay occurs in reading and writing in the memory circuit, which not only slows the operating frequency but also causes unnecessary current consumption to flow in the memory circuit. The same applies to arithmetic circuits that process data. That is, in order to process a large amount of data simultaneously, a signal for controlling a plurality of arithmetic circuits must be synchronized with a signal for controlling a memory circuit, for example, a signal transmitted by each global word line. If the operation timings of the control lines of the arithmetic circuit and the memory circuit do not match, not only the high-speed operation of the arithmetic circuit is disturbed but also an unnecessary current consumption is caused to flow. The conventional semiconductor memory device has a problem that it is difficult to match the operation timing in this way.

  By the way, as a method of performing synchronous design of the memory circuit and the arithmetic circuit, it may be possible to mount a plurality of small-capacity memory circuits, but each memory circuit requires a control circuit, which increases the chip size. Occurs. In such a case, when the address is decoded and data is input / output after the synchronous clock is input, there arises a problem that the data access time itself becomes long. Thus, when the data delay time is long with respect to the period of the synchronous clock, control becomes difficult, and it is necessary to take measures such as pipelining memory access. Further, when the control signal propagates in the bit line direction, skew caused by signals in the bit line direction becomes a problem.

  The present invention solves the above-described problem, and facilitates timing control in the exchange of data between a large-capacity memory circuit and a plurality of arithmetic circuits, and the data transfer in each circuit. It is an object of the present invention to provide a semiconductor memory device that can realize not only improvement in operation performance and operation speed but also reduction in current consumption by matching the timing at an optimum timing.

  A semiconductor memory device according to the present invention includes a plurality of memory banks formed by dividing a memory cell array composed of a plurality of memory cells arranged in a matrix, and is shared by each memory bank, and each memory bank has a predetermined control. And a plurality of global word lines for transmitting signals. Each memory bank includes a plurality of local word lines connected to each corresponding row of the memory cells, and a driver that drives each local word line in response to the control signal. . Each of the global word lines is arranged at an interval where two or more of the local word lines can be arranged so that loads are equal. Hereinafter, this semiconductor memory device is referred to as a “first semiconductor memory device”.

  Preferably, in the first semiconductor memory device, the global word lines are arranged at equal intervals in the column direction of the memory cell array. Hereinafter, this semiconductor memory device is referred to as a “second semiconductor memory device”.

  Preferably, the second semiconductor memory device is connected in common by a plurality of input / output circuits that respectively input / output data to / from each memory bank, and the input / output circuits. And a global control line for transmitting input / output control signals. The global control line is arranged so that the load is equal to each global word line. Hereinafter, this semiconductor memory device is referred to as a “third semiconductor memory device”.

  Preferably, in the third semiconductor memory device, the global word lines and the global control lines are arranged at equal intervals in the column direction of the memory cell array. Hereinafter, this semiconductor memory device is referred to as a “fourth semiconductor memory device”.

  Preferably, in the third or fourth semiconductor memory device, the memory cell array includes a plurality of dummy cells. The global control line is arranged for each dummy cell so as to have the same relation as the arrangement relation of the global word line to the memory cell. Hereinafter, this semiconductor memory device is referred to as a “fifth semiconductor memory device”.

  Preferably, in any of the first to fifth semiconductor memory devices, at least one shield line is disposed between each of the global word lines. Hereinafter, this semiconductor memory device is referred to as a “sixth semiconductor memory device”.

  Preferably, in the sixth semiconductor memory device, the global word lines and the shield lines are arranged at equal intervals in the column direction of the memory cell array.

  According to the semiconductor memory device of the present invention, each memory bank has a plurality of local word lines connected to each corresponding row of memory cells and a control signal transmitted by a global word line shared by each memory bank. And a driver for driving the local word lines, respectively, and the global word lines are arranged at equal intervals so that two or more local word lines can be arranged. Therefore, it is possible not only to reduce the wiring load in the word line direction, which affects high-speed operation, but also to operate each circuit in synchronization with only the global word line in the same direction. Because there is no need to secure an unnecessary operating margin Speed up becomes possible. In addition, since the semiconductor device memory device can be operated at an optimum operation timing, unnecessary current consumption can be omitted.

Embodiments of the present invention will be described below with reference to the accompanying drawings.
(Embodiment 1)
FIG. 1 shows a configuration example of a semiconductor memory device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor memory device according to the first embodiment includes a plurality of memory banks 2, a plurality of input / output circuits (hereinafter referred to as “I / O circuits”) 3, and a plurality of arithmetic circuits. 4 and a decoder 5. Each memory bank 2 is connected by global lines GL0 to GLn (n is a positive integer). Each I / O circuit 3 and each arithmetic circuit 4 are connected by corresponding global lines GL (n + 1) and GL (n + 2), respectively. The global lines GL0 to GL (n + 2) are connected to the decoder 5, respectively. Each arithmetic circuit 4 processes data stored in each corresponding memory bank 2, and the I / O circuit 3 inputs and outputs data to each corresponding memory bank 2. The decoder 5 supplies a control signal to each memory bank 2, each I / O circuit 3, and each arithmetic circuit 4 via the global lines GL0 to GL (n + 2).

  Hereinafter, the configuration of the memory bank 2 will be described in detail. FIG. 2 is a circuit diagram showing a configuration example of the memory bank 2 of one block. This configuration example of the memory bank 2 is used when a large amount of data such as a SIMD image processor is simultaneously processed in parallel. As shown in FIG. 2, the memory bank 2 has a plurality of 1-bit memory cells (described as “bit cells” in FIG. 2) arranged in a matrix. The memory bank 2 includes a plurality of local word lines LWL00 to LWL03, LWL10 to LWL13, LWL20 to LWL23, LWL30 to LWL33, and local word lines LWL00 to LWL03, LWL10, respectively connected to the corresponding memory cells in each row. And local word line drivers (hereinafter simply referred to as “local drivers”) for driving LWL13, LWL20 to LWL23, and LWL30 to LWL33, respectively. This local driver includes a plurality of NAND circuits Nd and an inverter circuit Iv. Further, nine global lines including eight global word lines GWLA0 to GWLA3 and GWLB0 to GWLB3 and one global control line GREN are connected to the memory bank 2. The global control line GREN is a global line for read control connected to the I / O circuit 3. Here, the semiconductor memory device 1 has a hierarchical structure, and the global word lines GWLA0 to GWLA3, GWLB0 to GWLB3, and GREN and local word lines LWL00 to LWL03, LWL10 to LWL13, LWL20 to LWL23, and LWL30 to LWL33 are different wiring layers. May be arranged. The configuration example of the memory bank 2 shown in FIG. 2 is a configuration example when n = 8 in FIG. Although the arrangement of the global control lines GREN shown in FIG. 2 does not match that of FIG. 1, the configuration example shown in FIG. 2 is possible depending on the arrangement of the I / O circuit 3, and such a configuration is also possible. In this case, since a new effect is produced, the following description is based on the configuration example shown in FIG.

  As shown in FIG. 2, the global word lines GWLA0 to GWLA3 and GWLB0 to GWLB3 are arranged at equal intervals in the order of the global word lines GWLB3, GWLB2, GWLA3, GWLA2, GWLB1, GWLB0, GWLA1, and GWLA0. With respect to the global word line GWLB3, a local word line LWL33 is arranged on the opposite side of the global word line GWLB2, and two local word lines LWL32 and LWL23 are arranged between the global word lines GWLB3 and GWLB2, respectively. In addition, two local word lines LWL22 and LWL13 are arranged between the global word lines GWLB2 and GWLA3, respectively, and two local word lines LWL12 and LWL03 are arranged between the global word lines GWLA3 and GWLA2, respectively. Two local word lines LWL02 and LWL31 are arranged between the global word lines GWLA2 and GWLB1, respectively. Further, two local word lines LWL30 and LWL21 are respectively arranged between the global word lines GWLB1 and GWLB0, and two local word lines LWL20 and LWL11 are respectively arranged between the global word lines GWLB0 and GWLA1, Two local word lines LWL10 and LWL01 are arranged between each global word line GWLA1 and GWLA0, and a local word line LWL00 is arranged on the opposite side of the global word line GWLA0 from the global word line GWLA1.

  Each of the global word lines GWLA0 to GWLA3 and GWLB0 to GWLB3 transmits a predetermined control signal output from the decoder 5 to each memory bank 2. The local driver activates a specific local word line based on the transmitted control signal. At this time, operations such as data input / output are performed on the memory cells connected to the activated local word line.

  Hereinafter, the operation of the memory bank 2 will be described in detail. Here, since all the local word lines LWL00 to LWL03, LWL10 to LWL13, LWL20 to LWL23, and LWL30 to LWL33 have the same configuration and operation, any local word line can be connected to LWLpq (p = 0 to 3, q = 0). -3), the local word line LWLpq corresponds to one NAND circuit Nd and one inverter circuit Iv in the local driver. Here, when the NAND circuit and the inverter circuit connected to the local word line LWLpq are described as Ndpq and Ivpq, respectively, two input ends of the NAND circuit Ndpq are connected to two global word lines GWLAp and GWLBq. In this case, when the two global word lines GWLAp and GWLBq are selected, that is, when a predetermined control signal is output from the decoder 5 to the two global word lines GWLAp and GWLBq, the NAND circuit Ndpq outputs the inverter circuit Ivpq. To output a predetermined signal. When the above signal is output from the NAND circuit Ndpq, the inverter circuit Ivpq inverts the signal and outputs it to the local word line LWLpq, whereby the local word line LWLpq is activated.

  As described above, in the configuration example shown in FIG. 2, one local word is selected by selecting one of the global word lines GWLA0 to GWLA3 and one of the global word lines GWLB0 to GWLB3. A line can be selected. For example, two global word lines GWLA0 and GWLB0 may be selected to select the local word line LWL00, and two global word lines GWLA3 and GWLB3 may be selected to select the local word line LWL33. Thus, by selecting a combination of two global word lines, one of the 16 local word lines LWL00 to LWL03, LWL10 to LWL13, LWL20 to LWL23, and LWL30 to LWL33 can be selected.

In general, if each NAND circuit has two inputs in the configuration as shown in FIG. 2, 2 × j (j is a positive integer) global word lines drive j ² local word lines. be able to. In the configuration example shown in FIG. 2, j = 4, and 16 local word lines can be driven using 8 global word lines. According to the configuration example shown in FIG. 2, two local word lines correspond to one global word line. As a result, the wiring pitch of the global word lines is twice that of the prior art, and the wiring resistance of each global word line can be greatly reduced. Further, according to the configuration example shown in FIG. 2, the global word lines GWLA0 to GWLA3 and GWLB0 to GWLB3 are arranged so as to have an equal load. Timing control between transmitted signals is facilitated.

  2, the local word lines LWL00 to LWL03, LWL10 to LWL13, only the global word lines GWLA0 to GWLA3 and GWLB0 to GWLB3 in the word direction without using the selection line in the bit direction. LWL20 to LWL23 and LWL30 to LWL33 can be selected. Therefore, it is not necessary to define the timing for the selection line in the bit direction, the memory circuit can be operated at high speed, and the synchronization timing with peripheral circuits such as arithmetic circuits can be easily optimized.

  Further, in the configuration example shown in FIG. 2, the global control lines GREN are arranged at equal intervals to the global word lines GWLA0 to GWLA3 and GWLB0 to GWLB3. Further, the layout is the same as the layout in which the memory cells are arranged for each of the global word lines GWLA0 to GWLA3, GWLB0 to GWLB3 and the local wordlines LWL00 to LWL03, LWL10 to LWL13, LWL20 to LWL23, LWL30 to LWL33, Dummy cells (indicated as “dummy cell” in FIG. 2) are arranged for the global control line GREN and the local control line LREN. As a result, the global control line GREN has the same load as each global word line. Accordingly, it becomes easy to match the operation timings of the global word line and the global control line, and the synchronization timing between the memory circuit and the peripheral circuit such as the arithmetic circuit can be easily optimized.

Further, in the semiconductor memory device according to the first embodiment, the local driver is configured using the NAND circuit Nd having two inputs in each memory bank 2, but the local driver is configured using a NAND circuit having three or more input terminals. It may be configured. For example, if the NAND circuit constituting the local driver has 3 inputs, j ³ local word lines can be driven by 3 × j global word lines, and 4 × j if 4 inputs. in the global word line, it is possible to drive the local word lines j ⁴ present. In these cases, in order to select one local word line, if the NAND circuit has 3 inputs, 3 global word lines are selected, and if 4 inputs, 4 global word lines are selected. Needless to say.

  In the configuration example shown in FIG. 2, the global word lines GWLA0 to GWLA3 and the global word lines GWLB0 to GWLB3 are mixedly arranged, but the global word lines GWLA0 to GWLA0 are arranged by the circuit arrangement on the decoder 5 side. The location of GWLA3, GWLB0 to GWLB3 can be set freely. For example, the global word lines GWLA0 to GWLA3 and the global word lines GWLB0 to GWLB3 may be arranged together to facilitate circuit design and circuit analysis. However, if arranged as shown in FIG. 2, the wiring length from the global word line to the local driver can be made shorter and with an equal length.

  The configuration example shown in FIG. 2 is a configuration example when the entire circuit operates with positive logic, but when operating with negative logic, the number of gates of the local driver can be reduced. Become. FIG. 3 shows a configuration example of the memory bank 2 in such a case. As shown in FIG. 3, the set of NAND circuit Nd and inverter circuit Iv in the configuration example of FIG. 2 is replaced with one NOR circuit Nr. However, the configuration using a pass gate often used for the purpose of reducing the cell area of the local driver is not appropriate for the purpose of making the wiring load of the global line uniform.

  FIG. 4 is a diagram schematically showing the arrangement of the global lines shown in FIGS. As shown in FIG. 4, the global lines other than the global word line GWL, that is, the global control line GREN for reading and the global control line GWEN for writing are also arranged at the same pitch as the global word line GWL. The synchronization timing between the line and the control line can be optimized. In this case, it is desirable that the load on the global control lines GREN and GWEN is equal to the load on the global word line GWL as shown in FIG.

  A plurality of these global lines may be selected at the same time. In that case, a wiring delay difference due to crosstalk may occur. Therefore, as a countermeasure, it is possible to provide a new wiring layer in the same layer as the global line between the global lines and shield the global lines. In addition, if the risk of crosstalk can be limited by the arrangement of global lines, it is possible to shield only the necessary parts.

  As described above, according to the semiconductor memory device of the first embodiment, the wiring load in the word line direction that affects high-speed operation is reduced, and at the same time, the circuits are operated in synchronization with only the global line in the same direction. be able to. Therefore, it becomes easy to control the operation timing of each circuit and it is not necessary to secure an unnecessary operation margin, so that the operation of the semiconductor memory device can be speeded up. Further, according to the semiconductor device according to the first embodiment, the operation timings of the respective circuits can be matched at the optimum timing, so that unnecessary current consumption can be reduced. From the above, the semiconductor memory device according to the first embodiment can be applied to a semiconductor integrated circuit such as an image processor that needs to process a large amount of data simultaneously in parallel.

  Although the 1-port SRAM has been described in the first embodiment, the same description applies to other memory circuits such as a DRAM.

1 is a diagram showing a configuration example of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration example of a memory bank illustrated in FIG. 1. FIG. 5 is a diagram showing a modification of the memory bank shown in FIG. 2. It is the figure which showed arrangement | positioning of the global line schematically. It is the figure which showed the structural example of the conventional semiconductor memory device. It is the figure which showed the layout shape of the conventional memory cell. It is the figure which showed another structural example of the conventional semiconductor memory device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Memory bank 3 I / O circuit 4 Arithmetic circuit 5 Decoder GL Global line GWL Global word line LWL Local word line

Claims (7)

A plurality of memory banks formed by dividing a memory cell array composed of a plurality of memory cells arranged in a matrix, and a plurality of global words that are shared by the memory banks and respectively transmit predetermined control signals to the memory banks. In a semiconductor memory device comprising a line,
Each memory bank is
A plurality of local word lines connected to each corresponding row of the memory cells;
A driver for driving each local word line in response to the control signal,
Each of the global word lines is arranged at an interval where two or more of the local word lines can be arranged so that the loads are equal to each other.   2. The semiconductor memory device according to claim 1, wherein the global word lines are arranged at equal intervals in the column direction of the memory cell array. A plurality of input / output circuits for inputting / outputting data to / from each memory bank;
A global control line connected in common by each of the input / output circuits and transmitting an input / output control signal to each of the input / output circuits;
3. The semiconductor memory device according to claim 2, wherein the global control line is arranged so that a load is equal to each global word line.   4. The semiconductor memory device according to claim 3, wherein the global word lines and global control lines are arranged at equal intervals in the column direction of the memory cell array. The memory cell array includes a plurality of dummy cells,
5. The semiconductor memory according to claim 3, wherein the global control line is arranged for each dummy cell so as to have the same relation as the arrangement relation of the global word line to the memory cell. apparatus.   6. The semiconductor memory device according to claim 1, wherein at least one shield line is disposed between each global word line. 7. The semiconductor memory device according to claim 6, wherein the global word lines and shield lines are arranged at equal intervals in the column direction of the memory cell array.

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