JPH0574939A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a signal-delay phenomenon that affects an adjacent signal conductor, by classifying signal conductors into common-input logic circuit groups, and providing a shielding wire between these groups of signal conductors for transmitting a decoded signal from a decoding circuit. CONSTITUTION:Each shielding line SL1 or SL2 is located between signal line groups, such as a group of signal conductors L1, L2, L3, and L4 for transmitting a decoded signal from a decoding circuit DEC1, a group of signal lines L5, L6, L7, and L8 from a decoding circuit DEC2, a group of signal lines L9, L10, L11, and L12 from a decoding circuit DEC 3. Then, a ground line GL is connected to the shielding lines SL1 and S12 through a connection line CL, which is provided at right angles to these shielding lines SL1 and SL2. In these three signal line groups, only one signal line in each group is set to a high level, and therefore two adjacent signal lines can not be changed to a high level at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technique and a technique effective when applied to a signal delay prevention due to a coupling capacitance between wirings. And about effective technology.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, the distance between elements tends to become smaller as the circuit becomes more highly integrated. Also,
For example, in the case of bus wiring, a plurality of signal lines may be arranged in parallel, but even in such a signal line group, the signal line pitch tends to become smaller as the circuit becomes highly integrated. .. However, if the element spacing or signal line pitch is small, the change in signal on one element or signal line will be transmitted to the signal on the other element or signal line adjacent to this via parasitic capacitance such as coupling capacitance between signal lines. There is a problem in that it affects and causes noise and signal delay.

[0003]

Conventionally, in a semiconductor memory device, there has been proposed an invention in which a shield wiring is provided between elements in order to prevent influence between memory elements (Japanese Patent Application No. 63-174113). issue). However, there has been no countermeasure against the signal delay in the signal line group described above. Therefore, a method of preventing the influence (crosstalk) due to the coupling capacitance between the signal lines by providing a shield line between the signal lines and fixing the shield line to the ground level or the like can be considered. However, in the method of providing the shield line between the signal lines, the shield line increases as the number of the signal lines arranged in parallel increases, so that the occupied area of the signal line increases.

An object of the present invention is that in a signal line group on a semiconductor integrated circuit, a change in a signal on one signal line affects a signal on another signal line adjacent to the signal line via a coupling capacitance between the signal lines. An object of the present invention is to provide a signal line layout technique that can prevent a signal from being delayed. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

According to the present invention, only one of the signals after being decoded by the decoder circuit becomes high level or low level for each logical circuit group having a common input. In the signal line group, signals on two adjacent (both sides) signal lines should not change at the same time. In addition, the crosstalk between the signal lines is particularly large when the signals on the adjacent two (both sides) signal lines change at the same time, and it is not so large even if the signal on the signal line on one side changes. It was made. That is, according to the present invention, a signal line group for transmitting a signal decoded by a decoder circuit is divided into groups for each logic circuit group having a common input, and a power supply line or a test is provided between these group signal line groups. A shielded line composed of a signal line for use is arranged. This idea can also be applied to bus wiring in a microcomputer or the like. Further, the signal line groups divided by the shield line are crossed so that the signal lines that are adjacent to each other are not adjacent to each other in the middle.

[0006]

According to the above-mentioned means, since the shield line is interposed, it is possible to prevent the signals on the adjacent two (both sides) signal lines from changing at the same time, and one of them is coupled via the coupling capacitance between the signal lines. The purpose of preventing a phenomenon in which a signal on another signal line adjacent to the signal line is delayed due to a change in the signal on the signal line is achieved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to a signal line group for transmitting an address decode signal of a semiconductor memory. Although not particularly limited, in the memory of this embodiment, there are a decode circuit DEC1 for decoding the address signals A0 and A1 from the outside and a decode circuit DEC2 for decoding the address signals A2 and A3. , A decode circuit DEC3 for decoding the address signals A4 and A5 is provided.
The ADB0 to ADB5 convert the address signals A0 to A5 of the ECL level or the like supplied from the outside into signals of a level suitable for the internal circuits, respectively, and decode the decoding circuits DEC1,
The address buffer circuit is supplied to the DEC2 and DEC3.

In this embodiment, the decoding circuit DEC is used.
Signal line group L for transmitting the signal decoded by 1
1, L2, L3, L4 and signal line groups L5, L for transmitting signals decoded by the decoding circuit DEC2.
6, L7, L8 and signal line groups L9, L10 for transmitting the signals decoded by the decoding circuit DEC3.
Between L11 and L12, as shown enlarged in FIG.
The shield lines SL1 and SL2 are arranged so as to be interposed therebetween. Then, the shield lines SL1 and SL2
Is not particularly limited, but is connected to a ground line GL that gives the ground potential of the circuit by a coupling line CL arranged in a direction substantially orthogonal to this. Above bond line CL
Is formed by a wiring layer different from the wiring layer forming the signal lines L1 to L12.

In the above embodiment, only one of the three signal line groups is set to high level and the other three signal line groups are set to high level.
The signal line of the book is set to low level. Therefore, in each signal line group, signals on adjacent two (both sides) signal lines do not change at the same time. On the other hand, the signal lines L4, L5, L
As for 8 and L9, assuming that there are no shield lines SL1 and SL2, the signals on the signal lines on both sides may change in opposite directions at the same time. For example, when focusing on the signal line L5, when the signal X5 on the signal line L5 changes from the low level to the high level, the signal X4 on the signal line L4 and the signal X6 on the signal line L6 change from the high level to the low level. Sometimes. In this case, if the shield line SL1 is not provided, the signal X5 is delayed due to the change of the signals X4 and X6 via the coupling capacitance between the wirings as shown by the broken line B in FIG. Then the signal lines L4, L
Since the shield line SL1 is arranged between 5, L8 and L9, the influence of the change of the signal X4 via the coupling capacitance is reduced, and the delay of the signal X5 is reduced. Signal line L
The same applies to the signals on 4, L8 and L9. Also,
When the ground wiring GL is arranged in parallel with the signal line group, it is possible to reduce the original line width of the ground wiring in order to guarantee the same current density.

FIG. 4 shows a second embodiment of the present invention. In this embodiment, the signal line groups L1, L2, L3, L4
Are crossed so that the signal lines that were adjacent to each other will not be adjacent from the middle. That is, the signal line L1 of the first row is moved to the third row midway, the signal line L2 of the second row is midway through the first line, and the signal line L3 of the third row is midway through the fourth line. The signal line L4 of the fourth row and the signal line L4 of the fourth row are moved to the second row in the middle. The coupling lines CL1 and CL2 (shown by broken lines) that cross-couple the signal lines are formed by a wiring layer different from the wiring layer that forms the signal lines (shown by solid lines).

Here, the signal line groups L1, L2, L3, L
Although only FIG. 4 is shown, other signal line groups L5, L6,
Similarly, L7, L8 and the signal line groups L9, L10, L11, L12 are made to intersect in the middle of the wiring. In the above embodiment, the case where each signal line group is four has been described. However, when each signal line group is eight or sixteen, or when the number of signal line groups is different. Can also be applied to. Also, the second upper
In the above embodiment, the wiring is shown to intersect only once in the middle of the wiring, but each signal line may be intersected twice or more in the middle. Further, although the ground wiring is used as the shield wire in the above-described embodiment, the power supply voltage Vcc line or the test signal wire may be used as the shield wire.

As described above, in the above embodiment, the signal line groups for transmitting the signals after being decoded by the decoder circuit are grouped for each logical circuit group having a common input, and the group of signal line groups are connected to each other. In addition, for example, since the shield wire composed of the power supply wiring or the test signal wire is arranged, it is possible to prevent the signals on two adjacent (both sides) signal wires from being changed simultaneously by the shield wire, and There is an effect that it is possible to prevent a phenomenon in which a signal on one of the signal lines is delayed by a change in the signal on one of the signal lines via the coupling capacitance of the above-mentioned signal. Further, since the signal line group divided by the shield line is made to intersect so that the signal lines adjacent to each other are not adjacent to each other on the way, the influence of the change in the signal on the other adjacent signal line ( Crosstalk)
Is halved, and the signal delay can be prevented more effectively.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above-described embodiment, the description has been given of the case where the present invention is applied to the signal line group which transmits the signal after being decoded by the decoder circuit, but it is applied when the bus wiring and a plurality of signal lines are adjacently arranged in parallel. can do.

In the above description, the case where the invention made by the present inventor is mainly applied to the structure of the signal line in the semiconductor integrated circuit which is the field of application of the background has been described, but the invention is not limited thereto. Not
It can be used for the configuration of signal lines on a printed circuit board.

[0015]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a signal line group on a semiconductor integrated circuit, a change in a signal on one signal line affects a signal on another signal line adjacent to the signal line via a coupling capacitance between the signal lines, and the signal is delayed. Can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a signal line group for transmitting an address decode signal of a semiconductor memory.

FIG. 2 is a plan view showing an example of a specific layout of a signal line group for transmitting the address decode signal.

FIG. 3 is a time chart showing timings of signals transmitted through a signal line group.

FIG. 4 is a plan view showing another embodiment of the specific layout of the signal line group.

[Explanation of symbols]

L1 to L4, L5 to L8, L9 to L12 Signal line group DEC1, DEC2, DEC3 Decoder (Logic circuit group having common inputs) SL1, SL2 Shield line GL Ground line

Claims (3)

[Claims] 1. A signal line group for transmitting a signal decoded by a decoder circuit is divided into groups for each logic circuit group having a common input, and a shield line is arranged between these group signal line groups. Semiconductor integrated circuit characterized by 2. The shield line also serves as a power line or a test signal line.
The semiconductor integrated circuit described. 3. The semiconductor integrated circuit according to claim 1, wherein the signal line group divided by the shield line is crossed so that the signal lines that are adjacent to each other are not adjacent to each other in the middle. ..