JP2010021574A - Multilayer wiring device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form large decoupling capacitance having s superior high-frequency and high-speed characteristics in providing the decoupling capacitance composed of a parallel-traveling inter-wiring capacitance using a micropitch multilayer wiring structure. <P>SOLUTION: For example, wiring layers M1, M2, M3 are laminated so that directions of pitch arrangements of a plurality of wires M1a-M1h, M2a-M2f, M3a-M3h arranged at pitches in the same direction may cross one another. The wiring layers M1, M2, M3 are mutually connected so that different voltages VDD and VSS are supplied to adjacent wires in each wiring layer M1, M2, M3, respectively. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multilayer wiring device, and more particularly, to a decoupling capacitance by a capacitance between parallel wirings using a fine pitch multilayer wiring structure orthogonal to each other.

  In an integrated circuit (LSI), the supply of power supply voltage and current has been considered stable so far. However, when the number of circuits increases, the chip area increases, and when a large current flows instantaneously through the circuit due to high-speed operation, the voltage drop (power supply noise) of the power supply lines (VDD, VSS) due to power supply wiring resistance or inductance Has occurred and the circuit has malfunctioned.

  Conventionally, it has been known that this problem can be reduced by inserting a decoupling capacitor between power supply lines. That is, in order to reduce the above-described adverse effects, for example, a ceramic capacitor is inserted between the VDD and VSS pins of the package. However, this method is effective for reducing the power supply noise of the input / output driver of the semiconductor chip, but is effective for the power supply noise (spike current) generated in the circuit driven at high speed inside the LSI. Absent.

  As another method, by using a gate oxide film capacitance of a MOSFET (Metal Oxide Field Effect Transistor) and adding a decoupling capacitance between VDD and VSS, a spike current of a circuit driven at high speed by a large current is used. A method for absorbing power and reducing power supply noise is known. Although this method is effective, it has the disadvantage of poor high frequency and high speed characteristics. In addition, a large gate area capacity is required, and a small pinhole in the gate oxide film increases the leakage current between VDD and VSS, which increases power consumption.

  Furthermore, a proposal has been made that a large decoupling capacitance is formed on-chip by configuring a capacitance between parallel wirings of a multilayer wiring over a plurality of wiring layers and alternately connecting VDD and VSS wirings (for example, non-patent literature). 1). In this case, since the capacitance is between the metal wirings, there is an advantage that a decoupling capacitance with good high frequency and high speed characteristics can be provided as compared with the case of the gate oxide film capacitance of the MOSFET described above.

  However, this method is excellent in high-frequency and high-speed characteristics, but cannot cross the capacitor wiring region (area) to pass the signal line. Therefore, it can be arranged only at the periphery of the chip, and even when trying to absorb spike current of a circuit driven at high speed by a large current, there is a disadvantage that it cannot be provided in the vicinity of the circuit. . That is, there is a big problem that it cannot be arranged inside the semiconductor chip.

2001 Symposium on VLSI Circuits Digest of Technical Paper, pp. 201-204

  As described above, conventionally, the capacitance between parallel wirings of multilayer wiring is configured across a plurality of wiring layers, and the VDD and VSS wirings are alternately connected, so that a large decoupling capacitance excellent in high frequency and high speed characteristics can be obtained. Although it can be formed, there is a problem that it cannot be placed inside the semiconductor chip because the signal line cannot be passed through the capacitor wiring region.

  Therefore, the present invention can form a large decoupling capacitor excellent in high-frequency and high-speed characteristics, and can lay a signal line by crossing the capacitor wiring region and can be widely arranged inside a semiconductor chip. The purpose is to provide.

  In order to achieve the above object, in the multilayer wiring device of the present invention, a plurality of wiring layers that are stacked so that the directions of the pitch arrangement of the plurality of wirings arranged in the same direction intersect with each other. And a plurality of contact portions for connecting the plurality of wiring layers to each other such that different first and second potentials are supplied to adjacent wirings of each wiring layer, and the plurality of contacts The portion is provided between a wiring located on the outermost side of a certain wiring layer and a wiring of another wiring layer.

  In the multilayer wiring device of the present invention, a wiring having a multilayer wiring structure in which a plurality of wiring layers in which a plurality of wirings are arranged in the same direction are connected in a vertical direction via a plurality of contact portions. The plurality of wiring layers are stacked so that the pitch arrangement directions of the respective wirings intersect each other, and different first and second potentials are supplied to adjacent wirings. In the wiring device, the VDD and VSS potentials from the VDD and VSS potential supply sources are supplied to at least two of the plurality of wirings in the wiring layer of the plurality of wiring layers. One of the wirings is through the through-hole contact disposed at each intersection with the odd-numbered or even-numbered wiring of the plurality of wirings in the upper or lower wiring layer. Through-hole contacts that are electrically connected to the number or even-numbered wiring and the other one is arranged at each intersection of the plurality of wirings with the even-numbered or odd-numbered wiring in the upper or lower wiring layer It is electrically connected to the even-numbered or odd-numbered wiring via

  Furthermore, in the multilayer wiring device according to the present invention, n (n ≧ 2) wiring layers in which p (i) (i = 1 to k) wirings are arranged in the same direction are provided with a plurality of contacts. A wiring element block having a multilayer wiring structure composed of m layers (m ≧ n), which is connected in the vertical direction via the section, and the n wiring layers have mutually different pitch arrangement directions. The p (i) wirings are stacked so as to intersect with each other, and s (j) wirings (s (j) ≦ p (i) −2, j = 1 to k) are also used as signal lines. A multilayer wiring device in which different first and second potentials are supplied to adjacent wirings, excluding the signal lines, wherein the n wiring layers are arranged in a certain wiring layer. Among the p (i) wirings, at least two wirings have VDD and VSS potentials. VDD and VSS wiring to which VDD and VSS potentials are supplied from a power source, and the VDD wiring is supplied with the VDD potential of adjacent wirings other than the signal lines in the upper or lower wiring layer. Are electrically connected to each other through through-hole contacts arranged at respective intersections, and the VSS wiring is an adjacent wiring other than the signal line in the upper or lower wiring layer. Are electrically connected to the wiring to which the VSS potential is supplied through through-hole contacts arranged at the respective intersections.

  According to the present invention, a multi-layer wiring device capable of forming a large decoupling capacitor excellent in high-frequency and high-speed characteristics, laying a signal line by crossing the capacitor wiring region, and being widely arranged inside a semiconductor chip. Can provide.

  In particular, it is possible to efficiently and systematically define how to supply the first and second potentials to the adjacent wirings of each wiring layer through the through-hole contact.

  In addition, by removing the first and second potentials by eliminating the through-hole contact, it is possible to use a part of the wiring as a signal line. As a result, it is possible to cross the capacitor wiring region and pass the signal line. As a result, it is possible to provide a large decoupling capacitor excellent in high frequency and high speed characteristics in the vicinity of a circuit driven at a high speed by a large current. Become.

  Further, since the shield wiring can be present around the signal line, it is difficult to carry noise in the signal, and an automatic wiring connection algorithm with very few malfunctions due to noise can be realized.

  In addition, when the wiring element block is spread over the entire surface of the chip, it becomes possible to ensure the flatness on the surface of the chip, and to improve the uniformity and yield in the chip when forming the metal wiring. Preferred.

  In addition, since the signal line path can be arbitrarily changed only by deleting or adding the contact between the wiring layers, an effect of shortening the design period in the ASIC business can be expected.

  Furthermore, regarding the application as a wiring architecture, the input / output signal propagation characteristics associated with the wiring structure of the signal lines in the wiring element block are managed as a library centered on the wiring cells, so that the ASIC and SoC based on the library are used. (System on Chip) The design method can be developed.

The perspective view which shows typically the wiring structure of the wiring element block concerning the 1st Embodiment of this invention. The top view which decomposes | disassembles and shows the state of the connection between each wiring layer of the wiring element block shown in FIG. FIG. 2 is an exploded perspective view illustrating a case where a part of the wiring element block illustrated in FIG. 1 is used as a signal line. The disassembled perspective view which shows the example in the case of implement | achieving the wiring structure equivalent to the wiring element block shown in FIG. 1, reducing the number of through-hole contacts concerning the 2nd Embodiment of this invention. FIG. 5 is an exploded perspective view illustrating a case where a part of the wiring element block illustrated in FIG. 4 is used as a signal line. The disassembled perspective view which shows the other example at the time of implement | achieving the wiring structure equivalent to the wiring element block shown in FIG. 1, reducing the number of through-hole contacts concerning the 3rd Embodiment of this invention. FIG. 7 is an exploded perspective view illustrating a case where a part of the wiring element block illustrated in FIG. 6 is used as a signal line. The top view which shows the example of arrangement | positioning of a wiring element block concerning the 4th Embodiment of this invention. The top view concerning the 5th Embodiment of this invention which shows the other example of arrangement | positioning of a wiring element block. The top view of the multilayer wiring apparatus shown in order to demonstrate the wiring method concerning the 6th Embodiment of this invention. FIG. 11 is a plan view showing an example of laying signal lines for the multilayer wiring device shown in FIG. 10. The figure shown in order to demonstrate the wiring characteristic analysis / prediction method of a multilayer wiring apparatus concerning 7th Embodiment of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
1 and 2 show a configuration example of a multilayer wiring device (wiring element block having a multilayer wiring structure) according to a first embodiment of the present invention. FIG. 1 is a perspective view schematically showing the wiring structure of the wiring element block. FIG. 2 is an exploded view of the wiring element block shown in FIG. 1, and shows a plan view of the connection state between the wiring layers. Here, a case where the number of layers (m) is “5” and the number of wiring layers (n) is “3” (where m ≧ n, n ≧ 2) will be described. In this case, of the wiring layers M1 to M5 (M1 to M5 layers), the lower M1 to M3 layers are used as the wiring layers, and the upper M4 and M5 layers (not shown) are used as the power grid. It is done.

  Of the wiring layers M1 to M3, the lower M1 layer has a plurality (p (i), i = 1 to k) wirings (pitch wirings) M1a, M1b,..., M1h. The wirings M1a, M1b,..., M1h in the M1 layer are arranged (pitch arrangement) at the same pitch in the vertical direction of the drawing. The middle M2 layer has a plurality (p (i), i = 1 to k) of wirings (pitch wirings) M2a, M2b,..., M2f. The wirings M2a, M2b,..., M2f in the M2 layer are arranged in a pitch in the direction perpendicular to the M1 layer, that is, in the horizontal direction of the drawing. The upper M3 layer has a plurality (p (i), i = 1 to k) of wirings (pitch wirings) M3a, M3b,..., M3h. The wirings M3a, M3b,..., M3h in the M3 layer are arranged in the direction perpendicular to the M2 layer, that is, in the same vertical direction as the M1 layer in the vertical direction of the drawing.

  As shown in FIG. 2 (a), the M1 layer and the M2 layer include through-hole contacts Via-1aa, -1ab (indicated by □ in the drawing) that are first contacts and through-hole contacts Via that are second contacts. Through the -1ba, -1bb,..., -1bj (shown by circles), the M2 layer and the M3 layer are connected to the first through-hole contact Via- as shown in FIG. 2a, -2ab (□ in the figure) and through-hole contacts Via-2ba, -2bb,..., -2bj (o in the figure) which are the second contacts, respectively, are electrically connected.

  That is, the through-hole contact Via-1aa is the intersection of the M1 layer wiring M1a and the M2 layer wiring M2a. Similarly, the through hole contact Via-1ab is the M1 layer wiring M1h and the M2 layer wiring. It is provided at each intersection with M2f.

  Similarly, the through-hole contact Via-1ba is provided at the intersection of the M1 layer wiring M1a and the M2 layer wiring M2c. The through-hole contact Via-1bb is provided at the intersection of the M1 layer wiring M1a and the M2 layer wiring M2e. The through-hole contact Via-1bc is provided at the intersection of the M1 layer wiring M1b and the M2 layer wiring M2f. The through-hole contact Via-1bd is provided at the intersection of the M1 layer wiring M1c and the M2 layer wiring M2a. The through-hole contact Via-1be is provided at the intersection of the M1 layer wiring M1d and the M2 layer wiring M2f.

  The through-hole contact Via-1bf is provided at the intersection of the M1 layer wiring M1e and the M2 layer wiring M2a. The through-hole contact Via-1bg is provided at the intersection of the M1 layer wiring M1f and the M2 layer wiring M2f. The through-hole contact Via-1bh is provided at the intersection of the M1 layer wiring M1g and the M2 layer wiring M2a. The through-hole contact Via-1bi is provided at the intersection of the M1 layer wiring M1h and the M2 layer wiring M2b. The through-hole contact Via-1bj is provided at the intersection of the M1 layer wiring M1h and the M2 layer wiring M2d.

  On the other hand, the through-hole contact Via-2aa is formed at the intersection of the M2 layer wiring M2a and the M3 layer wiring M3a. Similarly, the through hole contact Via-2ab is connected to the M2 layer wiring M2f and the M3 layer wiring. It is provided at each intersection with M3h.

  Similarly, the through-hole contact Via-2ba is provided at the intersection of the M2 layer wiring M2c and the M3 layer wiring M3a. The through-hole contact Via-2bb is provided at the intersection of the M2 layer wiring M2e and the M3 layer wiring M3a. The through-hole contact Via-2bc is provided at the intersection of the M2 layer wiring M2f and the M3 layer wiring M3b. The through-hole contact Via-2bd is provided at the intersection of the M2 layer wiring M2a and the M3 layer wiring M3c. The through-hole contact Via-2be is provided at the intersection of the M2 layer wiring M2f and the M3 layer wiring M3d.

  The through-hole contact Via-2bf is provided at the intersection of the M2 layer wiring M2a and the M3 layer wiring M3e. The through-hole contact Via-2bg is provided at the intersection of the M2 layer wiring M2f and the M3 layer wiring M3f. The through-hole contact Via-2bh is provided at the intersection of the M2 layer wiring M2a and the M3 layer wiring M3g. The through-hole contact Via-2bi is provided at the intersection of the M2 layer wiring M2b and the M3 layer wiring M3h. The through-hole contact Via-2bj is provided at the intersection of the M2 layer wiring M2d and the M3 layer wiring M3h.

  Here, when the plane size of each wiring layer M1, M2, M3 is, for example, 20 μm square (20 μm × 20 μm), in the CMOS process of 0.13 μm level, the wiring in each wiring layer M1, M2, M3 Are respectively 0.36 μm, 0.4 μm, and 0.36 μm. Therefore, 55 lines, 50 lines, and 55 lines can be laid on the wiring layers M1, M2, and M3 of the above sizes, respectively.

  The wirings M1a, M1h, M2a, M2f, M3a, and M3h arranged on the outermost sides of the wiring layers M1, M2, and M3 are always supplied with the VDD potential (first potential) or the VSS potential from the VDD potential supply source. A VSS potential (second potential) from the source is supplied. For example, a VDD potential is supplied to the wirings (VDD wirings) M1a, M2a, and M3a, and a VSS potential is supplied to the wirings (VSS wirings) M1h, M2f, and M3h. This is because, for example, in the order of the M3 layer, the M2 layer, and the M1 layer through the through-hole contacts Via-1aa and -2aa or the through-hole contacts Via-1ab and -2ab, the VDD potential or the VSS potential, respectively. Is realized.

  Similarly, wirings other than the outermost side of each wiring layer M1, M2, M3 (signal wirings that can be used as signal lines (s (j) lines (s (j) ≦ p (i) −2, j = 1 to k)) are supplied so that the VDD potential and the VSS potential are adjacent to each other, for example, the wiring (odd-numbered wiring) M1c, M1e, M1g, M2c, M2e, M3c, M3e, and M3g The potentials are supplied to the wirings (even-numbered wirings) M1b, M1d, M1f, M2b, M2d, M3b, M3d, and M3f, respectively, which are the through-hole contacts Via-1ba and -1bb. , -1bd, -1bf, -1bh, -2ba, -2bb, -2bd, -2bf, -2bh, or the through-hole contacts Via-1bc, -1be, -1bg, -1bi, -1b , -2bc, -2be, -2bg, -2bi, via -2Bj, respectively, is VDD potential or VSS potential is realized by supplying.

  Assuming that the pitch wiring adjacent wiring capacitance of each wiring layer M1, M2, M3 in a typical 0.13 μm level CMOS process is 0.26 fF / μm, it is about 0 in a 20 μm square area (capacitance wiring region). High-speed decoupling capacitance of 2 pF can be realized.

  Further, in a typical 0.13 μm level CMOS process, the wiring sheet resistance value of each wiring layer M1, M2, M3 is 0.07 Ω / square, and the wiring time constant is 0.1 ps or less, Excellent responsiveness.

  In this way, the adjacent wiring capacity of wiring in each wiring layer M1, M2, M3 (capacitance between parallel wirings using a fine pitch multilayer wiring structure) works as a decoupling capacity between VDD and VSS, so that a large decoupling capacity is obtained. Can be formed.

  In addition, since the large decoupling capacitance is formed by using the capacitance between the parallel wirings, the effect is increased as the fine process technology advances.

  In the multilayer wiring device according to the present embodiment, a part of the wirings in the wiring layers M1, M2, and M3 can be used as signal lines. That is, all the signal wirings other than the outermost wirings of the wiring layers M1, M2, M3, that is, the VDD wirings M1a, M2a, M3a and the VSS wirings M1h, M2f, M3h can be used as signal lines. .

  FIG. 3 shows an example in which a part of the wiring is used as a signal line in the multilayer wiring device according to the present embodiment. 2A shows the connection state between the M1 layer and the M2 layer, and FIG. 2B shows the connection state between the M2 layer and the M3 layer.

  For example, the wiring M2c can be used as a signal line by removing the through-hole contacts Via-1ba and -2ba and removing the supply of the VDD potential to the wiring M2c (with a floating state). In this case, the VDD potential or the VSS potential is always supplied to the other wirings. Therefore, the wiring M2c used as a signal line is shielded by a DC electrode at the periphery, that is, the wiring M2c has a wiring (shield wiring) shielded at a fixed potential of VDD or VSS adjacent to the wiring M2c. Therefore, there is a great advantage that the signal line noise (crosstalk noise) resistance is excellent.

  In this manner, not only the wiring M2c but also the VDD and VSS potentials are removed from the desired signal wiring except for the VDD and VSS wirings, so that the signal wiring is used as a signal line that crosses the capacitor wiring region. It is possible. As a result, the wiring element block can be easily disposed inside the semiconductor chip.

  As described above, in this embodiment, it is possible to realize a multilayer wiring device that has a large decoupling capacitance and enables signal lines to pass, which is impossible with the conventional structure. In other words, this is a major drawback when a large decoupling capacitance is formed on-chip by configuring the capacitance between parallel wirings of a multilayer wiring over a plurality of wiring layers and alternately connecting VDD and VSS wirings. The problem that the signal line cannot be passed through the capacitor wiring region can be solved, and a high-speed decoupling capacitor can be widely arranged in the chip.

  In particular, the multilayer wiring device having this configuration is most likely to be used, for example, in the field of high-frequency / high-speed CMOS. Further, it can be widely used as a wiring architecture in a system LSI having a large chip area.

  In the first embodiment described above, the number of layers is “5”, and the M1, M2, and M3 layers are used as wiring layers. However, the present invention is not limited to this. For example, the M1 layer, The M2, M3, and M4 layers can also be used as wiring layers, and the number of layers is not limited to “5”.

(Second Embodiment)
FIGS. 4A and 4B show a configuration example of a multilayer wiring device (wiring element block having a multilayer wiring structure) according to the second embodiment of the present invention. Here, an example in which a wiring structure equivalent to the wiring element block having the configuration shown in FIG. 1 is realized by reducing the number of through-hole contacts between the wiring layers M1 and M2 will be described.

  As shown in FIG. 6A, by deleting the through-hole contacts Via-1ba, -1bb, -1bi, -1bj, a wiring structure equivalent to the wiring element block having the configuration shown in FIG. 1 can be realized. .

  For example, when the through-hole contact Via-1ba is deleted, the supply of the VDD potential to the wiring M2c is performed from the wiring M3a through the through-hole contact Via-2ba (see FIG. 5B). Similarly, when the through-hole contact Via-1bb is deleted, the supply of the VDD potential to the wiring M2e is performed from the wiring M3a through the through-hole contact Via-2bb (see FIG. 5B). Similarly, when the through-hole contact Via-1bi is deleted, the VSS potential is supplied to the wiring M2b from the wiring M3h via the through-hole contact Via-2bi (see (b) of FIG. 11). Similarly, when the through-hole contact Via-1bj is deleted, the VSS potential is supplied to the wiring M2d from the wiring M3h via the through-hole contact Via-2bj (see FIG. 5B).

  As described above, in the wiring element block having the configuration shown in FIG. 1, the through-hole contacts Via-1ba, -1bb, -1bi, -1bj can be deleted, thereby simplifying the process.

  Further, as shown in FIGS. 5A and 5B, in the multilayer wiring device according to the second embodiment, as in the case of the first embodiment described above, a part of the wiring is connected to the signal line. It can be used as

  That is, in the configuration in which the through-hole contacts Via-1ba, -1bb, -1bi, -1bj are deleted, for example, as shown in FIG. 9A, the through-hole contact Via-1be is deleted, and the VSS potential with respect to the wiring M1d By removing the supply, the wiring M1d can be used as a signal line. In this case, either the VDD potential or the VSS potential is always supplied to the other wirings. Therefore, the wiring M1d used as the signal line is excellent in signal line noise resistance.

  Note that the signal wiring can be used as a signal line that crosses the capacitor wiring region by removing the supply of the VDD and VSS potentials to desired signal wirings, not limited to the wiring M1d, except for the VDD and VSS wirings. Of course it is possible.

(Third embodiment)
FIGS. 6A and 6B show a configuration example of a multilayer wiring device (wiring element block having a multilayer wiring structure) according to the third embodiment of the present invention. Here, an example in which a wiring structure equivalent to the wiring element block having the configuration shown in FIG. 1 is realized by reducing the number of through-hole contacts between the wiring layers M2 and M3 will be described.

  As shown in FIG. 6B, the wiring structure equivalent to the wiring element block having the configuration shown in FIG. 1 can be realized by deleting the through-hole contacts Via-2ba, -2bb, -2bi, -2bj. .

  For example, when the through-hole contact Via-2ba is deleted, the supply of the VDD potential to the wiring M2c is performed from the wiring M1a via the through-hole contact Via-1ba (see FIG. 5A). Similarly, when the through-hole contact Via-2bb is deleted, the supply of the VDD potential to the wiring M2e is performed from the wiring M1a via the through-hole contact Via-1bb (see FIG. 5A). Similarly, when the through-hole contact Via-2bi is deleted, the VSS potential is supplied to the wiring M2b from the wiring M1h via the through-hole contact Via-1bi (see (a) of FIG. 11). Similarly, when the through-hole contact Via-2bj is deleted, the VSS potential is supplied to the wiring M2d from the wiring M1h via the through-hole contact Via-1bj (see (a) of FIG. 11).

  As described above, in the wiring element block having the configuration shown in FIG. 1, the through-hole contacts Via-2ba, -2bb, -2bi, -2bj can be deleted, and the process can be simplified.

  Also, as shown in FIGS. 7A and 7B, in the multilayer wiring device according to the third embodiment, part of the wiring is connected to the signal line as in the case of the first embodiment described above. It can be used as

  That is, in the configuration in which the through-hole contacts Via-2ba, -2bb, -2bi, -2bj are deleted, for example, as shown in FIG. 9A, the through-hole contact Via-1ba is deleted and the VDD potential with respect to the wiring M2c is obtained. Can be used as a signal line. In this case, either the VDD potential or the VSS potential is always supplied to the other wirings. Therefore, the wiring M2c used as the signal line has excellent signal line noise resistance.

  Note that the signal wiring can be used as a signal line that crosses the capacitor wiring region by removing the supply of the VDD and VSS potentials to the desired signal wiring, not limited to the wiring M2c but the VDD and VSS wirings. Of course it is possible.

(Fourth embodiment)
FIG. 8 shows an arrangement example of a multilayer wiring device (wiring element block having a multilayer wiring structure) according to the fourth embodiment of the present invention. Here, a case where the wiring element block of the present invention is embedded under a 100 * 100 μm square power grid (hereinafter, Pw grid) laid on a semiconductor chip having a size of 20 * 20 mm square will be described as an example. .

  For example, in the 20 * 20 mm square semiconductor chip 11, when the upper M4 layer and M5 layer are used as a power grid, 16 wiring regions 13 are arranged in a grid pattern. A first VDD / VSS pair 15 and a second VDD / VSS pair 17 are provided at the periphery of each wiring region 13 (in this example, the grid side on which a 100 * 100 μm square Pw grid is laid). It is arranged.

  The first VDD / VSS pair 15 includes a VDD power supply line 15a and a VSS power supply line 15b provided in the M4 layer, and is arranged in the horizontal direction of the drawing. The second VDD / VSS pair 17 includes a VDD power line 17a and a VSS power line 17b provided in the M5 layer, and is disposed in the vertical direction of the drawing.

  Of the first and second VDD and VSS pairs 15 and 17, the wiring element block having the configuration shown in FIG. 1, for example, is provided below the first VDD and VSS pair 15 arranged in the horizontal direction of the drawing. 21 is embedded. That is, 20 wiring element blocks 21 using three layers of M1, M2, and M3 as wiring layers are embedded (100 in total).

  On the other hand, under the second VDD and VSS pair 17 arranged in the vertical direction of the drawing, four layers of M1, M2, M3, and M4 (not shown) were used as wiring layers, respectively. 20 wiring element blocks 31 (100 in total) are embedded.

  As shown in the drawing, when a Pw grid of 100 * 100 μm square size is laid on the entire semiconductor chip 11 of 20 * 20 mm square size, wiring element blocks 21 and 31 are respectively embedded under the Pw grid. Thus, a decoupling capacitance of 200 nF in total can be formed between the VDD and VSS power supply lines. In this case, the CR time constant of the decoupling capacitance is 1 ps or less, and high-speed current noise and capacitive coupling noise can be easily absorbed.

  In the present embodiment, the first VDD, VSS pair 15 is formed by using the M5 layer, and the second VDD, VSS pair 17 is formed by using the M4 layer. It is also possible to embed the wiring element block 31 under the VSS pair 15.

  Further, when the planar size of the wiring element blocks 21 and 31 is 20 μm square, the CR time constant is 1 ps or less, which is a response speed that is too high considering the case where it is used as a decoupling capacitor. However, it is not limited to this size. For example, a response characteristic of about 100 GHz is necessary to cope with a clock response of 10 GHz. For that purpose, there is no problem even if it is increased to about 50 μm square. However, the CR time constant is calculated assuming a 0.13 μm level CMOS process, and it is a well-known fact that it varies depending on the technical level.

(Fifth embodiment)
FIG. 9 shows an arrangement example of a multilayer wiring device (wiring element block having a multilayer wiring structure) according to the fifth embodiment of the present invention. Here, a case where the wiring element block of the present invention is embedded in the entire surface of a semiconductor chip having a size of 20 * 20 mm square will be described as an example.

  For example, in the 20 * 20 mm square semiconductor chip 11 ′, when the upper M4 layer and the M5 layer are used as the power grid, the grid sides where the 100 * 100 μm square Pw grid is laid are respectively One VDD / VSS pair 15 ′ and a second VDD / VSS pair 17 ′ are arranged.

  The first VDD / VSS pair 15 ′ is composed of a VDD power line 15 a ′ and a VSS power line 15 b ′ provided in the M5 layer, and is disposed in the horizontal direction of the drawing. The second VDD / VSS pair 17 ′ includes a VDD power line 17 a ′ and a VSS power line 17 b ′ provided in the M4 layer, and is disposed in the vertical direction of the drawing.

  Of the first and second VDD and VSS pairs 15 ′ and 17 ′, the second VDD and VSS pair 17 ′ disposed in the vertical direction of the drawing are respectively shown in FIG. 1, for example. The wiring element blocks 21 having the configuration are embedded by 20 pieces (100 pieces in total).

  On the other hand, between the second VDD and VSS pair 17 'corresponding to the vertical direction of the drawing, including the first VDD and VSS pair 15' disposed in the horizontal direction of the drawing (the wiring region of FIG. 8). 13), there are 100 wiring element blocks 31 each using four layers (not shown) of M1, M2, M3, and M4 as wiring layers (400 in total). Embedded.

  As shown in the drawing, when a Pw grid of 100 * 100 μm square size is laid over the entire semiconductor chip 11 ′ of 20 * 20 mm square size, that is, the wiring element block 21, By embedding 31 each, the decoupling capacity can be greatly increased compared to the fourth embodiment described above. Therefore, fluctuations in the power supply voltage can be suppressed and the operation of the LSI circuit can be made extremely stable.

  Further, when the wiring element blocks 21 and 31 are respectively embedded in the entire surface of the semiconductor chip 11 ′, in order to maintain the uniformity of the film thickness when forming the wiring layer in the CMP (Chemical Mechanical Polishing) technique, A process of laying a rectangular wiring pattern (dummy pattern) in an area where the wiring density is low becomes unnecessary. As a result, problems such as deterioration in wiring signal transmission performance and setting mistakes in wiring mask design can be solved. It is also effective for improving process uniformity and resistance to electrostatic breakdown.

  In the present embodiment, the M4 layer is used for forming the first VDD / VSS pair 15 ′ and the M5 layer is used for forming the second VDD / VSS pair 17 ′. It is also possible to embed the wiring element block 31 in the direction, and in any case, it is convenient (efficiency) to increase the decoupling capacitance by arranging more wiring element blocks 31 having a large number of wiring layers. ) Is good.

(Sixth embodiment)
10 and 11 show a wiring method of a multilayer wiring device (wiring element block having a multilayer wiring structure) according to the sixth embodiment of the present invention. Here, a case where six wiring element blocks are spread so as not to overlap each other will be described as an example. 10 shows the basic structure of the multilayer wiring device according to the supply of the VDD and VSS potentials, and FIG. 11 shows an example of laying signal lines for the multilayer wiring device having the configuration shown in FIG.

  In FIG. 10, six wiring element blocks 21a, 21b,..., 21f are arranged in an area (for example, a power supply wiring area and a signal wiring area between circuit blocks) on the semiconductor chip 11a in a matrix. Arranged in a shape.

  Each of the wiring element blocks 21a, 21b,..., 21f is composed of 12 (p (i), i = 1 to k) wirings composed of, for example, M3 layers (n layers) arranged in the horizontal direction in the drawing. It has 22a, 22b, 22c, 22d, 22e, 22f, 22g, 22h, 22i, 22j, 22k, 22m, and is composed of, for example, M2 layers (n-1 layers) arranged in the vertical direction of the drawing, respectively. Twelve wirings 23a, 23b, 23c, 23d, 23e, 23f, 23g, 23h, 23i, 23j, 23k, and 23m are provided.

  In each wiring element block 21a, 21b,..., 21f, the outermost wiring (first and second potential wirings) of each layer is common VSS wiring (second power supply line) 22a, 23a or common VDD wiring. (First power line) 22m and 23m are connected. In this example, the VSS wiring 22a and the VDD wiring 22m are laid by the M3 layer, and the VSS wiring 23a and the VDD wiring 23m are laid by the M2 layer.

  Of the twelve wirings 22a, 22b, 22c, 22d, 22e, 22f, 22g, 22h, 22i, 22j, 22k, and 22m, the wirings 22b, 22c, 22d, and 22e excluding the VSS wiring 22a and the VDD wiring 22m. , 22f, 22g, 22h, 22i, 22j, and 22k are assigned as signal wirings (s (j) lines (s (j) ≦ p (i) −2, j = 1 to k)) that can also be used as signal lines. It has been. The signal wirings 22b, 22d, 22f, 22h, and 22j are each set to the VDD potential, and the signal wirings 22c, 22e, 22g, 22i, and 22k are each set to the VSS potential.

  Similarly, of the twelve wirings 23a, 23b, 23c, 23d, 23e, 23f, 23g, 23h, 23i, 23j, 23k, 23m, the wirings 23b, 23c, except for the VSS wiring 23a and the VDD wiring 23m, 23d, 23e, 23f, 23g, 23h, 23i, 23j, and 23k are signal wirings that can also be used as signal lines (s (j) lines (s (j) ≦ p (i) −2, j = 1 to k)). ). The signal lines 23b, 23d, 23f, 23h, and 23j are set to the VDD potential, and the signal lines 23c, 23e, 23g, 23i, and 23k are set to the VSS potential.

  As described above, in each of the wiring blocks 21a, 21b,..., 21f, VDD and VSS potentials are supplied to adjacent wirings to form VDD and VSS decoupling capacitors due to the parallel wiring wiring capacitance. In order to increase the VDD and VSS decoupling capacitance, it is desirable to arrange the wiring of each layer at the minimum pitch. This is because the inter-wiring capacitance is the largest.

  On the other hand, when the signal line (shown thick line) 24 is laid in the multilayer wiring apparatus having the configuration shown in FIG. 10, for example, as shown in FIG. 11, the wiring connection within the same block is made between the M2 layer and the M3 layer. This is realized by providing an intra-block connection Via (contact wiring). For example, the wirings 24b-1 and 24b-2 in the wiring element block 21b are connected to each other by providing an intra-block connection Via (contact wiring) 25b-1 between the M2 layer and the M3 layer positioned above and below.

  Further, wiring connection between adjacent blocks (blocks adjacent in the horizontal direction of the drawing) is realized by providing an inter-block connection wiring (M2 layer) 26 between both blocks. For example, the wiring 24b-2 of the wiring element block 21b and the wiring 24a-1 of the wiring element block 21a are connected to each other by providing an inter-block connection wiring 26 between the blocks 21a and 21b.

  Similarly, connection of wiring between adjacent blocks (blocks adjacent in the vertical direction in the drawing) is realized by providing an inter-block connection wiring (M3 layer) 27 between both blocks. For example, the wiring 24b-3 of the wiring element block 21b and the wiring 24e-1 of the wiring element block 21e are connected to each other by providing an inter-block connection wiring 27 between the blocks 21b and 21e.

  In this case, in each of the wiring element blocks 21a, 21b,..., 21f, all of the wirings used as the signal lines 24 have the through-hole contacts for supplying VDD or VSS potentials deleted beforehand (FIG. 3). reference). In other words, as described above, for example, in the wiring element block 21b, VDD for the wirings 22d, 22g, 22j, 22k, 23c, and 23f used as the signal lines 24b (24b-1, 24b-2,...) The supply of the VSS potential has been removed.

  A low-resistance conductive material is used for the intra-block connection Via 25b-1 and the inter-block connection wirings 26 and 27. Alternatively, a fuse material that can be programmed from a high resistance state to a low resistance state can be used.

  According to such a configuration, not only can a multilayer wiring device having a large decoupling capacity be arranged in the power supply wiring region and the signal wiring region between circuit blocks on the semiconductor chip 11a, but also the arbitrary signal lines 24 can be freely set. It can be easily routed with a certain degree.

  In addition, it is possible to easily provide a wiring to which the VDD and VSS potentials are supplied in the vicinity of the arbitrary signal line 24. That is, a wiring to which VDD and VSS potentials are supplied is arranged close to the signal line 24. By doing so, it is possible to make the wiring supplied with the VDD and VSS potentials work as an electromagnetic field shield. For this reason, there is a great advantage that signal noise (signal quality) can be remarkably improved by reducing the mixing of electromagnetic field noise into the signal line 24. Therefore, it is suitable for realizing an automatic wiring connection algorithm with very few malfunctions due to noise.

  Further, since the wiring connection path can be arbitrarily changed by changing the position of the contact, it is particularly effective for shortening the design period in the ASIC business.

  In the case of the present embodiment, the wirings assigned as signal lines are electrically connected in the same block, and thus can basically be used as only one signal line. In this respect, there is a drawback that the wiring density is reduced as compared with the conventional wiring method. However, this disadvantage can be easily solved by adding means for cutting (electrically insulating) the wiring at an arbitrary position in the block.

  Further, the case where the M2 layer and the M3 layer are used has been described as an example. However, the present invention is not limited to this. For example, the present invention can be similarly applied to a multilayer wiring device having a multilayer wiring structure of three or more layers.

(Seventh embodiment)
FIG. 12 shows a wiring characteristic analysis / prediction method for a multilayer wiring device according to a seventh embodiment of the present invention.

  11A is an example of laying signal lines for the multilayer wiring apparatus shown in FIG. 11. For example, the wiring element block 21b includes twelve wirings 22a arranged in the left-right (X) direction in the drawing. 22b, 22c, 22d, 22e, 22f, 22g, 22h, 22i, 22j, 22k, 22m and twelve wirings 23a, 23b, 23c, 23d, 23e, which are arranged in the vertical (Y) direction of the drawing. 23f, 23g, 23h, 23i, 23j, 23k, and 23m. Therefore, even when all the wirings (except for the VSS wirings 22a and 23a and the VDD wirings 22m and 23m) are used as signal lines, the wiring element block 21b is a basic block having 40 terminals.

  FIG. 6B shows an example of a characteristic library for the wiring element block 21b obtained from FIG. Here, the wirings 22b to 22k in the X direction and the wirings 23b to 23k in the Y direction are assigned to X values 1 to 10 and Y values 1 to 10, respectively.

  Further, here, a transmission characteristic τ (delay value) is taken as a signal transfer function (input / output signal propagation characteristic). Other S-parameters can be used as the signal transfer function.

  That is, the signal transfer function between the 40 terminals is calculated in advance for every combination, and the result is managed as a library centered on the wiring cells. As a result, the characteristics of the wiring installed between arbitrary blocks can be accurately predicted by performing simple four arithmetic operations according to the wiring connection paths while referring to this library.

  Note that the characteristic library is not limited to this form, and other forms may be used.

  As described above, in any of the embodiments, the wiring arrangement directions of the wiring layers positioned above and below are shown to be orthogonal to each other, but they need not be parallel and are not necessarily limited to the orthogonal directions. It is not a thing.

  In addition, although the VDD and VSS wirings are installed on the outermost side of each wiring layer, the present invention is not limited to this, and for example, wirings that cross all signal wirings located above and below can be installed as VDD and VSS wirings.

  In addition, this multilayer wiring device can be used as a capacitive element having a large capacitance value and excellent high-frequency characteristics by being connected between signal lines other than the VDD and VSS power supplies, for example. In particular, it can be used as a feedback capacitor in an analog circuit or as a capacitive element of a switched capacitor circuit. It can also be used as a voltage boosting capacitor of a digital circuit.

  In addition, the present invention is not limited to the above (each) embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if several constituent requirements are deleted from all the constituent requirements shown in the (each) embodiment, the problem (at least one) described in the column of the problem to be solved by the invention can be solved. When the effect (at least one of the effects) described in the “Effect” column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

M1 to M3 ... wiring layers (M1, M2, M3 layers)
M1a, M1b, ..., M1h ... wiring M2a, M2b, ..., M2f ... wiring M3a, M3b, ..., M3h ... wiring Via-1aa, -1ab ... through-hole contact Via-1ba, -1bb, ..., -1bj ... Hole contact Via-2aa, -2ab ... Through-hole contact Via-2ba, -2bb, ..., -2bj ... Through-hole contact 11, 11 ', 11a ... Semiconductor chip 13 ... Wiring region 15, 15' ... First VDD, VSS pair 15a, 15a '... VDD power supply line 15b, 15b' ... VSS power supply line 17, 17 '... Second VDD, VSS pair 17a, 17a' ... VDD power supply line 17b, 17b '... VSS power supply line 21, 21a, 21b, ..., 21f ... Wiring element block 22a ... VSS wiring 22b, 22c, 22d, 22e, 22 , 22g, 22h, 22i, 22j, 22k ... wiring 22m ... VDD wiring 23a ... VSS wiring 23b, 23c, 23d, 23e, 23f, 23g, 23h, 23i, 23j, 23k ... wiring 23m ... VDD wiring 24, 24b ... signal Lines 24a-1, 24b-1, 24b-2, 24b-3, 24e-1 ... wiring 25b-1 ... intra-block connection Via
26, 27: Inter-block connection wiring 31: Wiring element block

Claims (10)

A plurality of wiring layers stacked in such a manner that the directions of the pitch arrangement of the plurality of wirings arranged in the same direction intersect each other;
A plurality of contact portions for connecting the plurality of wiring layers to each other so that different first and second potentials are supplied to adjacent wirings of each wiring layer;
The multi-layer wiring device, wherein the plurality of contact portions are provided between a wiring located on the outermost side of a certain wiring layer and a wiring of another wiring layer.   The plurality of contact portions include a first contact inevitably provided between a wiring located on the outermost side of a certain wiring layer and a wiring located on the outermost side of another wiring layer, and the outermost side of a certain wiring layer. 2. The multilayer wiring device according to claim 1, further comprising: a second contact that is selectively provided between the wiring located in the wiring and the wiring located outside the outermost side of the other wiring layer.   Wirings located on the outermost side of the wiring layer are VDD and VSS wirings connected to a VDD and VSS potential supply source, and wirings located on the outermost side of the wiring layer can also be used as signal lines. The multilayer wiring device according to claim 2, wherein the signal wiring is possible. A wiring element block having a multilayer wiring structure in which a plurality of wiring layers in which a plurality of wirings are arranged in a pitch in the same direction is connected in a vertical direction via a plurality of contact portions,
The plurality of wiring layers are stacked so that the pitch arrangement directions of the respective wirings intersect each other, and different first and second potentials are supplied to adjacent wirings,
Of the plurality of wiring layers, among the plurality of wirings in a certain wiring layer, VDD and VSS potentials from the VDD and VSS potential supply sources are supplied to at least two wirings. One is electrically connected to the odd-numbered or even-numbered wiring through through-hole contacts respectively arranged at the intersections of the plurality of wirings with the odd-numbered or even-numbered wiring in the upper or lower wiring layer And the other one is connected to the even-numbered or odd-numbered wiring via a through-hole contact disposed at each intersection with the even-numbered or odd-numbered wiring of the plurality of wirings in the upper or lower wiring layer. A multilayer wiring device characterized by being electrically connected.   5. The multilayer wiring device according to claim 4, wherein at least two wirings to which the VDD and VSS potentials from the VDD and VSS potential supply sources are supplied are positioned on the outermost side of the plurality of wirings. . p (i) n (n ≧ 2) wiring layers in which wirings of i (i = 1 to k) are pitch-arranged in the same direction are connected in the vertical direction via a plurality of contact portions. A wiring element block having a multilayer wiring structure composed of layers (m ≧ n),
The n wiring layers are stacked so that the pitch arrangement directions of the respective wirings intersect each other, and s (j) (s (j) ≦ p) of the p (i) wirings. (I) -2, j = 1 to k) are assigned as signal wirings that can also be used as signal lines, and different first and second potentials are supplied to adjacent wirings excluding the signal lines. A wiring device,
Of the p (i) wirings in a certain wiring layer of the n wiring layers, at least two wirings are VDD and VSS wirings supplied with VDD and VSS potentials from a VDD and VSS potential supply source. Yes,
The VDD wiring is connected to the wiring to which the VDD potential is supplied among the adjacent wirings other than the signal line in the upper or lower wiring layer and through-hole contacts respectively disposed at the intersections. The VSS wiring is electrically connected, and the VSS wiring is disposed at each intersection with the wiring to which the VSS potential is supplied among the adjacent wirings other than the signal line in the upper or lower wiring layer. A multilayer wiring device characterized in that it is electrically connected via a through-hole contact.   The multilayer wiring device according to claim 6, wherein the VDD and VSS wirings are respectively located on the outermost side of the p (i) wirings.   The multilayer wiring device according to claim 6, wherein the wiring element block is disposed so as to overlap the power grid wiring of the semiconductor chip in a plan view.   9. The multilayer wiring device according to claim 8, wherein the wiring element block is arranged in a power supply wiring region and a signal wiring region between circuit blocks on the semiconductor chip. A plurality of wiring element blocks are arranged in a matrix so as not to overlap each other,
VDD and VSS power supply lines to which VDD and VSS wirings of each wiring element block are connected in common, inter-block connection wiring for connecting signal lines extending between a plurality of wiring element blocks, and in each wiring element block 10. The multilayer wiring device according to claim 9, further comprising contact wiring for connecting signal lines extending over the upper and lower wiring layers.

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