JP2014029903A - Semiconductor device and design device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dummy cell columns and spacing between adjacent memory macros in an LSI containing multiple memory macros such as a system LSI, thereby cutting a chip area.SOLUTION: Memory mats each having the same number of memory cells arranged in a row or a column direction are placed adjoining each other via tie cells without placing dummy cells on sides each having the same number of rows or columns. The tie cells have almost the same layout pattern as the memory cells, and can have memory cells placed adjoining each other on both sides in the row direction or column direction. Word lines or bit lines are electrically separated by restraining distortion in resolution pattern in the periphery of the memory mats while maintaining the continuity and periodicity of the layout pattern. An LSI design device is provided with row direction and column direction tie cells in a library, extracts memory mats each having the same number of memory cells placed in the row or column direction from an input net list, and outputs layout information on memory mats placed adjoining each other via appropriate tie cells.

Description

  The present invention relates to a semiconductor integrated circuit device including a plurality of memory macros and a design apparatus therefor, and can be suitably used particularly for reducing a chip area.

  As the functionality of semiconductor products such as system LSI (Large Scale Integrated Circuit) in recent years has increased and the amount of processing data has increased, the memory capacity and area of SRAM (Static Random Access Memory), etc. occupying the chip has been increasing. ing. In response to this, reduction of the memory cell size, reduction of memory peripheral circuits, reduction by banking, and the like have been performed. However, each of these measures is also tuned to the limit, and further area reduction in each part cannot be expected in the future.

  Some spacing is required between the memory macro and other circuit areas, including a logic circuit area composed of standard cells arranged around the memory macro. Further, when the memory macro is divided into a memory mat in which memory cells are arranged two-dimensionally and a peripheral circuit composed of an address decoder, a word line driving circuit, a sense amplifier and a bit line driving circuit, the memory macro is connected between the memory mat and the peripheral circuit. In addition, spacing is necessary. This spacing is defined according to the layout rule. For example, when circuits with different well structures are adjacent to each other, it is necessary to form an insulating layer such as STI (Shallow Trench Isolation) between the wells in order to insulate both wells. Necessary.

  A memory mat is configured by arranging memory cells two-dimensionally, but dummy cells that do not function as memory elements are arranged around the memory cells that actually function as memory elements, although they have substantially the same layout as the memory cells. Has been. Since memory cells are periodically arranged in the memory mat, a layout pattern, that is, a mask pattern is periodically arranged in each photolithography process, but this periodicity is cut off in the peripheral portion of the memory mat. It is known that the resolution is disturbed. The dummy pattern is arranged in the periphery of the memory mat in order to prevent such a disturbance in resolution around the memory mat from affecting the circuit operation of the memory. Japanese Patent Laid-Open No. 2004-133867 discloses that “the continuity of unit cells is maintained by providing dummy cells that are configured in substantially the same pattern as unit cells (memory cells) and do not perform circuit operation, and that photo-etching conditions and the like in the unit cell arrays are substantially omitted. Since it can be made uniform, it is possible to prevent unit cell defects from occurring. " Furthermore, Patent Document 2 discloses a technique that can prevent an insulation failure that occurs due to pattern disturbance in a transistor included in a dummy cell. Since the transistor included in the dummy cell does not function at all, it is terminated so as to be turned off. However, in Patent Document 2, there is a risk that current may leak and further be short-circuited depending on the disturbance of the resolution pattern. In other words, an invention for preventing the occurrence of such defects is disclosed.

  FIG. 1 of Patent Document 1 shows an SRAM layout including four memory mats. Dummy cells (4A to 4D) are arranged on four sides at the periphery of each memory mat (3A to 3D). Spacing is provided between the memory mats (3A to 3D), the X decoders (5A and 5B), the Y decoders (6A to 6D), and the peripheral circuits (7A and 7B).

Japanese Patent Laid-Open No. 61-214559 Japanese Patent Laid-Open No. 06-314778

  In recent years, higher performance of semiconductor products and larger scale of processing data have been accompanied by higher performance accompanied by improved processing speed, leading to an increase in the number of memory macros mounted. Due to the recent high integration of semiconductors, the memory cannot be sufficiently speeded up, so that the capacity of each memory cannot be increased while satisfying the speed performance. For this reason, there is a tendency that many high-speed memories with a small capacity are mounted.

  At this time, the area of the dummy cells arranged in the periphery of the memory mat, the spacing between the memory macro and the peripheral logic circuit area, and the spacing area between the memory mat in the memory macro and the peripheral circuit such as the decoder are determined. The ratio of the total to the chip area is increasing.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  According to one embodiment, it is as follows.

  That is, in a semiconductor integrated circuit device including a plurality of memory macros, dummy cells are not arranged on the same number of sides of the memory mat in which the same number of memory cells are arranged in the row direction or the column direction, and the connection cells are not arranged. The memory mats are arranged adjacent to each other. The connection cell has substantially the same layout pattern as the memory cell, and the memory cells can be adjacently arranged on both sides in the row direction or the column direction, and the continuity and periodicity of the layout pattern at that time are maintained. Thereby, the word line or the bit line is electrically separated while suppressing the disturbance of the resolution in the peripheral portion of the memory mat.

  The LSI design apparatus includes row cells and column cells connected in the cell library, extracts memory mats in which the same number of memory cells are arranged in the row direction or column direction from the input netlist, and appropriately connects cells. The layout information in which the memory mats are arranged adjacent to each other is output via the.

  The effect obtained by the one embodiment will be briefly described as follows.

  That is, dummy cells and spacing between memory mats can be eliminated, and the chip area can be reduced.

FIG. 1 is an explanatory diagram illustrating a layout layout of memory macros according to the first embodiment. FIG. 2 is an explanatory diagram illustrating a layout layout of memory macros according to the second embodiment. FIG. 3 is a layout diagram (impurity diffusion layer L, gate wiring layer FG, contact layer CONT, and first metal wiring layer M1) showing in detail a design example of the connection cell. FIG. 4 is a layout diagram (contact layer CONT and first metal wiring layer M1) showing a detailed design example of the connecting cell. FIG. 5 is a layout diagram (first via layer V1 and second metal wiring layer M2) showing a detailed design example of the connection cell. FIG. 6 is a layout diagram (second via layer V2 and third metal wiring layer M3) showing in detail a design example of a connection cell. FIG. 7 is an equivalent circuit diagram showing in detail a design example of a connection cell. FIG. 8 is an explanatory diagram showing the layout of the entire semiconductor chip including the memory macro in the second embodiment. FIG. 9 is a flowchart illustrating the operation of the design apparatus according to the fourth embodiment. FIG. 10 is a schematic diagram for explaining memory division by the RTL wrapper.

1. First, an outline of a typical embodiment disclosed in the present application will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

[1] <Adjacent of two mats by connecting cells>
A semiconductor device including a first memory macro (20_1) and a second memory macro (20_2), which is configured as follows.

  The first memory macro (20_1) includes a first memory mat (21_1) in which memory cells (10) are arranged in L rows × M columns (where L and M are positive integers). The second memory macro (20_2) has an address line (25_2) and a data line (26_2) different from the first memory macro, and the memory cell (10) having the same layout as the memory cell has N 2nd memory mat (21_2) arranged in rows (where N is a positive integer) × M columns.

  One side of the M columns of the first memory mat and one side of the M columns of the second memory mat are connected cells having the same layout size as the memory cells. One row × the M columns (11_1 to 11_M) is arranged in contact with both the one side of the first memory mat and the one side of the second memory mat.

  In the connection cell, the well layer, the impurity diffusion layer, and the gate wiring layer have the same layout as the memory cell or a symmetrical layout with the cell boundary line as an axis.

  As a result, dummy cells and spacing between memory mats can be eliminated, and the chip area can be reduced.

[2] <Separation of word lines in connecting cells>
In item 1, the semiconductor device is configured as follows. A plurality of memory cells included in each column of the first memory macro share a first word line and a first power supply line or a first ground line. A plurality of memory cells included in each column of the second memory macro share a second power line or a second ground line corresponding to the second word line and the first memory macro, respectively. The connecting cell electrically separates the first word line and the second word line, and electrically connects the first power line or the first ground line and the corresponding second power line or the second ground line. Connect.

  As a result, the word lines are separated between adjacent memory mats to enable independent memory operation, and the power supply line and / or the ground line can be connected between adjacent memory mats to stabilize the power supply voltage. it can.

[3] <Continuity of layout pattern>
In item 2, the semiconductor device is configured as follows. In the connection cell, all layout layers other than the wiring corresponding to the first word line or the second word line have the same layout as the memory cell or a symmetrical layout about the cell boundary line.

  As a result, the continuity and periodicity of the pattern are maintained in all layout layers other than the layers that need to be electrically separated.

[4] <Separation of bit lines in connecting cells>
In item 1, the semiconductor device is configured as follows. The first memory macro shares a first bit line and a first power supply line or a first ground line for each column. The second memory macro shares the second power line or the second ground line corresponding to the second bit line and the first memory macro for each column. The connecting cell electrically separates the first bit line and the second bit line, and electrically connects the first power line or the first ground line and the corresponding second power line or the second ground line. Connect.

  As a result, the bit lines are separated between adjacent memory mats to enable independent memory operation, and the power supply line and / or ground line can be connected between adjacent memory mats to stabilize the power supply voltage. it can.

[5] <Continuity of layout pattern>
In item 4, the semiconductor device is configured as follows. In the connection cell, all layout layers other than the wiring corresponding to the first bit line or the second bit line have the same layout as the memory cell or a symmetrical layout with a cell boundary line as an axis.

  As a result, the continuity and periodicity of the pattern are maintained in all layout layers other than the layers that need to be electrically separated.

[6] <Adjacent of 4 mats by connecting cells>
In item 1, the semiconductor device is configured as follows. A third memory macro (20_3) including a third memory mat (21_3) in which memory cells having the same layout as the memory cells are arranged in the L rows is further provided. The connection cell is defined as a first connection cell (11_1_1 to 11_1_M).

  One side of the L row sides of the first memory mat and one side of the L row side of the third memory mat have a second connection having the same layout size as the memory cells. The L rows × 1 columns (11_2_1 to 11_2_L) of the cells are disposed in contact with both the one side of the first memory mat and the one side of the third memory mat.

  In the second connection cell, the well layer, the impurity diffusion layer, and the gate wiring layer have the same layout as the memory cell or a symmetrical layout about the cell boundary line.

  As a result, dummy cells and spacing between memory mats can be eliminated in both two-dimensional directions, and the chip area can be further reduced.

[7] <Separation of word line and bit line in connection cell>
In item 6, the semiconductor device is configured as follows. The first memory macro shares a first word line for each column, the second memory macro shares a second word line for each column, and the first connection cell is connected to the first word line and the first word line. Two word lines are electrically separated. The first memory macro shares a first bit line for each row, and the third memory macro shares a third bit line for each row. In the second connection cell, the first bit line and the third bit line are electrically separated.

  Thereby, each of the word line and the bit line can be separated, and independent memory operations can be performed between adjacent memory mats.

[8] <Continuity of layout pattern>
In item 7, the semiconductor device is configured as follows. In the first connection cell, all layout layers other than the wiring corresponding to the first word line or the second word line have the same layout as the memory cell or a symmetrical layout with a cell boundary line as an axis. In the second connection cell, all layout layers other than the wiring corresponding to the first bit line or the third bit line have the same layout as the memory cell or a symmetrical layout with a cell boundary line as an axis.

  As a result, the continuity and periodicity of the pattern are maintained in all layout layers other than the layers that need to be electrically separated.

[9] <Design equipment>
A cell library (40) including a plurality of cells is provided, and a netlist (42) including a plurality of memory macros is input, and a plurality of cells are selected from the cell library and arranged and wired (57). A design apparatus that outputs layout information (44) corresponding to a netlist, and is configured as follows.

  The cell library includes a memory cell, a first connection cell (12), and a second connection cell (13). The memory cells are two-dimensionally arranged adjacent to each other so that the word lines of the memory cells adjacent in the first direction are connected to each other, and the memory cells adjacent in the second direction orthogonal to the first direction are connected to each other. Layout information for connecting the bit lines to each other. The first connection cell has layout information for electrically separating a word line between adjacent memory cells on both sides in the first direction. The second connection cell has layout information for electrically separating bit lines between memory cells adjacent on both sides in the second direction.

  The input netlist includes information defining the number of words and the number of bits for each memory macro of the plurality of memory macros.

  The design apparatus extracts a memory macro group having the same number of words and / or a memory macro group having the same number of bits from the plurality of memory macros (step 52).

  Depending on whether the number of words is the same, the number of bits is the same, or the number of words and the number of bits is the same, one or both of the following processing steps are performed.

  Two memory macros (20_1 and 20_2) included in the memory macro group having the same number of words are arranged adjacent to each other in the second direction with the same number of first connected cells as the number of words (11_1_1). ˜11_1_M), the two memory macros having the same number of words are adjacently arranged on both sides adjacent to each other in the first direction. Two memory macros (20_1 and 20_3) included in the memory macro group with the same number of bits are arranged adjacent to each other in the first direction (11_2_1). ˜11_2_L), the two memory macros having the same number of bits are adjacently arranged on both sides adjacent to each other in the second direction.

  As a result, it is possible to provide a design device for designing a semiconductor integrated circuit device with reduced chip area by eliminating dummy cells and spacing between memory mats.

[10] <Continuity of layout pattern>
In item 9, the design apparatus is configured as follows. The first connection cell has the same layout layer as the memory cell except for the wiring corresponding to the word line of the memory cell, and the second connection cell has the wiring corresponding to the bit line of the memory cell. All the layout layers are the same as the memory cell.

  As a result, the continuity and periodicity of the pattern are maintained in all layout layers other than the layers that need to be electrically separated.

2. Details of Embodiments Embodiments will be further described in detail.

Embodiment 1
FIG. 1 is an explanatory diagram illustrating a layout layout of memory macros according to the first embodiment. A schematic representation of a layout in which a first memory macro 20_1 of L rows × M columns and a second memory macro 20_2 of N rows × M columns are arranged adjacent to each other via connecting cells 11_1 to 11_M is schematically shown. (L, M, and N are each a positive integer).

  The first memory macro 20_1 includes a memory mat 21_1 in which memory cells MC are two-dimensionally arranged in L rows × M columns, and a peripheral circuit 22_1. The peripheral circuit 22_1 receives a signal including an address line 25_1 and a data line 26_1 from the outside or is output to the outside. An address decoder, a word line driver, a data input / output circuit, a bit line driver, a sense amplifier (not shown) , Including a control circuit and the like. In the memory mat 21_1, for example, memory cells with the same address are arranged in the row direction and connected to the same word line, and memory cells at the same bit position are arranged in the column direction and connected to the same bit line. In an SRAM, a word line is formed by a single wiring layer, and a bit line is formed by a pair of two complementary signal lines of the same wiring layer, which are laid out orthogonal to each other. It is common. According to this example, the word lines are laid out in the row direction (left and right in the drawing), and are driven by a word line driver disposed in the peripheral circuit 22_1 on the extension. The bit lines are laid out in the column direction (up and down in the drawing), driven by a bit line driver disposed in the peripheral circuit 22_1 on the extension, and connected to a sense amplifier.

  In the first memory macro 20_1, dummy cells 15 are arranged adjacent to each other around the memory mat 21_1. However, as will be described later, a connecting cell 11 is arranged in place of the dummy cell 15 in a portion adjacent to the second memory macro 20_2. The dummy cell 15 has substantially the same layout structure as the memory cell, and maintains the periodicity and continuity of the layout pattern of the memory mat. A transistor similar to the memory cell is included, but a termination process on the circuit is performed so as not to adversely affect the memory macro. For this reason, the layout structure is not exactly the same as that of the memory cell. The layout of the dummy cell 15 is designed so that no violation of the layout rule will occur if a predetermined spacing is ensured no matter what layout structure element is arranged on the side not connected to the memory cell MC. ing. Also in the first memory macro 20_1, a predetermined spacing is provided between the peripheral circuit 22_1 and the dummy cells arranged around the memory mat 21_1.

  The second memory macro 20_2 is also configured in the same manner as the first memory macro 20_1 except for the difference in size in the row direction. For example, in a design apparatus such as a system LSI, a plurality of memory macros (in many cases, all SRAM macros mounted on the same LSI) refer to the same cell library, and the same memory cell, the same dummy cell, and a peripheral circuit It is configured using the same unit cell for configuring. The peripheral circuit 22_2 is externally input with a signal independent of the signal input to the first memory macro 20_1, including the address line 25_2 and the data line 26_2, and the second memory macro 20_2 includes the first memory macro 20_2. It is optional to operate asynchronously independently of the memory macro 20_1, or to operate in synchronization with the first memory macro 20_1.

  In the second memory macro 20_2 as well, dummy cells 15 are arranged adjacent to each other around the memory mat 21_2. However, a connecting cell 11 is arranged in place of the dummy cell 15 in a portion adjacent to the first memory macro 20_1. In the example in which the word lines are laid out in the row direction (left and right direction in the drawing), the connection cell 11 separates the word line of the first memory macro 20_1 from the word line of the second memory macro 20_2. . Thus, the first memory macro 20_1 and the second memory macro 20_2 can be operated independently. The connection cell 11 can have the same layout as that of the memory cell except that the connection cell 11 has a layout structure different from that of the memory cell MC in order to divide the word line. Thereby, the periodicity and continuity of the layout pattern can be maintained in the memory mats 21_1 and 21_2. At this time, if there is a power supply line or ground line laid out in the same row direction as the word line, it is not necessary to divide it. Thereby, the impedance of the power supply wiring can be kept low, and the power supply voltage fluctuation can be suppressed.

  In the above example, it is assumed that the word lines are laid out in the row direction (left and right direction in the drawing). However, when the bit lines are laid out in the row direction, the connection cell 11 divides the bit lines. A layout structure may be used.

  As described above, dummy cells and spacing between memory mats can be eliminated, and the chip area can be reduced.

[Embodiment 2]
FIG. 2 is an explanatory diagram illustrating a layout layout of memory macros according to the second embodiment. In addition to the first and second memory macros 20_1 and 20_2 shown in FIG. 1, a third memory macro 20_3 of L rows × K columns, and a fourth memory macro 20_4 of N rows × K columns, Is a schematic representation of a layout that is two-dimensionally adjacent via the connecting cell 11 (L, M, N, and K are positive integers, respectively). Memory macros having the same column size are arranged adjacent to each other in the row direction, and memory macros having the same row size are arranged adjacent to each other in the column direction.

  The third and fourth memory macros 20_3 and 20_4 are configured in the same manner as the first and second memory macros 20_1 and 20_2 except for the difference in size.

  In the following description of the second embodiment, it is assumed that the word lines are laid out in the row direction (left and right direction on the drawing) and the bit lines are laid out in the column direction (up and down direction on the drawing), but this is only an example.

  In the portion where the first memory macro 20_1 and the second memory macro 20_2 are adjacent to each other, the connecting cells 11_1_1 to 11_1_M are arranged instead of the dummy cells 15, and the third memory macro 20_3 and the fourth memory macro 20_4 are arranged. In adjacent portions, connecting cells 11_3_1 to 11_3_K are arranged instead of the dummy cells 15. The connection cells 11_1_1 to 11_1_M divide the word line of the first memory macro 20_1 from the word line of the second memory macro 20_2, and the connection cells 11_3_1 to 11_3_K include the word line of the third memory macro 20_3 and the fourth line. The memory macro 20_4 is disconnected from the word line.

  In the portion where the first memory macro 20_1 and the third memory macro 20_3 are adjacent to each other, the connecting cells 11_2_1 to 11_2_L are arranged instead of the dummy cells 15, and the second memory macro 20_2 and the fourth memory macro 20_4 are arranged. In adjacent portions, connecting cells 11_4_1 to 11_4_N are arranged instead of the dummy cells 15. The connection cells 11_2_1 to 11_2_L divide the bit line of the first memory macro 20_1 and the bit line of the third memory macro 20_3, and the connection cells 11_4_1 to 11_4_N are connected to the bit line of the second memory macro 20_2 and the fourth line. The memory macro 20_4 is disconnected from the bit line.

  Accordingly, the first, second, third, and fourth memory macros 20_1, 20_2, 20_3, and 20_4 can be operated independently. All of the four memory macros are operated in synchronism with the same clock, for example, they can be operated in parallel, or all or part of them can be operated asynchronously. For the connection cell 11, it is preferable to prepare and use at least two types of the connection cell 12 for dividing the word line and the connection cell 13 for dividing the bit line. These connecting cells can have the same layout as that of the memory cells except that they have a layout structure different from that of the memory cells MC in order to divide the word lines or bit lines. Thereby, the periodicity and continuity of the layout patterns of the memory mats 21_1, 21_2, 21_3, and 21_4 can be maintained. At this time, the power supply line and the ground line need not be divided. Thereby, the impedance of the power supply wiring can be kept low, and the power supply voltage fluctuation can be suppressed.

  As a result, dummy cells and spacing between memory mats can be eliminated in both two-dimensional directions, and the chip area can be further reduced.

  FIG. 8 is an explanatory diagram showing the layout of the entire semiconductor chip including the memory macro in the second embodiment. (A) is a schematic diagram showing a layout of a semiconductor chip, which is designed by laying out four memory macros 20_1 to 20_4 by a conventional method in a logic circuit region 31 of standard cells. Each of the memory macros 20_1 to 20_4 includes memory mats 21_1 to 21_4 and peripheral circuits 22_1 to 22_4, and dummy cells 15_1 to 15_4 are arranged around the memory mats 21_1 to 21_4. (B) is an enlarged view of the vicinity of the region X, which is a part of (a). A spacing 39 is provided between the dummy cell 15 and the peripheral circuit 22_4, and between the dummy cell 15 and the logic circuit region 31. Although not shown in (b), the same spacing is provided between the peripheral circuits 22_1 to 22_4 of the memory and the logic circuit region 31. (C) is a schematic diagram showing a layout of a semiconductor chip, in which four memory macros 20_1 to 20_4 are laid out and designed by the method of this embodiment in a logic circuit region 31 of standard cells. The memory mats 21 </ b> _ <b> 1 to 21 </ b> _ <b> 4 are arranged adjacent to each other via the connecting cell 11, and the dummy cell 15 is arranged on the side where the connecting cell 11 is not present. Peripheral circuits 22_1 to 22_4 are arranged outside the memory mats 21_1 to 21_4. The peripheral circuits 22_1 to 22_4 are arranged upside down or left and right as appropriate as the memory mats 21_1 to 21_4 are adjacent to each other. In the chip layout by the conventional method shown in (a), the horizontal length of the chip includes five spacings and four dummy cells at a portion crossing the memory macro, and the vertical length is also five locations. Spacing and 4 dummy cells. On the other hand, in the chip layout according to the method of the present embodiment shown in (b), in the portion crossing the memory macro, the spacing in the horizontal direction of the chip is four places, two dummy cells, and one connection cell. The vertical length also includes four spacings, two dummy cells, and one connecting cell. It is preferable that the dummy cell 15 and the connecting cell 11 have the same size as the memory cell 10. In this example, the layout of the present embodiment is adopted, so that the height of the memory cell is one space in the vertical direction. The length of one place is shortened, and the width of one memory cell and the length of one spacing are shortened in the horizontal direction.

  In this example, the four memory macros 20_1 to 20_4 are described as two-dimensionally adjacent to each other. However, the layout of this embodiment is adopted as the number of similar memory macro combinations existing in the chip increases. The effect of reducing the chip area due to is increased.

[Embodiment 3]
3 to 6 are layout diagrams showing in detail a design example of a connection cell. A memory cell 10 and three types of connecting cells 12, 13, 14 are shown. FIG. 7 is an equivalent circuit diagram of memory cells and connection cells.

  3 shows the impurity diffusion layer (L), the gate wiring layer (FG), the contact layer (CONT), and the first metal wiring layer (M1), and FIG. 4 shows the contact layer (CONT) and the first metal. FIG. 5 shows the first via layer (V1) and the second metal wiring layer (M2), and FIG. 6 shows the second via layer (V2) and the third metal wiring layer (M3). .

  3 to 7 are design examples when the memory cell 10 is a 6-transistor CMOS-SRAM memory cell. Next to the memory cell 10, a connection cell 12 having a disconnected word line is disposed adjacent to the memory cell 10, and a connection cell 13 having a bit line disconnected is disposed adjacent to the memory cell 10.

In the memory cell 10, the bit lines 61 that are complementary to each other are wired in the vertical direction in the second wiring layer M 2, and the power supply (V _DD ) wiring 66 is vertically arranged in the second wiring layer M 2 at a position sandwiched between them. Wired. These are wired vertically from the upper end to the lower end of the memory cell 10, and when the same memory cell is arranged adjacent to each other vertically, they are connected to each other and become conductive, thereby wiring from the upper end to the lower end of the memory mat. Form. Further, the word lines 64 are wired in the horizontal direction in the third wiring layer M3, and ground (V _SS ) wirings 67 are wired in the horizontal direction in the same third wiring layer M3 on both sides thereof. These are wired horizontally from the left end to the right end of the memory cell 10, and when the same memory cell is arranged adjacent to the left and right, they are connected to each other and become conductive, thereby wiring from the left end to the right end of the memory mat. Form. As often adopted in general SRAM, the two memory cells 10 arranged adjacent to each other in the vertical direction have a layout pattern that is inverted up and down around the memory boundary, and are arranged adjacent to the left and right. The two memory cells 10 have a layout pattern that is reversed left and right around the memory boundary. However, it is important that the word lines, the bit lines, the power supply lines, and the ground lines are connected without deviation when they are arranged adjacent to each other, and it is not always necessary to invert them vertically and horizontally.

  The connecting cell 12 arranged adjacent to the side of the memory cell 10 is adjacent to a memory cell constituting another memory mat at the other end (right end in the figure). Even memory cells of other memory mats have the same layout pattern as the memory cell 10. The connection cells 12 are arranged adjacent to each other in the downward direction.

  The word line 64 of the adjacent memory cell 10 is connected to the right side of the memory cell 10 via the second via V2, the second wiring layer M2, the first via V1, and the first wiring layer M1 on the boundary line with the connection cell 12. The access transistor is connected to the gate of the access transistor on the left side of the connection cell 12. The word line 64 is divided at the connection cell 12. Therefore, the gate of the right access transistor on the other side of the connection cell 12 is connected not to the word line 64 but to a word line of a memory cell belonging to another memory mat arranged adjacent to the right side. Here, since the two memory mats arranged adjacent to each other on both sides of the connecting cell 12 are separated from each other, the operation of selecting independent words at independent timing can be performed.

As shown in FIG. 7, the connection cell 12 basically has the same circuit configuration as that of the memory cell 10, but the left and right access transistors are connected to the word lines of different memory mats. Does not work. In order not to cause malfunction or useless current consumption, the dummy bit lines 62 and 63 of the connection cell 12 are fixed to the power source (V _DD ) and the ground (V _SS ), respectively, at the lower end of the memory mat or in the connected peripheral circuit. Similarly, both ends of the storage element by the internal cross-coupled inverter are fixed to the power supply (V _DD ) and the ground (V _SS ), respectively.

  The connection cell 12 includes a third wiring layer M3 that divides the word line 64 and a first wiring layer M1 that forms wiring for fixing the above-described potential. The connection cell 12 has a layout pattern different from that of the memory cell 10. The wiring layer has the same layout pattern as the memory cell 10 or a symmetrical layout pattern reversed left and right at the cell boundary. Thereby, the continuity and periodicity of the pattern are maintained in all layout layers other than the third wiring layer M3 that needs to be electrically separated and the first wiring layer M1 that forms a fixed potential.

Unlike FIG. 7, it is also possible to use a connection cell in which the potential of the storage node of the storage element by the cross-coupled inverter is not fixed internally. At this time, the value held in the storage element cannot be predicted, but since it is fixed at the high level or the low level, useless power is not consumed. The word line 64 is selected and activated, and is electrically connected to the dummy bit line 62 via the access transistor, so that the dummy bit line 62 is fixed to the power supply (V _DD ). High is written, and the high level is held thereafter. Even if the reverse word line is selected and activated, the dummy bit line 63 is fixed at the ground (V _SS ), so that the value written to the complementary side (inversion side) of the storage element is low. Therefore, there is no data conflict.

  Thereby, the first wiring layer M1 can also have the same layout pattern as the memory cell 10, and the continuity and periodicity of the pattern in all layout layers other than the third wiring layer M3 that needs to be electrically separated. Is maintained.

  The connecting cell 13 arranged adjacently on the memory cell 10 is adjacent to a memory cell constituting another memory mat at the other end (upper end in the figure). Even memory cells of other memory mats have the same layout pattern as the memory cell 10. The connection cells 13 are arranged adjacent to each other in the left direction.

  The complementary bit lines 61 of the adjacent memory cells 10 are connected to the left and right access transistors of the memory cell 10 and the left and right access transistors 13 via the first via V1 and the first wiring layer M1 on the boundary line with the connection cell 13. Connected to the gate of the access transistor. The complementary bit line 61 is divided at the connection cell 13. For this reason, the gate of the access transistor on the other side of the connection cell 13 is connected not to the complementary bit line 61 but to the complementary bit line of a memory cell belonging to another memory mat arranged adjacent to the upper side. Here, since the two memory mats arranged adjacently above and below the connecting cell 13 have the bit lines separated, independent data input / output operations can be performed at independent timings.

As shown in FIG. 7, the connection cell 13 basically has the same circuit configuration as that of the memory cell 10, but does not function as a memory because the word line is fixed to the ground (V _SS ) potential.

  The connection cell 13 includes a second wiring layer M2 that divides the bit line 61 and a first wiring layer M1 that forms a wiring for fixing the potential, and has a layout pattern different from that of the memory cell 10. The wiring layer has a symmetrical layout pattern that is the same as that of the memory cell 10 or is inverted up and down at the cell boundary. Thereby, the continuity and periodicity of the pattern are maintained in all the layout layers other than the second wiring layer M2 that needs to be electrically separated and the first wiring layer M1 that forms the fixed potential.

Unlike FIG. 7, it is also possible to use a connection cell in which the potential of the storage node of the storage element by the cross-coupled inverter is not fixed internally. At this time, the value held in the storage element cannot be predicted, but since it is fixed at the high level or the low level, useless power is not consumed. Since the dummy word line 65 is fixed to the ground (V _SS ) potential, it is not activated. Thereby, the first wiring layer M1 can also have the same layout pattern as the memory cell 10, and the continuity and periodicity of the pattern in all layout layers other than the second wiring layer M2 that needs to be electrically separated. Is maintained.

[Embodiment 4]
FIG. 9 is a flowchart showing the operation of the design apparatus of this embodiment.

  When a netlist described in behavioral level, RTL (Register Transfer Level), etc. is input (step 41), gate level nets including memory macros and other macrocells using logic synthesis, RAM compiler, RTL wrapper, etc. A list is generated (step 51). The logic circuit portion of the net list described in the behavior level, RTL, etc., synthesizes a functionally equivalent gate level net list using standard cells by referring to the library 40 by logic synthesis. The RAM macro is replaced with a memory macro that is synthesized by referring to the library 40.

  Next, a group of memory macros having the same number of words and bits is extracted (step 52), and a combination of memory macros to be arranged adjacent to each other is selected (step 53). Here, it is more preferable to evaluate the influence on the chip area and determine the priority. For example, it is possible to reduce the chip area by arranging four memory macros adjacently as shown in the second embodiment rather than arranging two memory macros adjacently as shown in the first embodiment. . For each combination of memory macros to be placed adjacent to each other, either the first connected cell or the second connected cell is selected according to the adjacent direction (step 54), and the layout data is synthesized (step 55). The combined memory macro layout data is generated (step 43).

  Thereafter, the layout plan of the entire chip including layout data of the combined memory macro (step 56), the placement and wiring of standard cells are performed (step 57), and the layout data is verified (step 58). The layout data is output (step 44).

  The RTL wrapper has a size that can be synthesized by the RAM compiler when the memory included in the netlist described in the behavior level, RTL, etc. is large and exceeds the size that can be synthesized by the RAM compiler. It is used when configuring a circuit description that is logically equivalent to the memory, including a memory macro. FIG. 10 is a schematic diagram for explaining memory division by the RTL wrapper. The case where the size of the memory included in the netlist described at the behavior level is 56 bits × 30K words, and the size of the memory macro that can be synthesized by the RAM compiler is a maximum of 16 bits 4K words. Take and explain. 56 bits are divided into 16 bits × 3 + 8 bits, and 30K words are divided into 4K words × 7 + 2K words. The memory described in 56 bits × 30K words at the behavioral level includes 21 16-bit 4K-word memory macros (71), 7 8-bit 4K-word memory macros (72), and 16-bit 2K-word memory macros (73 3) and one 8-bit 2K word memory macro (74). The RTL wrapper includes these multiple memory macros and is logically equivalent to a 56-bit × 30-k word memory with input / output terminals for signals such as clock, address, data input, data output, chip enable, and write enable. Described as a circuit. The circuit description of the memory includes a connection between a control circuit and a memory macro for operating a plurality of memory macros as a 56-bit × 30k word memory as a whole. The control circuit may be described in behavior or RTL and generate a gate logic circuit through normal logic synthesis.

  Here, the RTL wrapper is often a memory description including a large number of memory macros having the same number of bits and the same number of words, and the first embodiment or the second embodiment described above can be applied efficiently. Returning to the example of FIG. 10, it is first considered to combine four memory macros as in the second embodiment. In the configuration A, the memory macro (71) of 16 bits and 4K words is composed of six in the word line direction and two in the bit line direction. Therefore, the combination of four memory macros as in the second embodiment 3 can be made. The portion of the configuration B is configured by six rows of 16-bit 4K-word memory macros (71) and 8-bit 4K-word memory macros (72) arranged in the word line direction. A combination as in the second embodiment can be made with two 16-bit 4K word memory macros (71) and two 8-bit 4K word memory macros (72). The portion of configuration C is configured by a 16-bit 4K word memory macro (71) and a 16-bit 2K word memory macro (73) arranged in two columns in the bit line direction. With these four memory macros, a combination as in the second embodiment can be made. The part of configuration C consists of a 16-bit 4K word memory macro (71), an 8-bit 4K word memory macro (72), a 16-bit 2K word memory macro (73), and an 8-bit 2K word memory macro (74). The four memory macros can make a combination as in the second embodiment.

  In this example, all the four memory macro combinations as in the second embodiment can be combined, but two memory macro combinations as in the first embodiment may be mixed. In addition, for the total of six 16-bit 4K word memory macros (71) included in configuration B and two 16-bit 4K word memory macros (71) included in configuration C in this description, Including the configuration A, the four combinations as in the second embodiment may be further increased by two. At this time, the six 8-bit 4K word memory macros (72) remaining in the configuration B are combined in the same manner as in the second embodiment, and the remaining two are combined in the configuration B as in the first embodiment. The remaining two 16-bit 2K word memory macros (73) may be combined as in the first embodiment. Furthermore, the combination of memory macros as in the first or second embodiment does not need to be configured within the range of a group of memory macros collected by the RTL wrapper. However, a group of memory macros compiled with RTL wrappers often have common signal lines such as clocks and addresses, so giving priority to this range complicates control circuit layout and control signal wiring. It does not increase the chip area.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the above embodiment, the memory macro provided with the peripheral circuits on the left and bottom two sides has been described. However, if there is a side where the memory mats can be adjacent to each other, it can be generally applied to that side. Therefore, if the memory macro has peripheral circuits on the upper and lower sides, any number of memory macros that are connected in the left-right direction can be arranged adjacent to each other, and the peripheral circuit is provided on the inner side and the entire periphery is a memory mat. If so, any number of the four sides can be connected and arranged adjacent to each other.

  In the above embodiments, the description has been mainly made on the assumption that the SRAM is used. However, the present invention can be similarly applied to any kind of memory. It may be a non-volatile memory such as a mask ROM, or an electrically rewritable non-volatile memory such as a phase change memory or a ferroelectric memory.

10 memory cells 11 connecting cells 12 connecting cells (disconnection of word lines)
13 Connection cell (bit line disconnection)
14 Connecting cell (corner)
15 Dummy cell 16 Dummy cell (word line termination)
17 Dummy cell (bit line termination)
18 Dummy cell (corner)
20 Memory Macro 21 Memory Mat 22 Peripheral Circuit 23 Word Line Driver 24 Bit Line Driver + Sense Amplifier 25 Address Line 26 Data Line 30 LSI (Large Scale Integrated Circuit)
31 Standard cell area 39 Spacing 40 Cell library 41 Netlist (behavior level or RTL level)
42 Netlist (gate level + memory macro + others)
43 Combined memory macro layout data 44 Whole chip layout data 51 Logic synthesis, RTL wrapper, RAM compiler
52 Extract a group of memory macros having the same number of words or bits 53 Select a combination of memory macros to be placed adjacent to each other 54 Select first connected cell or second connected cell according to the adjacent direction 55 Composition of layout data 56 Chip Floor Plan 57 Placement / Wiring 58 Verification 61 Complementary Bit Line 62, 63 Dummy Bit Line 64 Word Line 65 Dummy Word Line 71-74 Memory Macro

Claims (10)

A first memory macro including a first memory mat in which memory cells are arranged in L rows × M columns (where L and M are positive integers); an address line and a data line different from the first memory macro; And a memory cell having the same layout as the memory cell includes N rows (where N is a positive integer) × second memory macro including a second memory mat arranged in the M columns,
One side of the M columns of the first memory mat and one side of the M columns of the second memory mat are connected cells having the same layout size as the memory cells. 1 row × M columns are arranged in contact with both the one side of the first memory mat and the one side of the second memory mat,
The connecting cell is a semiconductor device in which a well layer, an impurity diffusion layer, and a gate wiring layer have the same layout as the memory cell or a symmetrical layout about a cell boundary line.   2. The memory cell according to claim 1, wherein a plurality of memory cells included in each column of the first memory macro share a first word line and a first power supply line or a first ground line, respectively, and each column of the second memory macro. A plurality of memory cells included in each share a second power line or a second ground line corresponding to the second word line and the first memory macro, and the connection cell includes the first word line and the second word line. And electrically connecting the first power supply wiring or the first grounding line and the corresponding second power supply wiring or the second grounding line.   3. The connection cell according to claim 2, wherein all layout layers other than the wiring corresponding to the first word line or the second word line have the same layout as the memory cell or a symmetrical layout with a cell boundary line as an axis. , Semiconductor devices.   2. The first memory macro according to claim 1, wherein the first memory macro shares a first bit line and a first power supply wiring or a first ground line for each column, and the second memory macro and the second bit line for each column. A second power supply line or a second ground line corresponding to the first memory macro is respectively shared, and the connection cell electrically separates the first bit line and the second bit line, and the first power supply line or the A semiconductor device that electrically connects a first ground line and the second power supply wiring or the second ground line corresponding to the first ground line.   5. The connection cell according to claim 4, wherein all layout layers other than the wiring corresponding to the first bit line or the second bit line have the same layout as the memory cell or a symmetrical layout with a cell boundary line as an axis. , Semiconductor devices. The memory cell according to claim 1, further comprising a third memory macro including a third memory mat in which memory cells having the same layout as the memory cells are arranged in the L rows, wherein the connection cell is a first connection cell,
One side of the L row sides of the first memory mat and one side of the L row side of the third memory mat have a second connection having the same layout size as the memory cells. Placing the L rows × 1 column of cells in contact with both the one side of the first memory mat and the one side of the third memory mat;
The second connection cell is a semiconductor device in which a well layer, an impurity diffusion layer, and a gate wiring layer have the same layout as the memory cell or a symmetrical layout with a cell boundary line as an axis. 7. The first memory macro according to claim 6, wherein the first memory macro shares a first word line for each column, the second memory macro shares a second word line for each column, and the first connection cell is the first connection cell. A word line and the second word line are electrically separated;
The first memory macro shares a first bit line for each row, the third memory macro shares a third bit line for each row, and the second connection cell is connected to the first bit line and the first bit line. A semiconductor device in which three bit lines are electrically separated.   8. The layout according to claim 7, wherein all the layout layers other than the wiring corresponding to the first word line or the second word line are the same as the memory cell or symmetrical about the cell boundary line. In the second connection cell, all layout layers other than the wiring corresponding to the first bit line or the third bit line have the same layout as the memory cell or a symmetrical layout with the cell boundary line as an axis. , Semiconductor devices. A cell library including a plurality of cells is provided, and a netlist including a plurality of memory macros is input. By selecting and arranging a plurality of cells from the cell library, layout information corresponding to the netlist is output. A design device,
The cell library includes a memory cell, a first connection cell, and a second connection cell,
The memory cells are two-dimensionally arranged adjacent to each other so that the word lines of the memory cells adjacent in the first direction are connected to each other, and the memory cells adjacent in the second direction orthogonal to the first direction are connected to each other. Layout information for connecting the bit lines to each other,
The first connection cell has layout information for electrically separating word lines between adjacent memory cells on both sides in the first direction;
The second connection cell has layout information for electrically separating bit lines between adjacent memory cells on both sides in the second direction,
The input netlist includes information defining the number of words and the number of bits for each memory macro of the plurality of memory macros,
The design apparatus extracts a memory macro group having the same number of words and / or a memory macro group having the same number of bits from the plurality of memory macros;
Two memory macros included in the same number of memory macro groups having the same number of words are arranged adjacent to each other in the second direction by arranging the same number of the first connected cells in the second direction. The two memory macros having the same number of words are arranged adjacently on both sides, and / or two memory macros included in the memory macro group having the same number of bits are arranged in the same number as the number of bits. The design apparatus, wherein the second connection cells are arranged adjacent to each other in the first direction, and the two memory macros having the same number of bits are adjacently arranged on both sides adjacent to each other in the second direction.   10. The first connection cell according to claim 9, wherein all layout layers except the wiring corresponding to the word line of the memory cell are the same as the memory cell, and the second connection cell is a bit line of the memory cell. A design apparatus in which all the layout layers except the wiring corresponding to are identical to the memory cell.

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