JPH0377324A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase resistance to electromigration, to make wiring region small and to realize a high integration by a method wherein a semiconductor integrated circuit is provided with a plurality of metal wirings layers and a plurality of wiring lines and the metal wiring are piled up in parallel on the same wiring lines over a plurality of layers and connected to each other via through-holes. CONSTITUTION:Al metal wiring such as power-supply lines 7a, 8a, signal conductors 7b, 8b, grounding conductors 7c, 8c, and the like are piled up in parallel on the same wirings lines over two layers in a semiconductor integrated circuit substrate which is provided with a plurality of metal wiring layers and a plurality of wiring lines; they are connected to each other via through-holes 6. Widths of the Al wirings 7a, 7b, 7c, 8a, 8b, 8c are narrow as compared with those of conventional metal wirings. The widths of the metal wirings are not made wider but are composed of a plurality of layers. Thereby, an electric current is distributed and a current density is suppressed. Since the widths of the wirings are narrow, the area of the semiconductor integrated circuit becomes small, compared with that of conventional circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring layout pattern of a semiconductor integrated circuit.

[Conventional technology] A1, A1 and Si are used for wiring that connects to semiconductor integrated circuits.

Power loss is reduced by using a metal with a low resistance value, such as a Cu alloy or W. FIG. 7 is a partial plan view of a conventional conductor & product circuit (inverter circuit). In the figure, (1) is a metal wiring, (la) is a power supply line, (1b) is a Nobuo line, and (1, c) is a grounding line. (
2) is the P diffusion region, (3) is the n4 diffusion region, (0 is polysilicon, and (5) is the diffusion region (2).

(3) and metal wiring (+, a), (lb), He
) is the w-tact hole (5) that connects.

Next, the operation will be explained. The metals used for metal wiring (+,), such as aluminum and AI alloys, have a lower melting point than the silicon compounds that make up logic gates, and are
Under a current density of Cm2, a phenomenon called electromigration such as disconnection or movement occurs.

In the conventional metal wiring (1), as a reinforcement measure against migration, a sufficient wiring width is provided so that the metal wiring (1) can withstand a large current density. Especially the power line (
1a) Among the grounding line (1C) and signal line (1b), the signal line with a large load capacity such as a clock line is provided with a wide line width so that the current density is less than 1O6/112. Ta.

[Problems to be Solved by the Invention] Since the metal wiring of conventional semiconductor integrated circuits has been configured as described above, it is possible to improve the layout pattern (mask pattern) of semiconductor integrated circuits by providing a sufficient width to withstand migration. ) became large.

The present invention was made to solve the above-mentioned problems, and aims to be strong against electromigration, reduce the wiring area, and achieve high integration as a result.

[: Means for solving Jifl] The semiconductor integrated circuit according to the present invention has a plurality of metal wiring layers and a plurality of wiring lines, and the metal wiring is overlapped in parallel on the same wiring line across multiple layers, and through holes are They are connected to each other through.

[Function] Since the metal wiring in the present invention is layered in parallel on the same wiring line over multiple layers and connected to each other via through holes, current can be distributed and the wiring width can be narrowed while strengthening electromigration. As a result, the width of the metal wiring can be narrowed, and as a result, high integration of the C semiconductor integrated circuit can be achieved.

[Embodiment] Hereinafter, an embodiment of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings. FIG. 1 is a plan view of an inverter circuit of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a perspective view of the vicinity of the ground line II--II in FIG. 1. Note that the reference numerals (2) to (5) in the figure are the same as those of the above-mentioned conventional device, and the explanation thereof will be omitted.

4, (7a) is the first
Layer power supply line, (8a) is the second layer power supply line, (7b) is the first layer signal line, (8b) is the second layer signal line, (7C) is the first layer ground line, (8c) is the second layer The ground wire (6) is a through hole. In addition, although FIGS. 1 and 2 show examples of metal wiring using AI, there are also other metal interconnections other than AI salt, such as AI and Si, AI and 54
Metal wiring using an alloy of 1 and Cu, 8L and Cu, etc. may also be used.

Unlike the conventional one, in FIGS. 1 and 2, power lines (7a), (8a), signal lines (7b), (8b)
, ground wires (7c), (8c), etc. are superimposed in parallel on the same wiring line across two layers in a semiconductor integrated circuit board having multiple metal wiring layers and multiple wiring lines, and through holes (6 ) are connected to each other through. Also, ^l metal wiring (7a), (7b),
(7c), (8a).

The width of (8b) and (8c) is the conventional metal wiring (la)
, (lb) is narrower than (1,c). Also,
Although one through hole (6) is used in FIGS. 1 and 2, two or more may be used. Considering that the A1 metal wiring path branches, it is effective to provide the through holes (6) at intervals of 1 the width of the metal wiring. An example of this is shown in Figure 3.

Next, the operation of the semiconductor integrated circuit will be explained.

In the conventional wiring method, the metal wiring width was widened in order to suppress the TLtL density to 106^/cm2 or less. Therefore, in a semiconductor integrated circuit, the proportion of the area occupied by the metal wiring width increases, and as a result, the area of the entire semiconductor integrated circuit increases.

In this embodiment, the current can be distributed and the constant current density can be suppressed by using multiple layers instead of increasing the width of the metal wiring.

In Figures 1 and 2, (7a)-(8a), (7
b)-(8b).

Although an example of two metal wiring layers such as (7c) to (8c) is shown, three or more layers may be used. Furthermore, because the wiring width is narrow, the area of the semiconductor integrated circuit becomes smaller by C compared to the conventional one. - to t71. ',,+In the example, all metal wiring is
Explain the case of C multiple loads, nj 'f■neawat+, f1 load capacity of power supply wire, grounding wire, click wire, etc.
When applied to the line, the effect is similar to that of the above embodiment.

Next, another embodiment C will be explained. ″r-conductor collection 11
When designing the 11th circuit, the basic functions and
It is constructed in a hierarchical manner from 1-7-rules (cells).
) Yuru Selbee There is a rice design force formula. A cell is a semiconductor integrated circuit film.
I can think about it.゛r designed using the CellHale design method
, a plane view of the conductor integrated circuit is shown in FIG. This conductor integration [q] path now functions as an active element such as a transistor.
l+】lx Bat for external electrical connections (10)
and an extra-cell wiring area (11) including metal wiring for electrically connecting cells and between cells and pads.

As shown in the figure, the cells are generally rectangular in shape, but
A polygon (6 f (J, octagon) for 1 and 1 may also be used.

For design! 1', Cell required for conductor integrated circuit (9)
7-4-ru.

Any number of cells may be placed.

For example, the function of each cell is the same 2'a-], but the function of each cell may be different. After placing the cell (9), cell (9), cell (
9) and the bat (]0) are electrically connected 1- with the metal wiring (
wide area wiring) (+4) will be done. The wide area wiring (14) is connected to the wiring area within the cell (12) and the wiring area outside the cell (11).
), or at least part of the outside-cell wiring area (11) is wired with only one layer of interconnection (1).The reason is that the wiring (10 is automatically This is done using a wiring program, and at this time, P4
．． It is said that the second layer metal wiring is wired in the direction perpendicular to the first layer metal wire with respect to the first layer metal wire. This is because the layers are used separately in the case of τL.

Conventionally, wide-area wiring (14) that spans inside and outside the cell is
The area of the cell can be reduced by applying the metal wiring method shown in Figures 11 to 3 and making sure that the wiring width is the same both outside the cell and inside the cell. The r-conductor East Circuit II\i product is smaller than when using conventional metal wiring5, especially this fact8.
Figure 5 shows the wide-area wiring that has a one-layer rise near the boundary between the intra-cell interconnect area (12) and the outer-cell interconnect area (11) in six cases. The metal wirings (7) and (8) in the C cell are twisted in parallel on the same wiring path across the visual layer, and are connected in η-i by through holes (Fi), l″l. The wide-area wiring in the outside-cell wiring area (11) has the conventional wiring width, but inside the cell, the wiring axis is narrower. In the cell near the boundary between the inside and outside of the cell, C is formed in a shape to transition from the width of the wiring outside the cell (conventional wiring axis) to the width of the multilayer metal wiring inside the cell. Some other embodiments are shown in FIG. FIG. 6 also shows an example in which one or two through holes (6) are used; however, any number of through holes (6) may be provided.

1 Effects of the Invention] According to the present invention, it is possible to narrow the metal wiring width in a semiconductor integrated circuit, as shown in ! t'-
The area of conductor integrated circuits becomes smaller. Furthermore, if a multilayer interconnection method is applied within a cell, the area of the cell will become smaller, and as a result, the circuit will become thicker due to the introduction of more cells into the conductor integrated circuit. This leads to higher integration. In addition, the metal wiring is superimposed in parallel using the same wiring route, multiple layers, and connected by through holes, making the wiring resistant to electro-migration. Force yourself.

[Brief explanation of drawings]

FIG. 1 is a plan view of an inverter circuit with 101 circuits (7) of t-conductor integrated circuits according to the present invention, and FIG. 21 is a perspective view taken from line II-II in FIG. is +
, is a plan view showing an example of the spacing between through-holes in the multilayer metal interconnection according to the present invention, in which through-hole (6)
is set at the interval of the metal wiring width 6-) Color. ';)'i <
The diagram is designed by the cell accent meter tf formula! ：・Conductor integration ['j] road diagram showing another practical example of the present invention, Figure 5-1 shows the actual wiring of the current area inside and outside the cell according to the present invention. Enlarged explanatory drawings, FIGS. 6(a) to (h) are partial plan views showing other embodiments of metal wiring near the boundaries between inside and outside cells, and FIG. 7 is a plan view showing a conventional semiconductor integrated circuit. In the figure, (6) is a through hole, (7) is a first layer metal wiring when two layers of metal wiring are stacked, (8) is a second layer metal wiring, and (9) is a cell. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A semiconductor integrated circuit having a plurality of metal wiring layers and a plurality of wiring paths, characterized in that it includes multilayer metal wiring means overlapping the plurality of layers in parallel on the same wiring path and connecting to each other via through holes. Semiconductor integrated circuit. (2) A cell that includes an active element and occupies a cell area on the surface of the semiconductor, and a pad that makes an electrical connection with the outside of the semiconductor integrated circuit, and that is located outside the area occupied by the cells and pads, and that In a semiconductor integrated circuit equipped with an extra-cell wiring area including a metal wiring that electrically connects between a cell and a pad, the semiconductor integrated circuit has a wide-area wiring that spans the cell area and the extra-cell wiring area, and the wide-area wiring covers at least a portion of the cell area. In this case, wiring is performed using the multilayer metal wiring means, at least a portion of the outside cell wiring area is wired using only one layer of metal, and the width of the multilayer metal wiring means portion is narrower than the width of the first layer metal portion. A semiconductor integrated circuit according to claim 1, characterized in that: