JP3353410B2 - Gate array multilayer wiring structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure of a gate array, and more particularly to a multilayer wiring structure of a gate array in a semiconductor device.

[0002]

2. Description of the Related Art A gate array is one in which cells of the same standard are regularly arranged on a chip, and various functions can be realized by wiring each cell according to a logic circuit diagram.

In recent years, with an increase in the degree of integration and functions of semiconductor devices, multilayered element structures have been developed. Also in the above-mentioned gate array, by increasing the number of wirings, the use efficiency of the cells is increased to improve the degree of integration, and the wirings are shortened to improve the functionality.

For example, in a gate array in which three wiring layers are stacked on a substrate, a circuit is formed by the following wiring structure. First, a power supply line for supplying power to each circuit and a signal line for connecting each cell to form a circuit are arranged in a first wiring layer formed on the substrate via an insulating film. Have been. Then, a ground line for grounding each circuit and a signal line similar to the above are arranged in the second wiring layer laminated on the first wiring layer via an insulating film.

Further, in the third wiring layer laminated on the second wiring layer via an insulating film, a reinforcing power supply line and a signal line for reinforcing power supply are arranged. The reinforcing power supply line is, for example, a wiring for supplementing the supply of power to a circuit that consumes more power than the power supplied from the power supply line.

The power supply line, the ground line, and the reinforcing power supply line arranged in each of the wiring layers are arranged at predetermined intervals over the entire surface of each wiring layer. The signal lines arranged in the respective wiring layers are, for example, arranged in the first wiring layer in accordance with the circuit configuration. At the second wiring layer. The signal line arranged in the second wiring layer is arranged in accordance with the circuit configuration in the same manner as described above, and if the signal line intersects with the ground line and another signal line, the third wiring is arranged so as to straddle the intersection. Arranged in layers.

In the gate array, by forming the above-described multilayer wiring structure, a circuit is formed without short-circuiting between the wirings. Further, as shown in the graph of FIG. 2, by increasing the number of wiring layers from two to three, the cell use efficiency can be reduced from the 50% level to the 70% level.
It is raised on the table.

[0008]

However, the above-mentioned multilayer wiring structure of the gate array has the following problems.
That is, in the above-described multilayer wiring structure, the power supply line, the ground line, and the reinforcing power supply line are arranged over the entire surface of each wiring layer. Therefore, the arrangement of the signal lines forming the circuit in each wiring layer is regulated by these wirings. For this reason, as shown in the graph of FIG. 2, when the fourth wiring layer is stacked by further increasing the number of layers, the use efficiency of the cell is reduced, and the integration degree is improved by the number of layers. It has become difficult.

Therefore, the present invention provides a multilayer wiring structure of a gate array which solves the above-mentioned problems,
It is another object of the present invention to achieve higher functionality and higher integration of a semiconductor device.

[0010]

SUMMARY OF THE INVENTION The present invention for achieving the above object comprises a multilayer wiring layer laminated on a substrate, and is arranged on any one of the multilayer wiring layers. Power supply line to supplement the power supply with
In a multilayer wiring structure of a gate array having a circuit receiving power supply from the reinforcing power supply line as having a large power consumption , the circuit is arranged collectively in a part of the gate array, and the reinforcing power supply line is , Comb-type parallel connection only to the area corresponding to the circuit that is arranged collectively
It is characterized by being arranged. Further, the circuit is arranged at least near a power supply pad among a plurality of pads formed on the substrate.

[0011]

According to the above-mentioned gate array multilayer wiring structure, power consumption is reduced.
Circuits that receive large power and receive power from the reinforcing power lines are collectively arranged and correspond to the
By arranging the reinforcing power supply lines in parallel with each other only in the region where the reinforcing power supply lines are arranged, a signal line region in which only the signal lines are arranged is formed in the wiring layer in which the reinforcing power supply lines are arranged. Therefore, the degree of freedom in arranging signal lines is improved. Further, in the multilayer wiring structure of the gate array, by arranging the circuit near the power supply pad, a voltage drop of the reinforcing power supply line is prevented.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. The gate array according to the embodiment has, for example, a circuit that consumes a large amount of power and needs to supply power from two power supply lines, and a circuit that consumes a small amount of power compared to this circuit and supplies power from one power supply line And a circuit that only needs to be formed.

[0013] The gate array constituting the above-mentioned circuit has a substrate on which a plurality of pads including a power supply pad and a ground pad are formed around a plurality of cells arranged therein, and an insulating film formed on the substrate. And three wiring layers which are laminated by the following method. Each of the wiring layers is a first wiring layer, a second
A wiring layer and a third wiring layer are formed in this order.

In the case of arranging the wiring in each layer of the gate array, first, the circuits having large power consumption described above are set so as to be collectively arranged in the vicinity of the power supply pad of the gate array. In the state set as described above, the wiring of each wiring layer is arranged as follows.

First, in the first wiring layer, there are arranged a signal line for connecting each cell to form a circuit, and a power supply line connected to the power supply pad and supplying power to all the configured circuits. You. The power supply lines are arranged in parallel at predetermined intervals over the entire surface of the first wiring layer, and the signal lines are arranged according to a circuit configuration of a gate array. When the signal line crosses the power supply line or another signal line, the signal line is connected to the second wiring layer so as to straddle the crossing portion.

In the second wiring layer, a signal line connected from the first wiring layer and a ground line connected to the ground pad and grounding the circuit are arranged. The ground lines are arranged perpendicular to the first power supply line and at predetermined intervals over the entire surface of the second wiring layer. The signal line connected from the first wiring layer is arranged according to the circuit configuration of the gate array, and when this signal line intersects with the ground line or another signal line, the signal line is straddled over the intersection. It is connected to three wiring layers.

Further, in the third wiring layer, the third wiring layer shown in FIG.
As shown in the layout diagram of the wiring layer 10, a reinforcing power supply line 11 connected to the power supply pad 20 to reinforce the power supply to the above-described circuit with large power consumption, and a signal line 12 connected from the second wiring layer Is arranged. The reinforcing power supply line 11 is arranged in a reinforcing power supply line region 13 corresponding to a portion of the third wiring layer 10 where the circuits with large power consumption are concentrated.
Then, for example, the reinforcing power supply lines 11 are arranged in parallel with the power supply lines arranged in the first wiring layer. And
The signal line 12 connected from the signal line 14 of the second wiring layer is
They are arranged according to the circuit configuration of the gate array 1.

By arranging the wiring as described above, each circuit is configured in the gate array. Power is supplied from a power supply line in the first wiring layer and a reinforcing power supply line in the third wiring layer to a circuit with large power consumption, and power is supplied from the power supply line to a circuit with low power consumption. .

In the above-described multilayer wiring structure of the gate array, the circuits consuming a large amount of power are set so as to be collectively arranged near the power supply pads. Then, as shown in FIG. 1, a reinforcing power supply line region 13 was formed in the third wiring layer 10 corresponding to a portion where this circuit was integrated, and the reinforcing power supply line 11 was arranged only in this region. Therefore, a signal line region 15 in which only the signal lines 12 are arranged is formed in the third wiring layer 10, and the degree of freedom in arranging the signal lines 12 is improved. Further, since the reinforcing power supply line region 13 is formed near the power supply pad 20, the reinforcing power supply line 11 is shortened and the reinforcing power supply line 1 is reduced.
One voltage drop is prevented.

Further, in the above-described embodiment, a circuit having a large power consumption, which is supplied with power from the reinforcing power supply line and the power supply line, is set, and this circuit is integrated near the power supply pad. However, the present invention is not limited to this, and if there is a circuit that receives power supply only from the reinforcing power supply line, it is arranged near the power supply pad including this circuit.

In the above embodiment, the case where the reinforcing power supply line and the signal line are arranged in the third wiring layer has been described. However, when arranging a reinforcing power supply line, a signal line, and a ground line in the third wiring layer, a circuit having a large power consumption is set to be arranged near the power supply pad and the ground pad. A ground line is arranged together with the reinforcing power line in the reinforcing power line region formed in the three wiring layers. Thereby, the arrangement area of the ground line is also limited, and the degree of freedom in arranging the signal lines is improved.

[0022]

As described above, according to the multilayer wiring structure of the gate array of the present invention, the circuits for receiving the power supply from the reinforcing power supply lines are arranged collectively, whereby the wiring for arranging the reinforcing power supply lines is provided. In the layer, the arrangement area of the reinforcing power supply lines can be concentrated, so that the degree of freedom of the signal lines is improved. Therefore, in the semiconductor device, the use efficiency of the cell can be improved and the degree of integration can be increased, and the signal line can be shortened to improve the functionality. Further, by integrating the circuits in the vicinity of the power supply pad, a voltage drop of the reinforcing power supply line can be prevented, so that the reliability of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a layout diagram illustrating an embodiment.

FIG. 2 is a graph illustrating a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate array 10 3rd wiring layer (wiring layer) 11 Reinforcement power supply line 20 Power supply pad

Claims (4)

(57) [Claims] 1. A reinforcing power supply line comprising a multilayer wiring layer laminated on a substrate, arranged on any one of the multilayer wiring layers and supplementing power supply,
In a multilayer wiring structure of a gate array having a circuit receiving power supply from the reinforcing power supply line as having a large power consumption , the circuit is collectively arranged in a part of the gate array, and the reinforcing power supply line is A multi-layer wiring structure of a gate array, which is arranged so as to be connected in parallel in a comb shape only in a region corresponding to such a collectively arranged circuit. 2. The multilayer wiring structure of a gate array according to claim 1, wherein said circuit is arranged at least near a power supply pad among a plurality of pads formed on said substrate. 3. The multi-layered gate array according to claim 2 , wherein if there is a circuit that receives power supply only from said reinforcing power supply line, said circuit is disposed near a power supply pad. Wiring structure. 4. When placing the ground wire to the wiring layer,
2. The ground line is arranged together with the reinforcing power line in a region where the reinforcing power line is arranged.
3. The multilayer wiring structure of the gate array according to 1.