JPS62203351A - Interconnection structure of integrated circuit - Google Patents

Abstract

PURPOSE:To contrive reduction in the crosstalk between signal wirings by a method wherein a shield wire is provided in the second interconnection layer of a plurality of interconnection layer in parallel with the adjoining signal wiring in the first interconnection layer, and the shield wire is earthed. CONSTITUTION:Signal wirings 4 and 4' in the first interconnection layer 3 are formed adjoiningly on the upper surface of the dielectric film 2 located on a semiconductor substrate 1. A shield wiring 8 is formed in the second interconnection layer 6 formed through the intermediary of an insulating film 5 in parallel with the signal wirings 4 and 4', and it is earthed. As a result, the crosstalk between the signal wirings 4 and 4' can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring structure for an integrated circuit that reduces crosstalk occurring between adjacent signal wiring lines inside a semiconductor integrated circuit.

[Conventional technology]

As integrated circuits become faster and more dense with advances in LSI technology, crosstalk occurring between circuit interconnections can no longer be ignored as a factor in signal waveform deterioration. Conventionally, in order to reduce the crosstalk between the connection wirings, for example, the spacing between the signal wirings is increased, a shield wire is installed between the signal wirings, or a first wiring layer including the signal wirings, A second layer is formed on top of the second layer with an insulating layer interposed therebetween.
Crosstalk was reduced by forming a new shield layer between the wiring layers.

[Problem that the invention seeks to solve]

The wiring structure described above, which reduces crosstalk by increasing the spacing between signal wirings and (1) installing shielded wires between signal wirings, inevitably causes a decrease in circuit integration, which is a problem in achieving high density. Met. In addition, in a wiring structure in which crosstalk is reduced by newly forming a dual shield layer, in addition to forming an insulating layer, a shield layer is newly formed and a second insulating layer is formed in the manufacturing process of each wiring. There was a problem in that a step of forming was required, complicating the manufacturing process.

An object of the present invention is to eliminate the above-mentioned problems and reduce crosstalk between internal wirings of an integrated circuit.

[Means for solving problems]

In order to solve the conventional problems, the present invention provides a 1616 film laminated circuit having a plurality of wiring layers of this type, in which signal wiring is formed above or below a first wiring layer including adjacent signal wirings via an insulating layer. The present invention is characterized by a wiring structure in which a shield wire patterned to a constant size is provided in parallel with the adjacent integrated circuit wiring in the first wiring layer and grounded.

[For production]

With the wiring structure of the present invention, leakage of electrical signals from signal wirings is reduced, and wall talk occurring between signal wirings is reduced. Examples will be described below based on the drawings.

〔Example〕

1A and 1B are a cross-sectional view and a plan view of an internal wiring structure in an integrated circuit showing an embodiment of the present invention. Explain.

Si formed by selective oxidation on a semiconductor substrate
When the signal wirings 4 and 4' in the first wiring layer 3 are formed adjacent to each other on the upper surface of the dielectric film 2, such as 4. Electrical signals on one wiring leak to the other wiring, resulting in so-called crosstalk. A second wiring layer 6 is formed on the first wiring layer 3 via an insulating film 5 made of, for example, 5iN5. In order to suppress electrical coupling with the wiring in the first wiring layer 3, the signal wiring in the second wiring layer 6 is connected to the signal wiring in the first wiring layer 3, such as the signal wiring 7 in FIG. 4. Install it so that it intersects with 4'. As a result, the signal wiring in the second wiring layer 6 does not run parallel to the signal wiring 4.4' in the first wiring layer 3, and therefore the signal wiring 4.4' in the second wiring layer 6 does not run parallel to the signal wiring 4.4' in the first wiring layer 3.
′ by excluding the wiring part that intersects with
Leakage of electrical signals from the signal lines 4, 4' is reduced, and crosstalk occurring between the J lines 4, 4' can be reduced.

In the wiring structure shown in FIG. 1, for example, if there are four signal wirings, the crosstalk can be reduced to about 40 wirings.

Based on the wiring structure shown in Figure 1, the current LSlff
The dielectric film 2 has a thickness of 1.6 μm (7) Si02 film,
The wiring length, wiring width, and thickness of adjacent signal wirings 4 and 4' are each l.
mm, 2.5 pm, 0.8 μm, the rewiring interval is 1.5 μm, the distance between the upper surface of the dielectric film 2 and the lower surface of the shield wiring 8 is 2.4 μm, and the thickness of the shield wiring 8 is 1.5 μm.
5 μm, the insulating film 5 is a 5i3N film, and the shield wiring 8
FIG. 2 shows the results of analyzing the amount of crosstalk when the line width was changed from 0 μm to 6 μm. The horizontal axis shows the line width of the shield wiring 8, and the vertical axis shows the amount of crosstalk. In the analysis, since the semiconductor substrate l has a low resistivity of, for example, 5 Ωcm, it is assumed that this is the ground plane, and the insulating film 5 is
is L CM L (Low P
overCurrent Mode Logic
) An input signal with a rise time and a fall time of 10Q ps is connected to the signal wiring 4 from the pulse generator 13 under conditions close to the actual operating state in which the standard gates 14-1 to 14-4 of the
This figure shows the results of analyzing the amount of l:J stoke at the input end 1) of the gate 14-1 connected to the gate 14-1 and the output end 12 of the signal line 4'. From Figure 2, the crosstalk, which was about 7.8% when the shield wiring width was 0 μm, that is, when the shield wiring 8 was not present, began to decrease rapidly when the shield wiring width was less than 1 μm, and the If the wiring width is set to about 4 μm, which can be processed using current technology, the amount of crosstalk can be reduced to about 40% of that when there is no shield wiring. This can be obtained by increasing the interval between the signal lines 4.4' from 1.5 μm to about three times, and is equivalent to a 1-stoke reduction.

In the embodiment shown in FIG. 1, the signal wirings 4 and 4' in the first wiring layer 3 and the signal wirings 7 in the second wiring layer 6 are arranged so as to cross each other, and in the second wiring layer, We have explained an example in which the shielding wiring 8 is formed in parallel with the signal wiring 4.4' in the empty space excluding the wiring part that intersects with the signal wiring 4.4'. They may be placed so as to cover each other, which is one embodiment of the present invention.

Similar to FIG. 1, FIGS. 4 and 5 are cross-sectional structures of wiring showing other embodiments of the present invention. FIG. 4 shows a case where a second wiring layer 9 exists under the first wiring Ji 3 where the signal wirings 4, 4' are present, with an insulating film 5 interposed therebetween. Shield wiring 8' as in Figure 1
By installing the signal lines 4 and 4', crosstalk between the signal lines 4 and 4' can be reduced. Figure 5 shows signal wiring 4.4
The second interconnection layer 3 is provided with an insulating film 5 interposed between the top and bottom of the first interconnection layer 3 where the interconnection layer 3 exists. By providing the third wiring layer 6, 108', crosstalk between the signal wirings 4 and 4' can be reduced.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is not necessary to increase the wiring spacing or newly form a shield layer as in the conventional case, and therefore it is possible to avoid reducing the degree of circuit integration (and to improve the current design). Crosstalk between adjacent wires within an integrated circuit can be reduced without changing the process.

[Brief explanation of drawings]

FIG. 1a is a diagram showing a cross-sectional structure of internal wiring of an integrated circuit in one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a dielectric film, 3 first wiring layers, 4 and 4' are signal wirings, 5 is an insulating film, 6 is a second wiring layer, and 8 is a shield wiring. FIG. 1 is a diagram showing a planar structure of internal wiring of an integrated circuit in an embodiment of the present invention. In the figure, 4.4' is the 1st. Signal wiring in the wiring layer, 7 is a signal wiring in the second wiring layer, and 8 is a shield wiring. FIG. 2 is a diagram showing the dependence of the amount of crosstalk on the shield line width, which was obtained by analyzing the amount of crosstalk between adjacent wirings inside the integrated circuit in one embodiment of the present invention. In the figure, the horizontal axis is the shield line width, and the vertical axis is the amount of crosstalk. FIG. 3 is a diagram showing a circuit configuration used when analyzing the crosstalk reduction effect in one embodiment of the present invention. In the figure, 4.4' is the signal wiring, 8 is the shield wire, and 14
-1-14-4 is an LCML standard gate, 1) is a signal input terminal, 12 is a crosstalk observation point, and 13 is a pulse generator. FIG. 4 is a diagram showing a cross-sectional structure of internal wiring of an integrated circuit in one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a dielectric film, 3 is a first wiring layer, 4, 4' is a signal wiring, 5 is an insulating film, 8' is a shield wiring, and 9 is a second wiring layer. FIG. 5 is a diagram showing a cross-sectional structure of internal wiring of an integrated circuit in one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a dielectric film, 3 is a first wiring layer, 4.4' is a signal wiring, 5 is an insulating film, 6 is a second wiring layer, 8 and 8' are shield wirings, and 10 is a This is the third wiring layer. Patent Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Tama Mushi Hisa Gobe (2 others) J) - J5 AaS "= '1 Kiyoshi, Crosstalk (510) R - NcA) 纒 い ■ +JcI
)Example of internal wiring for δ in the integrated circuit of the present invention Fig. 4 Example of internal wiring in the integrated circuit of the present invention No. 5
Amendment to figure procedure dated June 1986 1, Indication of case Patent Application No. 45933 of 1988 2, Title of invention Wiring structure of integrated circuit 3, Person making amendment Relationship with case Patent applicant address Tokyo 1-1-6 Uchisaiwaicho, Chiyoda-ku, Miyako
(422) Shinfuji, Representative of Nippon Telegraph and Telephone Corporation
4. Agent 5: Number of inventions increased by amendment No. 3 of the drawings is attached as shown in "Figure 3". Part 3 of the same shows the circuit configuration using 1lJl'c to be analyzed.
figure

Claims (2)

[Claims] (1) In a semiconductor integrated circuit formed by laminating a plurality of wiring layers on a semiconductor substrate, a second wiring layer formed above or below a first wiring layer including adjacent signal wirings with an insulating layer interposed therebetween. A wiring structure for an integrated circuit, comprising: a wiring structure in which a shield line is provided in parallel with adjacent signal wiring in the first wiring layer, and the shield line is grounded. (2) The wiring structure of an integrated circuit according to claim 1, wherein the shield line has a line width that is 0.8 to 8 times the interval between the adjacent signal lines. .