JPS5969954A - Semiconductor device - Google Patents

Abstract

PURPOSE:To delay signals similarly, and to prevent the generation of a whisker and malfunction by inserting dummy capacitance using the same P-N junction to another signal line to be synchronized when parasitic capacitance by a tunnel resistor for one cross wiring in a signal line group to be synchronized enters therein. CONSTITUTION:Wirings 70 and 72, 74 must be crossed on a pattern layout, the tunnel resistor 51 to which an N type region 7-1 is formed is formed in a P type region 6, the wiring 70 is divided into 70-1, 70-2 and connected by the tunnel resistor 51, and the wirings 72, 74 pass on the region 7-1 through an insulating film. A wiring 76 must be synchronized with the wiring 70, a region 7-2 of the same width and length as the region 7-1 is formed in order to give dummy capacitance, and the wiring 76 is divided into two of 76-1 and 76-2 and connected by the region 7-2. The capacitance values and resistance values of the regions 7-1, 7-2 are approximately equal to each other because the regions 7-1, 7-2 have the same width and length and are arranged adjacently. Accordingly, retardation time at points P, Q between the two lines 70, 76 is made approximately constant.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to cross wiring in semiconductor devices, particularly integrated circuits.

Recently, in bipolar ICs, there has been an increase in the number of analog-digital mixed ICs that incorporate a digital section using an IL device and an analog section circuit on one chip.

With the increase in the scale of ICs, the number of wires connecting devices has also increased tremendously, and this is a particularly important problem in the 2L section.

Normally, at wiring intersection points in the analog part, a P+ region is formed from the N-type epitaxial surface by co-diffusion with the base of the NPN transistor, and the emitter N+ of the ENPN transistor is diffused into the P+ layer and the N+ region at both ends of the resistor.
It is widely used to short-circuit the + layers and use them as part of one wiring. At this time, between the P+ region of the tunnel resistance and the outer N type epitaxial region,
0. IPF to 03PF: A certain amount of parasitic capacitance is generated, but this is not a problem except for high frequency circuits.

On the other hand, cross wiring in the I2L section is dealt with as follows. In other words, it is a region co-diffused with the base diffusion of the NPN transistor and connected to the ground potential:
A 1LfcP+ region is provided, and a reactor region is formed in which the emitter of the NPN transistor is co-diffused in the P+ region.
Contact portions are formed at both ends of the N+ region to draw out the aluminum wiring, and other wirings that cross are passed over the N+ region via an insulating film.

Hereinafter, the region formed in the base for cross wiring will be referred to as a tunnel resistance. At this time, a parasitic capacitance of several PF exists between the N+ region and the P+ region, and since it is difficult to detour the wiring in I2L, parasitic capacitance is introduced everywhere in I2L. As a result, if a tunnel resistance is introduced into one of the signal lines to be synchronized, the signal will be delayed compared to the other, resulting in malfunction.

FIG. 1 shows an example of the use of a conventional tunnel resistor.

It is necessary to synchronize the signal line between NAND gate IA and N'AND gate IB and the signal line between NAND gate 2A and NAND gate 2B, but due to mask layout, NAND gate 2A and NAND gate 2
A tunnel resistor TN is inserted between it and B. Therefore, if things remain as they are, the waveform at point P (
In contrast to (a) in the same figure, the waveform at point Q, where there is a parasitic capacitance of several PF between it and GND, is as shown in (b) in the same figure, which causes signal delay.

FIG. 3 is a layout diagram of a widely used I2L section. On the left side of FIG. 3, there are 20 injector areas with a fanout number of 3. Two 2L parts 5° having a base region 22 and a collector region 24 are shown, and a tunnel resistor 100 for cross wiring is shown on the right side.

In the tunnel resistor 100, a P+ region 6 diffused from the surface of the N-type epitaxial layer 3 is connected to the insulating region 4, and is at a GND (ground) potential. In P+ area 6,
■An N+ region 7 of tunnel resistance is formed which is simultaneously diffused with the collector region 24 of the 2L section 100, and the collector region 2
4 and one end of the region 7 are connected by an aluminum wiring 26-1, and a wiring 26-2 is taken out from the other end of the region 7. Above the region 7, there are two +12s connected to the other collector region of the 2L section 100.

30 are intersecting. Note that 5 is the furnace collar area.

FIG. 4 is a schematic cross-sectional view of the structure taken along line A-A/Kin of FIG. , 7-10μ thick N
4 is an insulating P+ region, and 5 is an N+ collar, which is formed by diffusion deep from the surface so as to reach the buried region. 6 is a P resistance which is co-diffused with the base of the NPN transistor or whose concentration is lower than this. normal I
In L, the region 6 diffuses at the same time as the base of the NPN transistor, but in the case of a high breakdown voltage IL, the region 6 diffuses at the same time as the base of the IL. In order to improve
It is better to use regions. 7 is a furnace tunnel resistance region co-diffused with the NPN emitter, 8 is an oxide film, 26-1.26
-2.28.30 is the aforementioned A7 wiring. As can be seen from FIG. 4, both the P+ layer 6 and the N+ layer 7, which form the tunnel resistance, have a high concentration, and the concentration near the junction is 10
~IO is reached. Also, the signal level propagating within the IL is 0.
．． Since it is less than 7V, the parasitic capacitance of the tunnel resistance is several PF.
is common. In order to reduce this parasitic capacitance, it is possible to use multilayer metal wiring, but this method inevitably increases the cost due to the increase in the number of steps.

An object of the present invention is to provide a semiconductor device which eliminates the drawback that one of the signal lines to be synchronized is delayed and malfunctions due to parasitic capacitance formed by the tunnel resistance of the I2L section.

In the semiconductor device according to the present invention, when one of the signal lines to be synchronized has a parasitic capacitance due to the tunnel resistance of the cross wiring, the same PN junction is used for the other signal lines to be synchronized. By inserting a dummy capacitor, the signals have the same delay, thereby preventing the occurrence of whiskers and malfunctions.

Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 5 is an equivalent circuit diagram when the present invention is applied to a NAND gate.
A tunnel resistor 5 is installed between the inputs of 2B as shown in Figure 1.
2 has been inserted. Also, NA that should be synchronized with this
A dummy capacitor 52 equal to the capacitance and resistance value of the tunnel resistor 52 is inserted between the output of the NAND gate IB and the input of the NAND gate IB.
The waveforms at point Q become as shown in FIGS. 6(a) and 6(b), showing the same delay, and do not affect the logic operation of the IL.

FIG. 7 shows an example of appropriate use of dummy capacitors when the present invention is applied to three signal lines in accordance with FIG. 5. Wiring 70
and 72 and 74 are wirings that should intersect in the pattern layout. Therefore, a tunnel resistor 51 is created in which an N-type region 7-1 is formed in a P-type region 6, and the wiring 70 is connected to 70-1.
, 70-2 and are connected by a tunnel resistor 51, and wirings 72 and 74 pass over the region 7-1 via an insulating film.

The wiring 76 is a wiring line that needs to be synchronized with the wiring 70, and in order to provide the wiring 76 with a dummy capacitance, a region 7-2 having the same width and length as the region 7-1 is provided.
The wiring 76 is divided into two parts 76-1 and 76-2 and connected in a region 7-2.

Since regions 7-1 and 7-2 have the same width and length and are located close to each other, the capacitance and resistance values of regions 7-1 and 7-2 are approximately equal. Therefore, the two lines 70.7
The delay time at the points ')' and Q between 6 and 6 is also approximately constant as shown in FIG. As mentioned above, the region 6 is grounded.

FIG. 8 is a plan view showing another embodiment of the present invention. Since the wiring 80 and the wirings 83 to 87 need to intersect, a tunnel resistance is formed in the wiring 80 by the region 7-1, and the C5 wirings 8 are formed on the region 7-1 via an insulating film.
3 to 87 have passed. In addition, the wiring 80 and the wiring 81
．． Since it is necessary to synchronize the signals transmitted to the lines 81 and 82, it is necessary to provide dummy capacitors in the lines 81 and 82. However, in FIG. 8, the wiring 81 as shown in FIG.
．． Rather than providing a region for a dummy capacitance in series in a part of the wiring 81.82, a conductor 81-1.8 is provided in a part of the wiring 81.82.
By connecting the regions 7-2, 7-3 via 2-2, it is connected to the wiring 81.82. A capacity is provided in between.

Region 7-1 has a resistance component in addition to capacitance, and the arrangement fij
81 and 82 have only capacitance, but since the resistance component in region 7-1 is at most 100Ω, it has almost no effect on signal delay. Therefore, as shown in FIG. 8, even if the dummy capacitance does not have a resistance component, the delays between the signals to be synchronized are almost the same. In addition, area 7-1 and area 7-2.7
In order to have the same capacity as -3, make them the same width and length. In this case, it may be thought that the shape of the regions 7-1°7-2 may be made rectangular, for example, instead of the shape shown in FIG. 8, but the capacitance value of the regions 7-1.7-2.7- 3
Since it is determined by the sum of the areas of the bottom and side surfaces, area 7-1
By changing the width between This increases the fluctuation, so it is preferable that each region have the same width and length.

In Figures 7 and 8, the dummy capacitor is formed in one continuous area, but of course it may be divided into several elements with the same width and the elements may be interconnected. , some of these divided dummy capacitors may be used for wiring intersections. In this case, the capacitance values must be equal to each other in total for each dummy container. By performing the above-described design, the degree of freedom on the mask lay plate is greatly increased, and it becomes possible to reduce the chip size. At this time, it is desirable that the width of the resistance (capacitance) of the dummy capacitor and tunnel resistor be constant, and that they be arranged close to each other in the same direction so that the capacitances maintain consistency with each other.

FIG. 9 shows still another embodiment of the present invention. Figure 8 1
In this case, an opposite conductivity type region formed in a grounded one conductivity type region was used as a tunnel resistance, but in Fig. 9,
The P-type region 6 where the N-type region 7 is formed is not grounded, and instead, the P and N
The mold regions 6, 7 are connected to form a tunnel resistance. Therefore, the dummy capacitor also connects the P type region 6 and the N type region 7. In this case, it is biased, so
The capacitance formed by the P+ region 6 and the N-type epitaxial layer 3 formed at the same time as the NPN base diffusion is 0.1 to 0.
It is about 3 PF, which is one digit smaller than the capacitance value mentioned above.

Therefore, °c1 In this case, there is almost no need to consider the balance of capacitance values. In other words, the shapes may be slightly different. The left side of FIG. 9 shows the tunnel resistance, and the right side shows the dummy capacitance, but the withstand region 6 of the dummy capacitance may not be provided.

Furthermore, the dummy capacitance shown in FIG. 9 is the same as the concept shown in FIG. 8, and the wiring 9-3 is connected to the wiring to be synchronized with the wirings 9-1 and 9-2.

As described above, the I2L to which the present invention is applied can be achieved by carefully arranging dummy capacitors in the design without adding any special process, and by crossing wiring without affecting the logic of the I2L section. The present invention will become increasingly important as the scale of the IC increases, that is, the number of wiring lines increases rapidly.

Although the present invention has been described only when applied to I2L, it is obvious that similar effects can be obtained when applied to other general analog circuits and cross wiring in MO8LSI.

[Brief explanation of drawings]

Figure 1 is an equivalent circuit diagram of a conventional I2L with a tunnel resistor provided, Figure 2 is a voltage waveform diagram at points P and Q in Figure 1, and Figure 3 is an equivalent circuit diagram of a conventional I2L. A plan view showing the arrangement of the digital section and tunnel resistance, Figure 4 is A in Figure 3.
5 is an equivalent circuit diagram provided with a tunnel resistor and a dummy capacitor according to the present invention,
FIG. 6 is a voltage waveform diagram at points P and Q in FIG. FIG. 9 is a structural sectional view showing another embodiment of the present invention. 1...P type substrate, 2...N+ buried layer, 3...N type epitaxial layer, 4...
P+ insulating region, 5...N+lyr region, 6.
...P+ area, 7...N+ territory 8...
...Oxide film, 9...Al wiring, 51...
...Tunnel resistance, 52...Dummy capacitance. Figure 1, Section 2, Figure 3, Figure 4, Figure 5, Figure 70, 6, Figure 7, Figure 6,

Claims (1)

[Claims] In a semiconductor device having a wiring that passes through a region within a semiconductor substrate for cross wiring in a signal transmission line, a dummy capacitor is provided in another wiring through which a signal synchronized with a signal transmitted to the wiring is transmitted. A semiconductor device characterized by: