JPH0682671B2 - Wiring method of integrated circuit - Google Patents
Wiring method of integrated circuitInfo
- Publication number
- JPH0682671B2 JPH0682671B2 JP61045933A JP4593386A JPH0682671B2 JP H0682671 B2 JPH0682671 B2 JP H0682671B2 JP 61045933 A JP61045933 A JP 61045933A JP 4593386 A JP4593386 A JP 4593386A JP H0682671 B2 JPH0682671 B2 JP H0682671B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- signal
- shield
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路内部で隣接する信号配線相互で
生じるスクロトークを低減せしめる集積回路の配線方法
に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method for an integrated circuit, which reduces a crosstalk generated between adjacent signal wirings inside a semiconductor integrated circuit.
LSI技術の進展に伴う集積回路の高速・高密度化ととも
に、回路の接続配線相互で生じるクロストークが信号波
形劣化要因として無視できなくなつている。上記接続配
線間クロストークを低減するために、従来では、例えば
信号配線の間隔を拡大したり、該信号配線間にシールド
線を設置したり、或いは該信号配線を含む第１の配線層
と、その上部に絶縁層を介して形成されている第２の配
線層の間に新たにシールド層を形成することによつてク
ルストークの低減化を図つていた。Along with the progress of LSI technology, high-speed and high-density integrated circuits have become possible, and crosstalk between circuit interconnections cannot be ignored as a signal waveform deterioration factor. In order to reduce the crosstalk between the connection wirings, conventionally, for example, an interval between the signal wirings is enlarged, a shield wire is provided between the signal wirings, or a first wiring layer including the signal wirings, By newly forming a shield layer between the second wiring layers formed on the upper part of the second insulating layer with the insulating layer interposed therebetween, the Kurstalk is reduced.
上記、信号配線間隔の拡大、及び信号配線間へのシール
ド線の挿入によりクロストークを低減せしめる配線構造
では必然的に回路集積度の低下をきたし、高密度化を図
る上で問題であつた。また、上記シールド層の新たな形
成によりクルストークを低減せしめる配線構造では、各
配線層間の構造工程において、絶縁層の形成の他に新た
にシールド層の形成、及び第２の絶縁層の形成という工
程が必要となり、構造プロセスが複雑化するという問題
があつた。In the above wiring structure in which the crosstalk is reduced by increasing the signal wiring interval and inserting the shield line between the signal wirings, the degree of circuit integration is inevitably lowered, which is a problem in achieving high density. In addition, in the wiring structure in which the Kurstoke is reduced by newly forming the shield layer, a shield layer is newly formed and a second insulating layer is formed in addition to the formation of the insulating layer in the structure process between the wiring layers. There is a problem that the process is required and the structure process is complicated.
本発明の目的は上記の問題点を除去した、集積回路の内
部配線間におけるクロストーク低減化を実現することに
ある。It is an object of the present invention to realize the reduction of crosstalk between internal wirings of an integrated circuit by eliminating the above problems.
本願発明は従来の問題点を解決するため、半導体基板に
ｎ層（ｎは２以上の正数）からなる信号線を設置した配
線層を積層してなる半導体集積回路の、第ｎ層に形成さ
れた、隣接する信号線のクロストークを低減する集積回
路の配線方法において、第（ｎ−１）層の信号線を有す
る層或は第（ｎ＋１）層の信号線を有する層に、前記第
ｎ層に形成された信号線間隙の直上部に前記第ｎ層に形
成された信号線に平行して、前記信号線間隔の0.8倍乃
至８倍の線幅を有するシールド線を設置し、前記シール
ド線は前記第ｎ層に形成された信号線と、前記シールド
線を設けた層の信号線とがクロスする部分には設けない
ことを特徴とする。In order to solve the conventional problems, the present invention is formed in the nth layer of a semiconductor integrated circuit in which a wiring layer in which a signal line composed of n layers (n is a positive number of 2 or more) is installed on a semiconductor substrate. In the wiring method of an integrated circuit for reducing crosstalk between adjacent signal lines, the layer having the (n-1) th signal line or the layer having the (n + 1) th signal line is added to the A shield line having a line width of 0.8 times to 8 times the signal line interval is installed in parallel with the signal line formed in the nth layer immediately above the signal line gap formed in the nth layer. The shield line is not provided at a portion where the signal line formed on the n-th layer and the signal line on the layer where the shield line is provided cross each other.
本発明の配線方法により、信号配線からの電気信号の漏
れが低減され、信号配線相互で生じるクロストークが低
減される。以下図面に基づき実施例について説明する。According to the wiring method of the present invention, leakage of an electric signal from the signal wiring is reduced and crosstalk generated between the signal wirings is reduced. Embodiments will be described below with reference to the drawings.
第１図ａ、及びｂは本発明の一実施例を示した集積回路
における内部配線構造のＡ−Ａ′断面図、及び平面図で
あり、第１図a,bを用いて本発明の作用を説明する。半
導体基板１上に例えば選択酸化により形成されたSiO2等
の誘電体膜２の上面に第１の配線層３における信号配線
４、及び４′が隣接して形成されている時、信号配線4,
4′相互の電気的結合によつて、一方の配線上の電気信
号が他方の配線に漏れ、いわゆるクロストークが生じ
る。第１の配線層３上には例えばSi3N4等の絶縁膜５を
介して第２の配線層６が形成される。第２の配線層６に
おいて信号配線は、第１の配線層３内の配線との電気的
結合を抑えるため、例えば第１図ｂの信号配線７のよう
に第１配線層３内の信号配線4,4′と交差するように設
置する。これにより第２配線層６内で信号配線が第１配
線層３内の信号配線4,4′と並行して走ることはなく、
従つて第２配線層６内で信号配線4,4′と交差して走る
配線部分を除いた空きスペースに、信号配線4,4′と並
行してシールド用の配線８を形成でき、シールド配線８
を接地することにより、信号配線4,4′からの電気信号
の漏れが低減され、信号配線4,4′相互で生じるクロス
トークを低減することができる。1A and 1B are a sectional view and a plan view of an internal wiring structure in an integrated circuit showing an embodiment of the present invention, taken along the line AA ', and FIG. 1A and FIG. Will be explained. When the signal wirings 4 and 4 ′ in the first wiring layer 3 are formed adjacent to each other on the upper surface of the dielectric film 2 such as SiO 2 formed by selective oxidation on the semiconductor substrate 1, the signal wiring 4 ,
Due to the electrical coupling between the 4's, an electric signal on one wiring leaks to the other wiring, so-called crosstalk occurs. A second wiring layer 6 is formed on the first wiring layer 3 with an insulating film 5 such as Si 3 N 4 interposed therebetween. In order to suppress the electrical coupling of the signal wiring in the second wiring layer 6 with the wiring in the first wiring layer 3, for example, the signal wiring in the first wiring layer 3 like the signal wiring 7 in FIG. 1B. Install it so that it crosses 4,4 '. As a result, the signal wiring in the second wiring layer 6 does not run in parallel with the signal wirings 4, 4'in the first wiring layer 3,
Therefore, the shield wiring 8 can be formed in parallel with the signal wirings 4 and 4 ′ in an empty space in the second wiring layer 6 except the wiring portion that runs across the signal wirings 4 and 4 ′. 8
By grounding, the leakage of electric signals from the signal wirings 4 and 4'can be reduced, and crosstalk generated between the signal wirings 4 and 4'can be reduced.
第１図の配線構造において、例えば信号配線4,4′の線
幅と間隔を各々2.5μm,1.5μｍとした場合、シールド配
線８の線幅を４μｍ程度にすればクロストークを40％程
度に低減できる。In the wiring structure shown in FIG. 1, for example, if the line widths and intervals of the signal wirings 4 and 4 ′ are 2.5 μm and 1.5 μm, respectively, and if the line width of the shield wiring 8 is set to about 4 μm, the crosstalk will be about 40%. It can be reduced.
第１図に示した配線構造に基づいて、現状のLSI製造プ
ロセス技術で加工可能な材料、及び形状寸法として、誘
電体膜２を厚さ1.6μｍのSiO2膜、隣接信号配線4,4′の
配線長、配線幅、厚さを各々1mm,2.5μm,0.8μｍ、両配
線間隔を1.5μｍ、誘電体膜２の上面とシールド配線８
の下面の間隔を2.4μｍ、シールド配線８の厚さを1.5μ
ｍ、絶縁膜５をSi3N4膜とし、シールド配線８の線幅を
０μｍから６μｍまで変化させた場合のクロストーク量
を解析した結果を第２図に示す。横軸はシールド配線８
の線幅、縦軸はクロストーク量を示す。解析において
は、半導体基板１は例えば５Ωcm程度の低い抵抗率を有
するためこれを接地面と仮定し、また絶縁膜５は近似的
にシールド配線の上部にも無限遠まで続いていると仮定
し、第２図は、第３図の回路構成図に示すように信号配
線4,4′の両端にLCML（Low Power Current Mode Logi
c）の標準ゲート14−１〜14−４を接続した実動作状態
に近い条件で、パルス発生器13より立上り時間、立下り
時間がともに100psの入力信号を信号配線４に接続され
たゲート14−１の入力端11に加え、信号配線４′の出力
端12におけるクロストーク量を解析した結果を示したも
のである。第２図より、シールド配線幅が０μｍ、すな
わちシールド配線８が存在しない状態では約7.8％であ
つたクロストーク量は、シールド配線幅がわずか１μｍ
に満たないうちに急激に低減されはじめ、シールド配線
幅を現状の技術で加工可能な４μｍ程度にすれば、クロ
ストーク量をシールド配線が存在しないときの約40％に
低減することができる。これは、信号配線4,4′の間隔
を1.5μｍから約３倍に拡大して得られるクロストーク
低減量と同等である。Based on the wiring structure shown in FIG. 1, as a material and shape dimension that can be processed by the current LSI manufacturing process technology, the dielectric film 2 is a SiO 2 film with a thickness of 1.6 μm, adjacent signal wirings 4, 4 ′. Wiring length, wiring width, and thickness of 1 mm, 2.5 μm, and 0.8 μm, respectively, the distance between both wirings is 1.5 μm, the upper surface of the dielectric film 2 and the shield wiring 8
The bottom surface of the shield is 2.4 μm, and the thickness of the shield wiring 8 is 1.5 μm.
FIG. 2 shows the result of analysis of the crosstalk amount when the line width of the shield wiring 8 was changed from 0 μm to 6 μm with the insulating film 5 being a Si 3 N 4 film. Horizontal axis is shield wiring 8
And the vertical axis represents the amount of crosstalk. In the analysis, since the semiconductor substrate 1 has a low resistivity of, for example, about 5 Ωcm, it is assumed that this is a ground plane, and the insulating film 5 is assumed to approximately extend to the upper part of the shield wiring to infinity. As shown in the circuit configuration diagram of FIG. 3, FIG. 2 shows LCML (Low Power Current Mode Logi
Under the condition close to the actual operating state in which the standard gates 14-1 to 14-4 in c) are connected, the gate generator 14 connected to the signal wiring 4 receives an input signal of which the rise time and the fall time are both 100 ps from the pulse generator 13. 2 shows the result of analyzing the amount of crosstalk at the output end 12 of the signal wiring 4'in addition to the input end 11 of -1. From FIG. 2, the shield wiring width is 0 μm, that is, about 7.8% when the shield wiring 8 is not present, the crosstalk amount is only 1 μm.
If the shield wiring width is set to about 4 μm, which can be processed by the current technology, the amount of crosstalk can be reduced to about 40% when the shield wiring is not present. This is equivalent to the crosstalk reduction amount obtained by expanding the distance between the signal wirings 4 and 4 ′ from 1.5 μm to about 3 times.
なお第１図に示した実施例において、第１配線層３内の
信号配線4,4′と第２配線層６内の信号配線７を交差す
るように配置し、第２配線層内で、信号線4,4′と交差
して走る配線部分を除いた空きスペースに信号配線4,
4′と並行してシールド用の配線８を形成した例につい
て説明したが、シールド用配線を積極的にかぶせるよう
に配置してもよく、本発明の一態様である。In the embodiment shown in FIG. 1, the signal wirings 4 and 4'in the first wiring layer 3 and the signal wiring 7 in the second wiring layer 6 are arranged so as to cross each other, and in the second wiring layer, Signal wiring 4, 4'in the empty space excluding the wiring part that runs crossing the signal wiring 4, 4 '
Although an example in which the shield wiring 8 is formed in parallel with 4 ′ has been described, it may be arranged so as to positively cover the shield wiring, which is one embodiment of the present invention.
第４図、及び第５図は第１図と同様に、本発明における
他の実施例を示した配線の断面図構造である。第４図は
信号配線4,4′が存在する第１の配線層３の下部に絶縁
膜５を介して第２の配線層９が存在する場合であり、第
２の配線層９内に第１図と同様にシールド配線８′を接
地することにより、信号配線4,4′間のクロストークを
低減することができる。第５図は信号配線4,4′が存在
する第１の配線層３の上部にも下部にもそれぞれ絶縁膜
５を介して第2,第３の配線層6,10が存在する場合であ
り、第2,第３の配線層6,10内の両方に第１図，第４図と
同様にシールド配線8,8′を設置することにより、信号
配線4,4′間のクロストークを低減することができる。Similar to FIG. 1, FIGS. 4 and 5 are sectional views of the wiring showing another embodiment of the present invention. FIG. 4 shows the case where the second wiring layer 9 is present below the first wiring layer 3 where the signal wirings 4 and 4 ′ are present, with the insulating film 5 interposed therebetween. By grounding the shield wiring 8'as in the case of FIG. 1, crosstalk between the signal wirings 4 and 4'can be reduced. FIG. 5 shows a case where the second and third wiring layers 6 and 10 are present above and below the first wiring layer 3 having the signal wirings 4 and 4 ', respectively, with the insulating film 5 interposed therebetween. By installing the shield wirings 8 and 8'in both the second and third wiring layers 6 and 10 as in FIGS. 1 and 4, the crosstalk between the signal wirings 4 and 4'is reduced. can do.
以上の説明から明らかな如く、本発明によれば従来のよ
うに配線間隔の拡大やシールド層の新たな形成を必要と
せず、従つて回路集積度の低下をまねくことなく、かつ
現状の構造プロセスを変更することなく、集積回路内部
の隣接配線間でのクロストークを低減することができ
る。As is clear from the above description, according to the present invention, it is not necessary to increase the wiring interval or newly form a shield layer as in the conventional case, and thus the circuit integration degree is not deteriorated and the current structural process is performed. It is possible to reduce crosstalk between adjacent wirings inside the integrated circuit without changing the.
第１図ａは本発明の一実施例における集積回路内部配線
の断面構造を示す図である。 図において１は半導体基板、２は誘導体膜、３は第１配
線層、4,4′は信号配線、５は絶縁膜、６は第２配線
層、８はシールド配線である。 第１図ｂは本発明の一実施例における集積回路内部配線
の平面構造を示す図である。 図において4,4′は第１配線層内の信号配線、７は第２
配線層内の信号配線、８はシールド配線である。 第２図は本発明の一実施例における集積回路内部の隣接
配線間のクロストーク量を解析して得られたシールド線
幅に対するクロストーク量依存性を示す図である。 図において横軸はシールド線幅，縦軸はクロストーク量
である。 第３図は本発明の一実施例におけるクロストーク低減効
果を解析する際に用いた回路構成を示す図である。 図において4,4′は信号配線、８はシールド線、14−１
〜14−４はLCML標準ゲート、11は信号入力端、12はクロ
ストーク観測点、13はパルス発生器である。 第４図は本発明の一実施例における集積回路内部配線の
断面構造を示す図である。 図において１は半導体基板、２は誘電体膜、３は第１配
線層、4,4′は信号配線、５は絶縁膜、８′はシールド
配線、９は第２配線層である。 第５図は本発明の一実施例における集積回路内部配線の
断面構造を示す図である。 図において１は半導体基板、２は誘電体膜、３は第１配
線層、4,4′は信号配線、５は絶縁膜、６は第２配線
層、８及び８′はシールド配線、10は第３配線層であ
る。FIG. 1a is a diagram showing a cross-sectional structure of internal wiring of an integrated circuit in one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a dielectric film, 3 is a first wiring layer, 4 and 4'are signal wirings, 5 is an insulating film, 6 is a second wiring layer, and 8 is a shield wiring. FIG. 1b is a diagram showing a plane structure of internal wiring of an integrated circuit in one embodiment of the present invention. In the figure, 4 and 4'are signal wirings in the first wiring layer, and 7 is a second wiring.
Signal wirings in the wiring layer and reference numeral 8 are shield wirings. FIG. 2 is a diagram showing the crosstalk amount dependence on the shield line width obtained by analyzing the crosstalk amount between adjacent wirings inside the integrated circuit in one embodiment of the present invention. In the figure, the horizontal axis is the shield line width, and the vertical axis is the amount of crosstalk. FIG. 3 is a diagram showing a circuit configuration used when analyzing the crosstalk reducing effect in the embodiment of the present invention. In the figure, 4'and 4'are signal wiring, 8 is a shielded wire, 14-1
14-4 are LCML standard gates, 11 is a signal input terminal, 12 is a crosstalk observation point, and 13 is a pulse generator. FIG. 4 is a diagram showing a cross-sectional structure of an integrated circuit internal wiring in one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a dielectric film, 3 is a first wiring layer, 4 and 4'are signal wirings, 5 is an insulating film, 8'is a shield wiring, and 9 is a second wiring layer. FIG. 5 is a view showing the cross-sectional structure of the internal wiring of the integrated circuit in one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a dielectric film, 3 is a first wiring layer, 4 and 4'are signal wirings, 5 is an insulating film, 6 is a second wiring layer, 8 and 8'are shield wirings, and 10 is This is the third wiring layer.
Claims (1)
らなる信号線を設置した配線層を積層してなる半導体集
積回路の、第ｎ層に形成された、隣接する信号線のクロ
ストークを低減する集積回路の配線方法において、 第（ｎ−１）層の信号線を有する層或は第（ｎ＋１）層
の信号線を有する層に、前記第ｎ層に形成された信号線
間隙の直上部に前記第ｎ層に形成された信号線に平行し
て、前記信号線間隔の0.8倍乃至８倍の線幅を有するシ
ールド線を設置し、 前記シールド線は前記第ｎ層に形成された信号線と、前
記シールド線を設けた層の信号線とがクロスする部分に
は設けないことを特徴とする集積回路の配線方法。1. An adjacent signal line formed in the n-th layer of a semiconductor integrated circuit in which a wiring layer in which signal lines made up of n layers (n is a positive number of 2 or more) is provided on a semiconductor substrate is laminated. In the wiring method of the integrated circuit for reducing the crosstalk, the signal formed on the n-th layer in the layer having the (n-1) -th signal line or the layer having the (n + 1) -th signal line A shield wire having a line width of 0.8 times to 8 times the signal line interval is installed parallel to the signal line formed in the nth layer immediately above the line gap, and the shield line is the nth layer. A wiring method for an integrated circuit, wherein the signal line formed on the wiring and the signal line on the layer on which the shield line is provided are not provided at a crossing portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61045933A JPH0682671B2 (en) | 1986-03-03 | 1986-03-03 | Wiring method of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61045933A JPH0682671B2 (en) | 1986-03-03 | 1986-03-03 | Wiring method of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62203351A JPS62203351A (en) | 1987-09-08 |
| JPH0682671B2 true JPH0682671B2 (en) | 1994-10-19 |
Family
ID=12733062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61045933A Expired - Lifetime JPH0682671B2 (en) | 1986-03-03 | 1986-03-03 | Wiring method of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682671B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2778060B2 (en) * | 1988-11-21 | 1998-07-23 | 日本電気株式会社 | Semiconductor integrated circuit device |
| JP2751591B2 (en) * | 1990-07-16 | 1998-05-18 | ソニー株式会社 | Method for manufacturing semiconductor memory device |
| US8803320B2 (en) | 2010-10-28 | 2014-08-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuits and fabrication methods thereof |
| JP2013074075A (en) * | 2011-09-27 | 2013-04-22 | Toshiba Corp | Semiconductor device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5645070A (en) * | 1979-09-21 | 1981-04-24 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS59144171A (en) * | 1983-02-07 | 1984-08-18 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS6015947A (en) * | 1983-07-06 | 1985-01-26 | Fujitsu Ltd | Semiconductor device |
| JPS60224244A (en) * | 1984-04-20 | 1985-11-08 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
-
1986
- 1986-03-03 JP JP61045933A patent/JPH0682671B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62203351A (en) | 1987-09-08 |
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