JPH0846049A - Wiring method of integrated circuit and its manufacture, and integrated circuit using the circuit - Google Patents

Abstract

PURPOSE:To realize power supply wiring which can prevent eletromigration by reducing 2 chip area by forming a metallic wiring layer on a substrate and by repeating a plurality of processes such as etching, formation of an oxide film, boring in a wiring part and formation of a metallic film in a hole part. CONSTITUTION:A first layer metallic wiring 210 is formed all over on a substrate 107 and a specified first layer metallic wiring 210 is formed by etching. An oxide film 211 is generated and a hole 213 is shaped in a specified part. A metallic layer 214 is selectively generated in a part of the hole 213. In the process, flattening technique is adopted. An oxide film is formed, a hole is partially shaped, metal is buried in the hole and a second layer metallic wiring is generated. Similar treatments are repeated also for following layers including a third layer of a wiring group separated in a vertical direction by an oxide film insulation matter in this way. Thereby, it is possible to increase a sectional area of a wiring without increasing a width of a power supply wiring and to prevent disconnection by electromigration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
More specifically, the present invention relates to a wiring method and a manufacturing method thereof when there are a plurality of wiring groups vertically separated by an insulating layer, and an integrated circuit using the wiring method.

[0002]

2. Description of the Related Art As the scale of integrated circuits increases, the number of wiring layers used for wiring between elements is increasing. From a conventional circuit in which an integrated circuit is formed by using a wiring layer of a metal first layer and a metal second layer as an upper layer of a polysilicon layer which is also used for a gate of a transistor, a metal third layer or a metal fourth layer is used. The number of integrated circuits is also increasing. Further, in the integrated circuit, reduction of the chip area is indispensable for reducing the manufacturing cost. As the process is becoming finer, the signal wiring for transmitting the logical value is thin, and the area occupied on the chip does not increase so much. However, since the power supply wiring for supplying power to the highly integrated device has a reduced wiring height and the supplied current amount does not change so much, it cannot be thinned to prevent disconnection due to electromigration. This is an obstacle to reducing the area. Therefore, in consideration of migration, it is being attempted to reduce the chip area by forming a wide wiring at the root of a power supply through which a large amount of current flows and by narrowing the power supply wiring near a tip end where a small amount of current flows.

As one of the conventional techniques close to the present invention, there are a semiconductor manufacturing method and a semiconductor device described in JP-A-2-238629 and JP-A-3-82031. In this conventional technique, a specific power supply wiring is formed as a metal layer having a high height, and the current density and the wiring surface area are increased without increasing the chip area.

Further, with the recent miniaturization of transistors, and because of the necessity of forming analog operating circuits and high-speed circuits on an integrated circuit, there is an increasing need to prevent malfunction due to noise.

Another conventional technique close to the present invention is a design method described in Japanese Patent Laid-Open No. 2-121349.
In this conventional technique, one wiring layer is formed above the transistor region and connected to the ground potential so that the transistor is not affected by noise from the wiring layer above the shield layer. Further, in the semiconductor devices described in JP-A-2-82531, JP-A-2-65238 and JP-A-2-65239, wirings and wiring layers are provided only for noise shielding. Further, there is a method of applying a shielding method, in which a wiring is surrounded by a conductor, to a printed circuit board, which has been conventionally used in a coaxial cable.
2191 and JP-A-62-219691.

In recent years, Monthly Semiconductor World 199
Multilayer wiring by flattening multilayer wiring technology by the selective growth method as shown in December 152, p. 152, and chemical mechanical polishing technology as described in Monthly Semiconductor World January 1994, p. 58. Time flattening technology has been established. This makes it possible to realize stacked contacts at the same coordinates, called stacked vias, in multilayer wiring.

[0007]

As described in the prior art, it is impossible to reduce the cross-sectional area of the power supply wiring in order to prevent disconnection due to electromigration, and the height of the metal wiring layer is constant. Therefore, there is a problem in that it is necessary to form a wide wiring and the chip area increases. However, the effect of increasing the cross-sectional area is small even if the conventional metal wiring is used only for the power supply line.
Further, in an integrated circuit which has been miniaturized, a problem may occur in that noise caused by a change in wiring voltage causes the integrated circuit to malfunction. However, if the wiring or wiring layer is used only for shielding noise, the chip area and the manufacturing cost will be greatly increased.

For example, Japanese Patent Laid-Open No. 2-23 which is a conventional technique.
In the semiconductor manufacturing method and the semiconductor device described in 8629 and JP-A-3-82031, although a new wiring is stacked, only a part of the wiring layer is effectively used. Another prior art, Japanese Patent Laid-Open No. 2-12
1349, JP-A-2-82531, JP-A-2-6523
8. In the semiconductor device described in JP-A-2-65239, the wiring and the wiring layer are provided only for the purpose of shielding noise, and the increased wiring area and the manufacturing cost of the newly formed wiring layer are high. . In addition, JP-A-4-3421
No. 91 and Japanese Patent Laid-Open No. 62-216961, the method of applying a shield method in which a wiring is surrounded by a conductor like a coaxial cable to a printed circuit board, a special wiring is embedded,
Since layers are added later, they cannot be used in an integrated circuit manufacturing method in which layers are stacked from the lower layer.

An object of the present invention is to manufacture an integrated circuit capable of preventing disconnection due to electromigration of a power supply line without increasing the chip area, and preventing noise due to a change in a signal from malfunctioning an integrated circuit. An object is to provide a wiring method, a design support device, and an integrated circuit that are low in cost.

[0010]

In order to achieve the above object, in the wiring method of the present invention, the heights of the wirings belonging to the wiring group vertically separated by the insulating layer have a plurality of types. In addition, a wiring layer is expanded to a region including wiring of another layer.

[0011]

According to the present invention, the cross-sectional area of the wiring can be increased and the disconnection due to electromigration can be prevented without increasing the width of the power supply wiring and without significantly increasing the chip manufacturing cost. Further, since the good shield conductor is arranged in the vicinity of the signal which becomes the noise source, it is possible to reduce the influence of the magnetic flux from the noise source on other circuits.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a diagram for explaining the basic concept of the present invention. The wiring 106 and the wirings 101 and 102 shown in FIG.
The wiring is different in height. The layer indicated by 103 not only increases the wiring cross-sectional area of the wirings 101 and 102, but also plays a role of shielding noise from the wiring 106 and the like. This layer 103 also increases the wiring cross-sectional area of the upper wiring 105. Next, an outline of an integrated circuit manufacturing method for realizing the present invention will be described with reference to FIG. In recent years, the planarization multilayer wiring technology by the selective growth method as shown in page 152 of December 1993 issue of Semiconductor World, and the monthly semiconductor world January 1994 issue of 58.
The planarization technique for multilayer wiring has been established by the chemical mechanical polishing technique as described on the page. This makes it possible to realize stacked contacts at the same coordinates, called stacked vias, in multilayer wiring. The present invention utilizes the above planarization process technology.

The generation of the wiring layer related to the present invention will be described. In FIG. 2A, the first layer metal wiring 210 is formed on the substrate.
Are formed on the entire surface. Figure 2 (b) by etching
First layer metal wiring as shown in FIG. Next, oxide film 2
11 is generated and a hole is formed in the portion shown in FIG. Figure 2
As shown in (d), a metal layer is selectively formed in the hole portion. Here, the flattening technique is used. As shown in FIG. 2E, an oxide film is further formed and a hole is partially formed. As shown in FIG. 2F, the hole is filled with metal. It is sufficient to generate the second layer metal wiring on the result of FIG. Here, among the finally formed metal layers, the wiring groups vertically separated by the oxide film insulator are called the first layer metal wiring and the second layer metal wiring from the bottom. Third
Similar processing may be repeated for layers and subsequent layers.

FIG. 3 shows an example of wiring in the same layer metal wiring (a wiring group vertically separated by an insulator) formed by the present invention. Wiring 301, Wiring 302, Wiring 303
The wiring 304, the wiring 305, and the wiring 306 have the same height. As described above, if the number of wirings having different heights is increased in manufacturing, the processing from 203 to 205 in FIG. 2 is repeated. Therefore, the sectional area is not controlled only by the height, but the sectional area is controlled by using the wirings having the same height but different widths such as the wiring 301 and the wiring 302.

An embodiment of the invention relating to the noise shield will be described with reference to FIG. The layer 403 shown in FIGS. 4A and 4B has both the function of the power supply wiring and the function of the noise shield. In Japanese Patent Laid-Open No. 2-121349 of the prior art, only a portion having a transistor is shielded, but in the example of the present invention, a power supply or ground shield is formed on the entire surface.
At this time, since it is necessary to connect the transistor portion and the wiring portion of the upper layer, the connection is realized by the same manufacturing method as that shown in FIG. 2 as shown in FIG. FIG. 4C is a view of the shape of each forming layer as seen from above.

A preferred embodiment will be described with reference to FIGS. 5, 1 and 6. FIG. 5 shows an example of power supply wiring according to the conventional method. As shown in Fig. 5 (a), VCC net 5
04 and GND net 505 are supplied from pad 503 to each block 502. The wiring is wide to prevent electromigration. When formed as an integrated circuit in this embodiment, it is composed of the first-layer metal wiring of the horizontal wiring shown in FIG. 5B and the second-layer metal wiring of the vertical wiring shown in FIG. 5C. ing. FIG. 1 shows a sectional view of a wiring layer structure according to the present invention. First layer metal wiring 1
Reference numeral 06 is a thin-line general signal wiring. 101 and 102 are examples of power supply wiring. The wiring layer indicated by 103 has both the function of the power supply wiring and the function of the noise shield. In the embodiment of the present invention, the wiring layer 103 not only increases the cross-sectional area of the power wiring belonging to the wiring layer 101, but also increases the cross-sectional area of the power wiring formed by the wiring layer 105. This will be described with reference to FIG. FIG. 6A is a power supply wiring display on the design support device. Since the power supply is reinforced by using the second-layer metal wiring, the wiring width viewed from above is narrower than that of the prior art, and the chip area can be reduced. FIG. 6B is an example of power supply wiring formed by using the first-layer metal wiring, and FIG. 6C is an example of power supply wiring formed by using the third-layer metal wiring. Then, the signal wiring is also generated at the same time. The second-layer metal wiring is a wiring layer having both a power supply wiring reinforcing function and a shielding function. It reinforces and shields the power supply wiring regardless of the vertical or horizontal direction of the wiring. As another example,
As shown in FIG. 6D, the second layer metal wiring can be wired above the block and above the empty wiring area to enhance the power wiring cross-sectional area increasing function and the shielding function.

An embodiment of a new shield will be described with reference to FIG. As shown in FIG. 7, shield layers 701, 702, 704, and 705 are formed so as to surround the signal wiring 703. The forming method hj is similar to the method shown in FIG.
In this embodiment, since the configuration is similar to that of the coaxial cable, it is possible to propagate a high frequency signal.

In the above-described embodiments, the present invention has been described by taking the power supply wiring as an example, but the present invention can be similarly applied to a wiring in which a large current flows such as clock supply logic.

The design support device required to implement the present invention will be described below.

FIG. 8 shows an example in which conventional wiring is displayed on the design support device. The wiring is represented by a set of rectangles. This is commonly called a segment. The segment 801 and the segment 802 are components that realize one net. The segment 801 is formed by the second layer metal wiring, and the segment 802 is formed by the first layer metal wiring. Actually, there is a part called a via for connecting segments of different layers, but the description is omitted. In the conventional case where the heights of layers are the same, it is possible to express the wiring information of FIG. 8 by a table example as shown in FIG. Here, column 901 is the name of the segment, 902 is the name of the net realized by the segment, 903 is the starting point coordinate of the center line of the segment, 904 is the ending point coordinate of the center line of the segment, 905 is the width of the segment, and 906 is If the wiring layer number is 2, it indicates a metal layer formed such as a second layer metal wiring. However, in the case of the wiring example according to the present invention, for example, the segment 801 and the segment 803 are the same wiring layer but have different heights when formed. An example of such a table that handles data is shown in FIG. The column 1001 represents not the wiring layer number for each segment but the column number in another table 1020. Columns 1004 and 1005 represent a lower limit layer and an upper limit layer in a thickness unit when each entry is actually manufactured. For example, in FIG. 2, the portion formed by the process 202 is L1, and the portion generated by the process 204 is L2. Wiring table number 1 is the first layer metal wiring whose height from L1 to L1 is 2, and wiring table number 3 is L1.
Means a first-layer metal wiring having a height of 6 to L2. In this way, the wirings of different heights according to the present invention can be handled inside the design support device.

FIG. 11 shows a display example on the design support apparatus according to the present invention. In the original display on the workstation, the color and the hatching can be combined to make the display easy to see. Here, the outline of the display method according to the present invention will be described by using the simple hatching. The wiring table number 2 is indicated by the hatching with a downward sloping line in the segment 803. The checkered pattern of the segment 801 shows the wiring table number 4 in which the diagonally downward hatching and the upwardly diagonal hatching overlap each other on the display. In the actual device, it seems that they are overlapped by wearing colors. Only one instruction such as movement on the layout is given to the segment 801, but it appears that the L3 layer and the L4 layer are overlapped on the display.

By doing so, wiring table number 4
The designer can clearly indicate that the segment of No. and the segment of wiring table No. 2 must not overlap.

[0024]

As described above, according to the present invention, it is possible to realize a power supply wiring which can reduce the chip area and prevent electromigration. Further, the shield layer can be formed to prevent malfunction due to noise, and the chip manufacturing cost does not increase so much.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an integrated circuit having a power supply line wiring area increase and a noise shield effect, which is a feature of the present invention.

FIG. 2 is a diagram schematically showing a manufacturing process of an integrated circuit which realizes the present invention.

FIG. 3 is an example of wirings having different heights and widths in the same wiring layer according to the present invention.

FIG. 4 is a diagram showing a configuration of a wiring layer having both a shield function and a power supply reinforcing function in the present invention.

FIG. 5 is a diagram showing an example of power supply wiring in a conventional technique.

FIG. 6 is a diagram showing a wiring example of a power supply in an example of performing power supply reinforcement and shielding in a more desirable form in the present invention.

FIG. 7 is a diagram showing an example of shielding all around a signal according to the present invention.

FIG. 8 is an example of expressing general wiring on a design support device.

FIG. 9 is an example of a table expressing wiring inside a design support device according to a conventional technique.

FIG. 10 is an example of a table expressing wiring in the design support device according to the present invention.

FIG. 11 is a display example of wiring from the design support device according to the present invention.

[Explanation of symbols]

 101. First layer metal wiring 102. First layer Second layer connection wiring 103. Second layer metal wiring 104. Second layer Third layer connection gold wiring 105. Third layer metal wiring 107. Substrate 210. Metal layer 211. Oxide film insulator 213. Hole 214. Metal layer 301. Section of wiring 401. First layer metal wiring layer 403. Second layer metal wiring 404. Third layer metal wiring 501. Chip 502. Block 503. Terminal 504. Power supply wiring 505. Power supply wiring (ground) 601. Chip 602. Block 603. Terminal 604. Power supply wiring 605. Power supply wiring (ground) 701. First layer metal wiring 702. First layer second interlayer connection wiring 703. Second layer metal wiring 704. Second layer Third layer connection wiring 705. Third layer metal wiring 801. Display of wiring 901. Table contents

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mikako Miyama 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (11)

[Claims] 1. A step of forming a metal wiring layer on a substrate, a step of etching the metal wiring layer in a predetermined pattern, a step of forming an oxide film on the substrate, and a step of forming a hole in a predetermined wiring portion. And a step of forming a metal film in the hole portion,
A method of manufacturing an integrated circuit, comprising repeating a plurality of steps including a step of flattening a surface of an oxide film and a metal film. 2. A step of creating a first table having a segment and a number to be a wiring element, a wiring net name, coordinates indicating a wiring position, a wiring width and a classification number, the classification number and a layer. Wiring of an integrated circuit including a step of creating a second table consisting of a name and a height, and a step of forming a pattern diagram of the integrated circuit by computer processing from the first table and the second table and displaying the screen on the screen. Method. 3. A method for forming wirings in an integrated circuit, wherein some wiring groups in a set of wiring groups vertically separated by an insulating layer are partially or entirely formed in other wiring groups. The wiring method is characterized in that it is a region including a region occupied by the wiring. 4. A method of forming wirings in an integrated circuit, wherein some wiring groups in a set of wiring groups vertically separated by an insulating layer are partially or wholly in other wiring groups. And a wiring method for increasing the wiring cross-sectional area of the wiring. 5. A method of forming wirings in an integrated circuit, wherein some wiring groups in a group of wiring groups vertically separated by an insulating layer are used as wirings above and below the wiring group. 2. The wiring method according to claim 1, wherein the area is an area including an area occupied by a part or all of the wires of the group. 6. A method of forming wirings in an integrated circuit, wherein some wiring groups in a set of wiring groups vertically separated by an insulating layer are used as wirings above and below the wiring group. The wiring method according to claim 2, wherein the wiring method is used for increasing a wiring cross-sectional area of a part or all of the wirings of the group. 7. A method of forming a wiring in an integrated circuit, characterized in that there are a plurality of types of width and height of wiring belonging to a wiring group vertically separated by an insulating layer. Method. 8. A wiring method for forming a wiring in an integrated circuit, comprising forming a wiring for shielding an insulating layer above and below and to the left and right of a wiring for passing a part of a signal. . 9. A method for forming wirings in an integrated circuit, wherein some wiring groups in a set of wiring groups vertically separated by an insulating layer are partially or wholly in other wiring groups. An integrated circuit characterized by being a region including a region occupied by the wiring. 10. A method for forming wirings in an integrated circuit, wherein some wiring groups in a set of wiring groups vertically separated by an insulating layer are partially or entirely formed in other wiring groups. An integrated circuit which is used to increase the wiring cross-sectional area of the wiring. 11. A method of forming a wiring in an integrated circuit, comprising forming wiring for shielding an insulating layer above and below and to the left and right of a wiring for passing a part of a signal. .