JP5401699B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that supplies a voltage from an external power supply to electrode pads formed on a semiconductor chip via bonding wires.

  The power of an LSI (Large-Scale Integrated circuit) is supplied to a bonding pad provided at the peripheral portion of the semiconductor chip, and is supplied from the peripheral portion of the chip to the central portion through a power supply wiring. At this time, the voltage supplied to the central portion is lowered due to the voltage drop due to the resistance of the power supply wiring, and the LSI may malfunction. In order to alleviate this phenomenon called IR drop, several techniques have been proposed so far.

  For example, the technique disclosed in Japanese Patent Application Laid-Open No. 2004-221260 (Patent Document 1) relates to a semiconductor chip in which a plurality of functional regions are formed. In this prior art, the first pad connected to the external connection terminal is formed in the peripheral portion, and the second pad connected to the functional region is located on the inner side of the position where the first pad is formed. Provided. Then, the first pad and the second pad are wire-connected. The first pad and the second pad can be connected in parallel by a wire and a wiring pattern.

  Further, in the technique disclosed in Japanese Patent Laying-Open No. 2005-85829 (Patent Document 2), a peripheral pad is provided in the peripheral part of the semiconductor chip, and a center for supplying power to a part other than the peripheral pad of the semiconductor chip. Part pads are provided. A plurality of center pads are arranged in a lattice pattern, and the center pads are connected to each other by wire bonding.

  Further, the technique disclosed in Japanese Patent Application Laid-Open No. 11-307383 (Patent Document 3) is similar to the above-described conventional technique, although the problem is different. An object of this technique is to provide a semiconductor device that does not require a package, a wiring board, or the like to be changed even if the wiring of a chip is changed. Specifically, when a chip is formed on a semiconductor wafer, a discontinuous linear pattern made of the same conductive material as the bonding pad is formed in the scribe line region to form a relay pad. When packaging, the center pad and the relay pad of the chip, and the relay pad and the lead are respectively wire-bonded.

The above-described problem of the power supply wiring similarly occurs in the ground wiring. That is, since the ground voltage increases due to the resistance of the ground wiring, the LSI may malfunction.
JP 2004-221260 A JP-A-2005-85829 JP-A-11-307383

  Usually, in order to suppress IR drop, a large number of bonding pads are provided in the peripheral region of the substrate, and a power supply voltage is supplied to the semiconductor circuit from the large number of pads. However, the total number of pads that can be provided in the peripheral region of the substrate is limited, and the number of pads allocated for power supply among these pads is also limited. Therefore, as described above, a method of reducing the wiring resistance by providing a bonding pad in the central region of the semiconductor chip and wire-connecting the pad in the central region and the pad in the peripheral region is effective.

  However, in this case as well, there are limitations on the location and total number of bonding pads provided in the central region of the substrate. First, the lower layer side of the bonding pad may be damaged during bonding. For this reason, it is necessary to provide an interference layer on the lower layer side of the bonding pad. Second, if a large number of bonding pads are provided at the center of the substrate and wire connections are made, not only does the problem of short-circuiting between wires easily occur, but it is also disadvantageous in terms of cost. Therefore, it is desirable to effectively suppress IR drop using as few wires as possible.

  The present invention has been made in consideration of the above problems, and an object thereof is to provide a semiconductor device that effectively suppresses IR drop.

  A semiconductor device according to one aspect of the present invention includes a substrate, a semiconductor circuit, a surface protective film formed on the substrate, a power supply wiring pattern, and first and second bonding wires. The semiconductor circuit includes a plurality of functional blocks that are formed in different regions on the substrate, operate at one or a plurality of operating frequencies, and receive a common power supply voltage. The power supply wiring pattern is provided on the substrate and connected to the semiconductor circuit to supply a power supply voltage. The power supply wiring pattern is a portion where a part of the power supply wiring pattern is exposed from the surface protective film, and includes first to third pads provided apart from each other. The first pad is provided in the peripheral area of the substrate. The third pad is provided in a region where the first functional block is formed among the plurality of functional blocks. Here, the maximum operating frequency among the one or more operating frequencies of the first functional block is higher than the maximum operating frequency of at least one functional block of the remaining functional blocks. The first bonding wire is connected to the first pad in order to receive a supply voltage from the outside. The second bonding wire connects between the second and third pads.

  A semiconductor device according to another aspect of the present invention includes a substrate, a semiconductor circuit, a surface protective film formed on the substrate, a power supply wiring pattern, and first and second bonding wires. The semiconductor circuit includes a plurality of functional blocks that are formed in different regions on the substrate and receive a common power supply voltage. The power supply wiring pattern is provided on the substrate and connected to the semiconductor circuit to supply a power supply voltage. The power supply wiring pattern is a portion where a part of the power supply wiring pattern is exposed from the surface protective film, and has first to third pads provided apart from each other. The first pad is provided in the peripheral area of the substrate. The third pad is provided in a region where the first functional block of the plurality of functional blocks is formed. Here, the power consumption of the first functional block is larger than the power consumption of at least one functional block among the remaining functional blocks. The first bonding wire is connected to the first pad in order to receive a supply voltage from the outside. The second bonding wire connects between the second and third pads.

  According to one aspect of the present invention, by providing the second bonding wire in parallel with the supply path of the power supply voltage by the power supply wiring pattern, it is possible to reduce the wiring resistance and suppress the IR drop. At this time, paying attention to the operating frequency of each functional block, the power supply voltage is supplied to the functional block having the highest operating frequency higher than the other functional blocks via the second bonding wire, thereby effectively suppressing the IR drop. can do.

  According to another aspect of the present invention, attention is paid to the power consumption of each functional block. For example, the power supply voltage is supplied to the functional block having higher power consumption than the other functional blocks via the second bonding wire. Thus, IR drop can be effectively suppressed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  1 and 2 are plan views showing a configuration of a semiconductor package 1 according to an embodiment of the present invention. FIG. 1 shows a layout of the wiring pattern 31 for the power supply voltage VDD connected to the core circuit 34 of the semiconductor chip 10. FIG. 2 shows a layout of the wiring pattern 32 for the ground voltage VSS connected to the core circuit 34 for the same semiconductor chip 10 as FIG. 1 and 2, only the uppermost wiring layer of the wiring patterns 31 and 32 is shown.

FIG. 3 is a cross-sectional view schematically showing the configuration of the semiconductor package 1.
FIG. 4 is an enlarged plan view showing a part of the semiconductor chip 10 in FIGS. The semiconductor package 1 corresponds to the semiconductor device of the present invention.

  1 to 4, a semiconductor package 1 is a QFP (Quad Flat Package) using a metal lead frame. The semiconductor package 1 includes a plurality of leads 11 to 14, a power bar 15 (bus bar), a GND (ground) ring 16, and a die pad 17 as a lead frame. Furthermore, the semiconductor package 1 includes a rectangular semiconductor chip 10 fixed to the die pad 17, a plurality of bonding wires 21 to 25, and a resin 26 that seals the wire-bonded semiconductor chip 10 and the lead frame. The bonding wires 21 to 25 are connected to bonding pads 19 (also simply referred to as “pads 19”) provided in the peripheral region along the four sides 30 U, 30 D, 30 R, and 30 L of the semiconductor chip 10. As shown in FIG. 4, the bonding pads 19 are formed in the peripheral region of the semiconductor chip 10 so as to be aligned in a double rectangular frame shape. In FIG. 1 (also in FIG. 2), the inner lead portion sealed by the resin 26 is shown among the plurality of leads 11 to 14, and the outer lead portion is omitted.

  Hereinafter, as a specific example of the semiconductor circuit mounted on the semiconductor chip 10, a case of a controller for a hard disk will be described. In this case, the semiconductor chip 10 includes a digital IO circuit unit 33A, an analog IO circuit unit 33B, and a core circuit 34, which are each formed integrally on a semiconductor substrate (reference numeral 60 in FIG. 6). The digital IO circuit unit 33 </ b> A and the analog IO circuit unit 33 </ b> B are provided in the peripheral region of the substrate 60. The core circuit 34 is provided in a region inside the region where the digital IO circuit unit 33A and the analog IO circuit unit 33B are formed. The core circuit 34 is a core circuit of the semiconductor circuit and corresponds to the semiconductor circuit of the present invention.

  A plurality of electrical signals and a plurality of power supply voltages are supplied to the semiconductor chip 10 via a plurality of leads 11, 12, and 13. Leads 11 that transmit electrical signals are connected to corresponding pads provided in the peripheral region of semiconductor chip 10 by bonding wires 21. Leads 12 for supplying power supply voltage are connected to corresponding pads provided in the peripheral region of the semiconductor chip 10 by bonding wires 22. The power supply voltage supply lead 13 is connected to the power supply bar 15. The power bar 15 is connected to a plurality of pads on the semiconductor chip 10 via a plurality of bonding wires 25.

  The semiconductor chip 10 is supplied with the ground voltage VSS via the GND ring 16. The GND ring 16 is connected to a plurality of pads provided in the peripheral region of the semiconductor chip 10 by bonding wires 23 and 24. The GND ring 16 is connected to the die pad 17 via the eight connecting portions 18 and is connected to four suspension leads 14 extending from four corners of the semiconductor package outline.

  The core circuit 34 includes a plurality of functional blocks formed in different regions on the substrate. Here, the functional block means a circuit (macro) having a single function.

  As shown in FIG. 1, the semiconductor chip 10 includes a wiring pattern 31 for supplying a power supply voltage VDD to a plurality of functional blocks (functional blocks 51 to 55 described later in FIG. 5) on the substrate. The wiring pattern 31 is formed in a lattice pattern by a multilayer wiring layer and is electrically connected to each part of the core circuit 34. In FIG. 1, only the uppermost wiring layer of the wiring pattern 31 is shown, but the wiring pattern 31 is electrically connected as a whole via the lower wiring. The bonding wire 22 is connected to the pad portion in the peripheral area of the substrate in the wiring pattern 31.

  Further, in parallel with the supply path of the power supply voltage VDD by the wiring pattern 31, bonding wires 44A and 44B (also referred to as center wires 44A and 44B) are provided in the central region of the substrate. As shown in FIG. 4, the center wire 44 </ b> A is connected to the wiring pattern 31 via pads 42 </ b> A and 43 </ b> A formed in the region of the core circuit 34. Similarly, the center wire 44B is connected to the wiring pattern 31 via pads 42B and 43B formed in the region of the core circuit 34. By these center wires 44A and 44B, it is possible to suppress a decrease in the power supply voltage VDD due to the wiring resistance.

  Similarly, as shown in FIG. 2, the semiconductor chip 10 further includes a ground voltage in a region where a plurality of functional blocks (functional blocks 51 to 55 described later) to which power is supplied from the wiring pattern 31 on the substrate. A wiring pattern 32 for supplying VSS is included. The wiring pattern 32 is formed in a lattice shape by a multilayer wiring layer and is electrically connected to each part of the core circuit 34. In FIG. 2, only the uppermost wiring layer of the wiring pattern 32 is shown, but the wiring pattern 32 is electrically connected as a whole via the lower layer wiring. The bonding wire 23 is connected to the pad portion in the peripheral area of the substrate in the wiring pattern 32.

  In parallel with the path of the wiring pattern 32, bonding wires 45A and 45B (also referred to as center wires 45A and 45B) are provided in the central region of the substrate. As shown in FIG. 4, the center wire 45 </ b> A is connected to the wiring pattern 32 via pads 48 </ b> A and 49 </ b> A formed in the region of the core circuit 34. Similarly, the center wire 45B is connected to the wiring pattern 32 via pads 48B and 49B formed in the region of the core circuit 34. These center wires 45A and 45B can suppress an increase in ground voltage VSS due to wiring resistance.

  4, in addition to the pads 42A, 42B, 43A, 43B, VDD supply pads 42C, 43C are provided in the area of the core circuit 34. Further, the pads 48A, In addition to 48B, 49A, and 49B, VSS supply pads 48C and 49C are provided. In this manner, bonding pads are provided in advance at a plurality of locations in the core circuit 34 region, and the final connection location of the center wire is determined based on the electrical characteristics of the prototype semiconductor chip.

  As described above, the functions of the center wires 45A and 45B for the ground voltage VSS are the same as the functions of the center wires 44A and 44B for supplying the power supply voltage VDD. Therefore, in the following description, the center wires 44A for the power supply voltage VDD are used. 44B as a representative. In this embodiment, gold wires are used for the bonding wires 22 to 25, 44A, 44B, 45A, and 45B.

  FIG. 5 is a plan view schematically showing the configuration of the semiconductor chip 10. FIG. 5 is an enlarged view of the semiconductor chip 10 of the semiconductor package 1 of FIG.

  The core circuit 34 shown in FIG. 5 includes a plurality of functional blocks 35, 36, 51 to 55 formed in different regions. In FIG. 5, the functional blocks 35, 36, 51 to 55 are formed in a region surrounded by a dotted line.

  In this embodiment, the functional blocks 35 and 51 are a read / write channel unit (RWC unit) that performs processing suitable for reading and writing to the hard disk main body. The functional block 35 is an interface circuit for inputting / outputting data to / from the hard disk main body in the RWC unit, and an analog front end unit for processing data as an analog signal. The functional block 35 includes, for example, an A / D (Analog to Digital) conversion unit and a D / A (Digital to Analog) conversion unit. The functional block 51 encodes a digital signal when writing to the hard disk, sends the processed digital signal to the functional block 35, and receives a digital signal from the functional block 35 when reading and performs a decoding process thereof. is there.

  The functional blocks 36 and 53 are communication control units that control serial ATA (Advanced Technology Attachment) with the central processing unit of the computer. The functional block 36 is an interface circuit with a computer, and is an analog front end unit that processes communication data as an analog differential signal. The functional block 36 also has an A / D converter and a D / A converter. The functional block 53 is a digital back end unit that performs serial ATA digital processing. The functional block 52 is a memory control unit that controls storage of data in a memory (dynamic RAM, static RAM, etc.) connected to the semiconductor package. The functional blocks 54 and 55 are hard disk controllers that control the read / write channel section and the serial ATA. For example, the function block 55 is a 16-bit or 32-bit general-purpose microcontroller unit (MCU unit) that operates according to a program. The functional block 54 is a dedicated logic circuit unit.

  The functional blocks 51 to 55 operate by receiving a common power supply voltage VDD from a common power supply wiring (wiring pattern 31) in the chip. The function blocks 35 and 36 operate by receiving a power supply voltage from a power supply wiring in a chip separate from the function blocks 51 to 55. The power supply wiring between the functional blocks 35 and 36 is separate. The analog IO circuit unit 33B is input to an input buffer circuit, an output buffer circuit (and / or an input / output buffer circuit) for inputting and outputting signals between the functional blocks 35 and 36 and the outside of the semiconductor chip, and a pad. Includes an electrostatic protection circuit for surge protection. The digital IO circuit unit 33A includes an input buffer circuit, an output buffer circuit (and / or an input / output buffer circuit) for inputting and outputting signals between the functional blocks 51 to 55 of the core circuit 34 and the outside of the semiconductor chip, and pads. Including an electrostatic protection circuit for surge protection. The analog IO circuit unit 33B and the digital IO circuit unit 33A operate by receiving a power supply voltage from a power supply wiring in a chip separate from the functional blocks 35, 36, and 51-55. In-chip power supply wiring between the analog IO circuit unit 33B and the digital IO circuit unit 33A is also separate. In FIG. 1 and FIG. 5, the power supply wiring patterns in the chip that supply the power supply voltage to the functional blocks 35 and 36, the digital IO circuit portion, and the analog IO circuit portion are not shown.

  Each functional block 35, 36, 51-55 operates at one or more operating frequencies. Therefore, a basic clock signal is supplied from the outside to the semiconductor circuit via the bonding wire 21, and a clock signal necessary for the operation of each functional block is generated in the semiconductor circuit.

  In the case of a hard disk controller shown as an example in this embodiment, the highest operating frequency is 1.7 GHz and is used in the function block 51. In the other functional blocks 35, 36, 52 to 55, a clock signal of 166 to 300 MHz is used. As described above, since the functional block 51 includes a circuit portion that operates at high speed, its power consumption is the highest, and consumes about 80% of the entire power consumption of the semiconductor chip 10.

  In consideration of IR drop, a function block with high power consumption can receive a predetermined power supply voltage VDD with a voltage drop as small as possible, and the power supply voltage among the pads 19 provided in the peripheral region of the semiconductor chip 10 is as follows. It is preferable to be provided in the vicinity of the pad 41 for supplying VDD. Specifically, in the case of FIG. 5, the functional block 51 is provided in the vicinity of the peripheral region of the left side 30L of the semiconductor chip 10 and receives the supply of the power supply voltage VDD from the pad 41 formed in the peripheral region of the left side 30L.

  FIG. 6 is a diagram schematically showing a part of the cross-sectional structure of the semiconductor chip 10. Hereinafter, the configuration of the wiring pattern 31 of the semiconductor chip 10 will be described in more detail with reference to FIGS. 5 and 6.

  As already described, the wiring pattern 31 is constituted by a grid-like multilayer wiring, and in the case of FIG. 6, includes wiring layers 31A and 31B. The uppermost wiring layer 31A and the wiring layer 31B formed thereunder via the interlayer insulating layer 62 are connected via the metal layer 31C formed in the contact hole. The uppermost wiring layer is made of aluminum, and the lower wiring layer is made of copper. FIG. 5 described above shows only the uppermost wiring layer 31 </ b> A among the wiring patterns 31.

  Further, the wiring pattern 31 has bonding pads 41, 42 (42A, 42B), 43 (43A, 43B), which are portions where a part of the uppermost wiring layer 31A is exposed from the surface protective film 61. Among these, a plurality of pads 41 are provided in the peripheral regions of the respective sides 30U, 30D, 30R, and 30L of the semiconductor chip 10, and are supplied with the power supply voltage VDD from the leads 12 through the bonding wires 22, respectively.

  The pad 42A is provided in the vicinity of the pad 41 formed in the peripheral region of the upper side 30U of the semiconductor chip 10. That is, the pad 42 </ b> A is provided at a position close to the pad 41 on the wiring extending from the pad 41 to the inside of the substrate 60 in the wiring pattern 31. The pad 42A is connected to the pad 43A provided in the functional block 51 of the core circuit 34 via the center wire 44A. At this time, the distance between the pad 42A and the pad 41 on the upper side 30U closest to the pad 42A (the linear distance, that is, the length of the line segment) is shorter than the distance between the pad 42A and the pad 43A. The distance between the upper side 30U and the pad 42A (the length of the perpendicular) is the shortest of the distances between the four sides of the substrate 60 and the pad 42A, and the distance between the pad 42A and the upper side 30U is the same as that of the pad 43A. It is shorter than the distance with the upper side 30U.

  Similarly, the pad 42B is provided in the vicinity of the pad 41 provided in the peripheral region of the lower side 30D of the semiconductor chip 10. That is, the pad 42 </ b> B is provided at a position close to the pad 41 on the wiring extending from the pad 41 to the inside of the substrate 60 in the wiring pattern 31. The pad 42B is connected to the pad 43B provided in the functional block 51 of the core circuit 34 via the center wire 44B. At this time, the distance between the pad 42B and the pad 41 on the lower side 30D closest to the pad 42B is shorter than the distance between the pad 42B and the pad 43B. The distance between the lower side 30D and the pad 42B is the shortest of the distances between the four sides of the substrate 60 and the pad 42B, and the distance between the pad 42B and the lower side 30D is greater than the distance between the pad 43B and the lower side 30D. Also short.

  The pad 41 corresponds to the first pad of the present invention, the pad 42 (42A, 42B) corresponds to the second pad of the present invention, and the pad 43 (43A, 43B) corresponds to the third pad of the present invention. Corresponds to the pad.

  Here, as shown in FIG. 6, the center wire 44 (44A, 44B) is ball-bonded to the pad 42 (42A, 42B) and stitch-bonded to the bump 47 provided on the pad 43 (43A, 43B). . This is because in the case of stitch bonding, it is necessary to increase the contact area between the bump 47 and the center wire 44 in order to increase the bonding strength, and thus it is necessary to increase the pad area. Compared with the pad 42, the pad 43 is arranged on the inner side of the substrate 60, so that the area can be easily increased. For this reason, the pad 43 (43A, 43B) provided near the center of the semiconductor chip 10 is stitch-joined.

  In the ball bonding, the tip of the gold wire is melted to form the ball 46 and then bonded to the pad 42. Thereafter, a loop is formed by reversely operating the capillary of the bonder. A predetermined interval is provided between the pad 41 and the pad 42 so that the capillary and the bonding wire 22 do not interfere when the loop is formed.

  FIG. 6 further shows multilayer wiring layers 64 and 65 for transmitting a data signal to the core circuit 34. The wiring layer 64 and the wiring layer 65 are connected through a contact hole 66 that penetrates the interlayer insulating layer 63. The wiring layers 64 and 65 are electrically connected to the outside of the semiconductor chip 10 via the lead 11 and the bonding wire 21 of FIG.

  Next, the reason why the pads 43A and 43B are arranged in the functional block 51 having the highest maximum operating frequency in the core circuit 34 as shown in FIG.

  7 and 8 are diagrams showing IR drop simulation results in the functional blocks 51 to 55 of the core circuit 34 of the semiconductor chip 10 of FIG. FIG. 7 is a simulation result of a comparative example when the center wires 44A and 44B are not provided, and FIG. 8 is a simulation result when the center wires 44A and 44B are provided.

  The simulations of FIGS. 7 and 8 are for the case where an ideal power supply of 0.9 V as the power supply voltage VDD is connected to the plurality of pads 41 in the peripheral region of the semiconductor chip 10 of FIG. In these simulations, the voltage of each part of the wiring pattern 31 when the power supply voltage VDD is supplied from the plurality of pads 41 to the functional blocks 51 to 55 via the grid-like wiring pattern 31 is calculated.

  According to the simulation result shown in FIG. 7, the region having the largest voltage drop among the functional blocks 51 to 55 is the region farthest from the plurality of pads 41 in the peripheral region of the semiconductor chip 10 (providing the functional block 53 in FIG. 5). Area). The power supply voltage VDD at the point where the voltage drop is the largest is 0.868V, and a voltage drop of 32 mV occurs.

  Further, as shown in FIG. 7, the voltage drop in the region on the left side 30L side from the vicinity of the center of the semiconductor chip 10 provided with the functional block 53 is larger than in other regions. This is because the functional block 51 having the highest operating frequency and thus the highest power consumption is provided in the region on the left side 30L side of the semiconductor chip. Accordingly, the amount of current supplied from the plurality of pads 41 in the peripheral region of the left side 30L to the vicinity of the center increases, so that the voltage drop of the power supply voltage VDD increases.

  On the other hand, in FIG. 8, the pads 43A and 43B provided in the area of the functional block 51 with the largest power consumption and the pads 42A and 42B provided close to the peripheral area of the substrate are connected by the center wires 44A and 44B, respectively. It is a simulation result in the case of being performed.

  Comparing the simulation result of FIG. 8 with the simulation result of FIG. 7, it can be seen that the IR drop of the entire functional blocks 51 to 55 is improved in FIG. As a result, the voltage drop in the region where the voltage drop is the largest in FIG. 7 (the region where the functional block 53 is provided) is also small. Specifically, in the case of FIG. 8, the power supply voltage VDD at the point where the voltage drop is the largest is 0.872 V, and the magnitude of the voltage drop is 28 mV, which is improved from 32 mV in the case of FIG.

  Here, it is assumed that the pads 43A and 43B are not the region where the power consumption is the largest (the region where the functional block 51 is formed) but the region near the center of the semiconductor chip 10 where the IR drop is the largest (the functional block 53 is formed). It is assumed that it is provided in the area. In the simulation result in this case, although the IR drop near the center of the substrate is improved, the IR drop in the region closer to the left side 30L of the substrate than the pads 43A and 43B is deteriorated.

  Therefore, it is preferable to provide the pads 43A and 43B in the area of the functional block 51 with the largest power consumption. As a result, the drop of the power supply voltage VDD in the area of the functional block 51 is suppressed, so that the IR drop of the entire functional blocks 51 to 55 is improved. Furthermore, as shown in FIG. 5, when the functional block 51 is arranged on the left side 30L side of the semiconductor chip 10, a decrease in the power supply voltage VDD near the center of the substrate, which is a region farther from the pad 41, is also suppressed. It will be.

  Next, the reason why the pads 42A and 42B are provided in the vicinity of the pads 41 on the upper side 30U and the lower side 30D of the semiconductor chip 10 will be described with reference to FIG. 5 again.

  The first reason is to suppress the electro-migration (EM) by dispersing the current flowing through the power supply wiring pattern 31. Among the functional blocks 51 to 55, the power consumption of the functional block 51 arranged close to the peripheral area of the left side 30L is the largest. For this reason, the amount of current flowing into the core circuit 34 from the pad 41 provided in the peripheral region of the left side 30L via the power supply wiring is supplied from the pad 41 provided in the peripheral region of the other sides 30U, 30D, and 30R. It becomes larger than the amount of current flowing into the functional blocks 51 to 55 via the wiring. In particular, the current density of the power supply wiring layer near the pad 41 on the left side 30L becomes a problem.

  Therefore, as shown in FIG. 5, pads 42A and 42B are provided in the vicinity of the pads 41 on the upper side 30U and the lower side 30D with sufficient current density, and the center wires 44A and 42B are provided between the pads 42A and 42B and the pads 43A and 43B. 44B, respectively. Accordingly, the amount of current flowing from the pad 41 on the upper side 30U and the lower side 30D into the functional block 51 can be increased, and the amount of current flowing from the pad 41 on the left side 30L into the functional block 51 can be decreased. As a result, current concentration in the power supply wiring layer near the pad 41 on the left side 30L can be reduced.

  Note that it is preferable to provide the pads 42A and 42B close to the pad 41 in the peripheral region of the substrate on the upper side 30U and the lower side 30D because the effect of reducing the wiring resistance is great.

  The second reason is to prevent the power supply voltage VDD supplied to the pad 41 provided in the peripheral region of the left side 30L of the semiconductor chip 10 from being lowered. When the center wires 44A and 44B are not provided, as described above, the amount of current flowing from the pad 41 provided in the peripheral region of the left side 30L to the functional blocks 51 to 55 is the peripheral amount of the other sides 30U, 30D, and 30R. It becomes larger than the amount of current flowing into the functional blocks 51 to 55 from the pad 41 provided in the region. For this reason, the current flowing through the bonding wire 22 of FIG. 1 electrically connected to the pad 41 on the left side 30L, the lead 12, and the solder connection portion between the lead 12 and the printed circuit board (not shown) is also applied to the pad 41 on the other side. It will be larger than the current flowing through these parts. As a result, the voltage of the pad 41 on the left side 30L may be lower than the voltage of the other pads 41. Therefore, the center wires 44A and 44B are provided to equalize the current amount, thereby preventing the power supply voltage VDD supplied to the pad 41 on the left side 30L from being lowered.

  For these reasons, the pads 42A and 42B are arranged so as to avoid the vicinity of the region sandwiched between the region where the functional block 51 is formed and the left side 30L of the semiconductor chip 10. In the case of FIG. 5, the pads 42A and 42B are provided in the vicinity of the pad 41 formed in the peripheral region of the upper side 30U and the lower side 30D of the semiconductor chip 10, respectively, but one of the pads 42A and 42B is provided. May be provided in the vicinity of the pad 41 on the right side 30R.

  As described above, according to the semiconductor package 1 of this embodiment, IR drops can be efficiently suppressed by effectively arranging the center wires 44A and 44B. Furthermore, it becomes possible to suppress electromigration.

  Here, depending on the layout of the power supply wiring pattern 31, the pads 42A and 42B may be provided outside the region where the functional blocks 51 to 55 are formed. That is, the pads 42 </ b> A and 42 </ b> B may be provided on the power supply wiring on the way from the pad 41 to the region where the core circuit 34 is formed in the power supply wiring pattern 31.

  The pads 43A and 43B have the greatest IR drop suppression effect when formed in a functional block with the maximum operating frequency or a functional block with the maximum power consumption, but need not necessarily be provided in the maximum region. IR drop suppression can also be expected by providing the pads 43A and 43B in the area of a functional block having a higher maximum operating frequency or a functional block having higher power consumption than other functional blocks.

  Further, it is assumed that the maximum operating frequency of the first functional block is higher than the maximum operating frequency of the second functional block, and therefore the power consumption of the first functional block is larger than the power consumption of the second functional block. . In such a case, the pad 43 (43A, 43B) is disposed in the region where the first functional block is formed, and the pad 42 (42A, 42B) is disposed in the region where the second functional block is formed. Further, the effect of suppressing the IR drop in the first functional block region can also be expected by connecting the two pads with the center wires 44A and 44B.

  In the above embodiment, the QFP using the lead frame has been described. However, the form of the semiconductor package is not limited to the lead frame QFP. The present invention can also be applied to, for example, a BGA (Ball Grid Array) package.

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a plan view showing a configuration of a semiconductor package 1 according to an embodiment of the present invention (a layout of a wiring pattern 31 for a power supply voltage VDD). 1 is a plan view showing a configuration of a semiconductor package 1 according to an embodiment of the present invention (a layout of a wiring pattern 32 for a ground voltage VSS). 1 is a cross-sectional view schematically showing a configuration of a semiconductor package 1. FIG. 3 is an enlarged plan view showing a portion of a semiconductor chip 10 in FIGS. 1 and 2. 1 is a plan view schematically showing a configuration of a semiconductor chip 10. 1 is a diagram schematically showing a part of a cross-sectional structure of a semiconductor chip 10. It is a figure which shows the simulation result of IR drop in the functional blocks 51-55 of the semiconductor chip 10 of FIG. 5 (when the center wires 44A and 44B are not provided). It is a figure which shows the simulation result of IR drop in the functional blocks 51-55 of the semiconductor chip 10 of FIG. 5 (when center wires 44A and 44B are provided).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor package, 10 Semiconductor chip, 11-14 Lead, 15 Power supply bar, 16 GND ring, 17 Die pad, 21-25 Bonding wire, 31, 32 Wiring pattern, 34 Core circuit, 41 Bonding pad (1st pad), 42A, 42B, 48A, 48B Bonding pad (second pad), 43A, 43B, 49A, 49B Bonding pad (third pad), 44A, 44B, 45A, 45B Bonding wire, 46 balls, 47 bumps, 35, 36,51-55 functional block, 60 semiconductor substrate, 61 surface protective film.

Claims (6)

A semiconductor device,
A rectangular substrate;
An IO circuit formed in a peripheral region on the substrate;
A core circuit including a plurality of functional blocks formed in a region surrounded by the peripheral region on the substrate;
The plurality of functional blocks are formed in different regions, each operating at one or more operating frequencies, receiving a common power supply voltage ,
The plurality of functional blocks are:
A first functional block formed adjacent to a peripheral region along the first side of the substrate;
It is formed adjacent to a peripheral region along the second side of the substrate different from the first side of the substrate, and is higher than the maximum operating frequency of one or more operating frequencies of the first functional block. A second functional block having a low maximum operating frequency,
The semiconductor device further includes:
A surface protective film formed on the substrate;
A power supply wiring pattern provided on the substrate and connected to the plurality of functional blocks to supply the power supply voltage;
The power supply wiring pattern includes a plurality of first pads, second pads, and third pads that are portions of the power supply wiring pattern that are exposed from the surface protective film and are spaced apart from each other. Including
The plurality of first pads are provided in a peripheral region along at least the first side and the second side among the four sides of the substrate,
It said third pad is pre SL provided on the first functional block is formed region,
The second pad is provided in a region where the second functional block is formed, or a peripheral region between the region where the second functional block is formed and the second side of the substrate,
The semiconductor device further includes:
A first bonding wire connected to the first pad to receive the supply voltage from outside;
A semiconductor device comprising: a second bonding wire that connects the second and third pads. The maximum operating frequency of the first functional block is the maximum among one or more of the operating frequency of each of the plurality of functional blocks, the semiconductor device according to claim 1. A semiconductor device,
A rectangular substrate;
An IO circuit formed in a peripheral region on the substrate;
A core circuit including a plurality of functional blocks formed in a region surrounded by the peripheral region on the substrate;
The plurality of functional blocks are formed in different regions on the substrate, receive a common power supply voltage ,
The plurality of functional blocks are:
A first functional block formed adjacent to a peripheral region along the first side of the substrate;
A second functional block formed adjacent to a peripheral region along the second side of the substrate different from the first side of the substrate, and having lower power consumption than the first functional block;
The semiconductor device further includes:
A surface protective film formed on the substrate;
A power supply wiring pattern provided on the substrate and connected to the plurality of functional blocks to supply the power supply voltage;
The power supply wiring pattern includes a plurality of first pads, second pads, and third pads that are portions of the power supply wiring pattern that are exposed from the surface protective film and are spaced apart from each other. Including
The plurality of first pads are provided in a peripheral region along at least the first side and the second side among the four sides of the substrate,
It said third pad is pre SL provided on the first functional block is formed region,
The second pad is provided in a region where the second functional block is formed, or a peripheral region between the region where the second functional block is formed and the second side of the substrate,
The semiconductor device further includes:
A first bonding wire connected to the first pad to receive the supply voltage from outside;
A semiconductor device comprising: a second bonding wire that connects the second and third pads. 4. The semiconductor device according to claim 3 , wherein power consumption of the first functional block is maximum among power consumption of each of the plurality of functional blocks. Before Symbol distance between the first pad provided on the peripheral region along said second side of said substrate and the second pad, than a distance between said second pad and the third pad short semiconductor device according to any one of claims 1-4. The semiconductor device according to claim 5 , wherein the second bonding wire is ball-bonded to the second pad and stitch-bonded to the third pad.

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