JP2005326976A - Cad system for electronic circuit board, computer program, and manufacturing method for electronic circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CAD system for an electronic circuit board capable of merging vias, and capable of connecting efficiently those to a through hole conductor, as to the via and the through hole conductor constituting a conductive path for an electric power source and for the ground. <P>SOLUTION: This CAD system has an integration via generating means for connecting the same kind of a via pattern and a through hole conductor pattern, by projecting a via integrated wiring pattern and a through hole conductor integrated wiring pattern onto an intermediate layer corresponding to a dielectric layer sandwiched by a wiring layer corresponding to the first wiring layer and a wiring layer corresponding to the second wiring layer, after wiring construction processing, and by generating the via pattern for integration in an intersection of the via integrated wiring pattern with the through hole conductor integrated wiring pattern, of which the projected patterns are the same kind. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic circuit board CAD system, a computer program used therefor, and an electronic circuit board manufacturing method.

  Semiconductor chips such as ICs and microprocessors have been rapidly integrated in recent years, so that the number of terminals at the input / output section of the chip is also increasing significantly. In response, electronic circuit boards for connecting such chips are also rapidly increasing in the number of wiring parts, and multilayer wiring parts are formed through dielectric layers such as polymer materials and ceramics. The number of mold package substrates is increasing. Recently, in order to efficiently design such an electronic circuit board, a so-called CAD (Computer Aided Design) system using a computer drawing process has been used (Patent Document 1). This is done by opening a drawing screen on the display device, and connecting the wiring elements, the surface conductor pattern for grounding or power supply, vias connecting wiring parts of different layers, or board elements such as pads and lands forming wiring terminal parts. As a CAD data, a board design drawing is obtained by drawing on a drawing layer using an input device such as a mouse.

  When two types of conduction paths for the power supply and ground of the electronic circuit board are designed using such a CAD system, the arrangement of input / output terminals of chips mounted on the electronic circuit board is predetermined. Based on these arrangements, the power supply and ground pads and vias in the electronic circuit board are designed, and wirings, through-holes and the like that are connected to these are designed. These conductive paths are formed at least at the pad portion on the chip mounting side of the electronic circuit board corresponding to the input / output terminals of the chip, and are well-known ball grid arrays (BGA) and pins formed on the back side from the pad portion. It is only necessary to form a conduction path that is electrically connected to a connection terminal portion such as a grid array (PGA). Therefore, the number, arrangement position, and shape of vias and through-holes are very small, including standards related to crosstalk. As long as the standard is satisfied, there are no particular restrictions, and it is often designed semi-manually according to established design rules.

JP 2000-276505 A

  However, with the recent trend toward higher integration and multifunctionality of semiconductor chips and the increase in the number of terminals forming the input / output portion of the chip, it has become necessary to supply a stable power supply voltage to an electronic circuit board. It was. For this reason, when forming the conduction path of the substrate, for example, as many vias and through-hole conductors as possible are arranged and integrated so that the same type of these vias and through-holes are conducted inside the substrate. Designed to let you. However, since the vias are formed based on the rows of the chip terminals, the arrangement positions are predetermined, and the number of through-hole conductors is limited by the size of the diameter, and the number of vias is greater than that of the vias. There are few. In this case, it is necessary to connect a large number of vias to the through-hole conductors while integrating the wirings with the wiring. However, designing such wiring requires a complicated wiring layout design.

  The present invention has been made in view of the above-mentioned problems, and regarding vias and through-hole conductors constituting power supply and ground conduction paths, the vias are efficiently merged, and these and the through-hole conductors are efficiently combined. CAD system for electronic circuit boards that can be connected to a computer, a computer program for realizing the functions of the CAD system on a computer, and a method of manufacturing an electronic circuit board using the CAD system for electronic circuit boards And to provide.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, a CAD system for an electronic circuit board according to the present invention includes:
On the first main surface on which the electronic component is mounted, a pad array for power supply and ground arranged corresponding to the arrangement of terminals of the electronic component,
Immediately below the pad array, a first type via array that conducts to one of the power supply and ground pad arrays and a second type via array that conducts to the other are arranged corresponding to the arrangement of the pad array. A core substrate on which a dielectric layer in which a via array is formed, a first type through-hole conductor conducting to the first type via array, and a second type through-hole conductor conducting to the second type via array; A CAD system for designing an electronic circuit board having a kind of via array, the first kind of through-hole conductor, and a wiring layer connecting the second kind of via array and the second kind of through-hole conductor,
Via drawing means for drawing the first type via graphic and the second type via graphic forming the via array on a via layer;
Through-hole conductor drawing means for drawing the first-type through-hole conductor figure and the second-type through-hole conductor figure, which are fewer than the via figure, on the through-hole conductor layer;
A wiring drawing means that integrates a plurality of via figures of the same type and draws a wiring figure that is electrically connected to the corresponding through-hole conductor figure on a wiring layer,
A first type via integrated wiring figure that integrates a plurality of the first type via figures and a second type via integrated wiring figure that integrates the plurality of second type via figures are drawn on the first wiring layer, The first type through-hole conductor integrated wiring graphic that integrates the first type through-hole conductor graphic, and the second type through-hole conductor integrated wiring graphic that integrates a plurality of the second type through-hole conductor graphic. Wiring drawing means for performing wiring drawing processing to be drawn on,
After the wiring drawing process, the via integrated wiring pattern and the through-hole are formed in an intermediate layer corresponding to a dielectric layer sandwiched between a wiring layer corresponding to the first wiring layer and a wiring layer corresponding to the second wiring layer. The hole conductor integrated wiring figure is projected, and by generating an integration via figure at the intersection of the projected same type of via integrated wiring figure and the through-hole conductor integrated wiring figure, the same kind of via figure and the It has an integrated via generation means for connecting the through hole conductor figure.

  In this CAD system, in order to design two kinds of conduction paths for power supply voltage supply (for power supply) and grounding (for ground) formed in a region immediately below an electronic component mounted on an electronic circuit board, Based on the terminal arrangement of the input / output terminals of the electronic components to be mounted on the circuit board, various figures corresponding to the power supply and ground pad arrays, via arrays, wirings, and through-hole conductors (through-hole conductors) It is possible to design by drawing on each drawing layer. In particular, in designing vias connected to pad conductors and through-hole conductors formed in the core substrate, first, via integrated wiring figures that integrate the same type of vias (first type vias that integrate first type via figures). A second-type via integrated wiring figure that integrates the integrated wiring figure and the second-type via figure) is designed on the first wiring layer. Next, the through hole conductor integrated wiring pattern that integrates the same type of through hole conductor (the first type through hole conductor integrated wiring pattern that integrates the first type through hole conductor graphic and the second type through hole conductor graphic that integrates the second type through hole conductor graphic) Drawing design of the through-hole conductor integrated wiring pattern) on the second wiring layer. After these wiring drawing processes, these integrated wiring figures are projected and projected onto an intermediate layer corresponding to a dielectric layer sandwiched between two wiring layers corresponding to the first wiring layer and the second wiring layer. The integration via is drawn and designed at the intersection of the same type of the intersection of the via integrated wiring pattern and the through-hole conductor integrated wiring pattern. It is possible to connect to the through-hole conductor of the core substrate while integrating the via connected to the pad conductor. Moreover, these can be easily performed only by calculating the intersection by a CAD system program.

In the CAD system for an electronic circuit board of the present invention,
The via drawing means alternately arranges the first-type via graphic and the second-type via graphic on a lattice arrangement having lattice points at intersections of two intersecting parallel lines on the via layer. Yes,
The through-hole conductor drawing means includes the first-type through-hole conductor figure and the second-type through-hole conductor on a lattice arrangement having lattice points at intersections of two intersecting parallel lines on the through-hole conductor layer. The figure may be arranged alternately.

  As described above, the via pattern and the through-hole conductor pattern (through-hole conductor pattern) are regularly arranged in a lattice shape, thereby facilitating the design of the integrated wiring pattern. In this case, as shown in FIGS. 12A and 12B, via figures are arranged in a lattice pattern, and different types of via figures are alternately arranged. In addition, the through hole conductor figure is also in a lattice shape, and figures of different types can be alternately arranged. As a result, the through-hole conductors can be arranged in a balanced manner in a lattice pattern in the substrate, and a stable power supply can be performed without forming a local electric field in the substrate. When drawing via graphics or through-hole conductor graphics, drawing between different types (for power supply and ground) with a predetermined width in consideration of the influence of crosstalk and the like. There is a need. Further, it is desirable that the through-hole conductors are drawn so as to be arranged as many as possible in the core substrate.

  Also, in the CAD system for an electronic circuit board according to the present invention, the wiring drawing means includes a plurality of parallel first-type via integrated wiring figures that linearly connect the first-type via figures, and the second-type via figures. A plurality of parallel second-type via integrated wiring figures that connect the first-type through-hole conductor figures in a straight line, and a plurality of parallel first-type through-holes that connect the first-type through-hole conductor figures in a straight line. A hole conductor integrated wiring pattern and a plurality of parallel second type through hole conductor integrated wiring patterns that linearly connect the second type through hole conductor pattern may be drawn on the first wiring layer. .

  Via figures and through-hole conductor figures (through-hole conductor figures) arranged in a grid are formed by a parallel wiring group in which a plurality of linear wiring figures (via integrated wiring figures and through-hole conductor integrated wiring figures) are arranged in parallel. The same kind of vias and the same kind of through-hole conductor figures can be integrated. As long as the via arrangement rules are clear, it is easy to draw a linear integrated wiring pattern, and the intersection of the via integrated wiring pattern projected on the intermediate layer and the through-hole conductor integrated wiring pattern Calculation is also very easy. These intersections can also be arranged in the same way because the via figure and the through-hole conductor figure are arranged in a grid pattern, and therefore the integrated vias to be drawn are also arranged in the entire dielectric layer. Arranged.

  The computer program according to the present invention is installed in a computer to cause the computer to function as each means constituting the CAD system for an electronic circuit board according to the present invention. Thereby, the CAD system of the present invention can be easily realized on a computer. The computer program is recorded on a computer-readable recording medium such as an optical recording medium (CD-ROM, DVD, etc.) or a magneto-optical recording medium (MO, etc.), and is read by a dedicated reader. The program can be installed on a fixed storage device (for example, a hard disk drive) provided on the computer side, or the whole or a part of the program can be downloaded from a host computer through an electric communication line such as the Internet. Can be installed.

  The method for manufacturing an electronic circuit board according to the present invention uses the CAD system for an electronic circuit board according to the present invention to design a power supply or ground conductive path formed on the electronic circuit board to be obtained. As the graphic data, the via layer, the through-hole conductor layer, the wiring layer corresponding to each of the via figure, the through-hole conductor figure, the wiring figure, and the integration via figure that are substrate elements constituting And an electronic circuit board design process for drawing these figures drawn on the intermediate layer and correcting these figures as necessary, and the graphic data of the electronic circuit board obtained by the board element design process. And an electronic circuit board manufacturing process for manufacturing the board element of the electronic circuit board. According to this, in the electronic circuit board design process, efficient board element design can be performed.

  Hereinafter, embodiments of the present invention will be described with reference to examples shown in the drawings. FIG. 1 is a block diagram showing the overall configuration of an embodiment of an electronic circuit board CAD system 100 (hereinafter also simply referred to as a CAD system) according to the present invention. The CAD system 100 includes a computer main body 112 including a CPU 103, a ROM 104, a RAM 105, an input / output interface 102, and the like. As peripheral devices, input means such as a keyboard 106 or a mouse 107, a CD-ROM drive 108, or a floppy disk drive. The whole is constructed as a computer system to which recording medium reading means such as 109, a hard disk drive (hereinafter referred to as HDD) 110, a monitor 113 connected via a monitor control unit 111, a printer 114, and the like are connected.

  Note that the CPU 103 has main components such as a drawing layer setting unit, a via drawing unit, a wiring drawing unit, and a through hole conductor drawing unit for setting various layers (via layer, wiring layer, through hole conductor layer, etc.) on which a figure is drawn and inputted. It is what you make. The keyboard 106 or the mouse 107, together with the CPU 103, is a main body of via drawing means, wiring drawing means, and through-hole conductor drawing means. The input / output interface 102 functions together with the CPU 103 as a drawing output means for printing out a design drawing of the electronic circuit board that has been drawn.

  The HDD 110 stores an operating system program (hereinafter referred to as OS) 161 and an application program (hereinafter referred to as application) 162. The application 162 is a computer program for realizing the functions of the CAD system 100, and operates on the OS 161 in the form of using the application work memory 152 as a work area. This is stored in a computer-readable state on, for example, the CD-ROM 120 and installed in a predetermined storage area on the HDD 110. On the other hand, the RAM 105 is provided with a work memory 151 of the OS 161 and a work memory 152 of an application.

  The present invention draws and designs a power supply voltage conduction path and a ground voltage conduction path formed on an electronic circuit board by the CAD system 100, and FIG. 1 shows a cross-sectional structure of a region in which conductive paths for power supply and ground are formed in a substrate (note that the electronic circuit substrate 1 is configured as an organic substrate, but the present invention is not limited to this). It can also be applied to ceramic substrates). Hereinafter, the structure of the electronic circuit board 1 of FIG. 2 will be described.

  2 is a plate-shaped core material (core substrate) made of a heat-resistant resin plate (for example, bismaleimide-triazine resin plate) or a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin). The core conductor layers M1 and M11 are respectively formed in a predetermined pattern on both surfaces of 2. The core conductor layers M1 and M11 are formed as a plane conductor pattern that covers most of the surface of the core material 2. On the other hand, a through hole 12 drilled by a drill or the like is formed in the core material 2, and a power supply through for electrically connecting first conductor layers (hereinafter also referred to as core conductor layers) M <b> 1 and M <b> 11 to the inner wall surface thereof. A hole conductor 30a and a ground through-hole conductor 30b are formed. The through hole 12 is filled with a resin filling material 31 such as an epoxy resin.

  Further, first dielectric layers V1 and V11 made of the photosensitive resin composition 3 are formed on the upper layers of the first conductor layers (core conductor layers) M1 and M11, respectively, and different conductor layers are formed therein. A power supply via 34a and a ground via 34b are formed. Further, first wiring conductor layers M2 and M12 having a ground wiring portion 7b are formed on the surface by Cu plating. The first conductor layers (core conductor layers) M1 and M11 and the second conductor layers (hereinafter also referred to as first wiring conductor layers) M2 and M12 are connected to each other by ground vias 34b. Second dielectric layers V2 and V12 using the photosensitive resin composition 3 are formed on the upper layers of the second conductor layers (first wiring conductor layers) M2 and M12, and different conductor layers are connected to the inside thereof. A power supply via 34a and a ground via 34b are formed. On the surface, third conductor layers (hereinafter also referred to as second wiring conductor layers) M3 and M13 are formed by Cu plating, respectively. The second conductor layers (first wiring conductor layers) M2 and M12 and the third conductor layers (second wiring conductor layers) M3 and M13 are not connected to each other, and the first conductor layer (core conductor layer). M1 and M11 and third conductor layers (second wiring conductor layers) M3 and M13 are connected to each other through power supply vias 34a. Upper layers of the third conductor layers (second wiring conductor layers) M3 and M13 are formed with third dielectric layers V3 and V13 using the photosensitive resin composition 3, respectively, and different conductor layers are formed inside the layers. A power supply via 34a and a ground via 34b to be connected are formed. On the surface, fourth conductor layers (hereinafter also referred to as third wiring conductor layers) M4 and M14 are formed by Cu plating, respectively. The third conductor layers (second wiring conductor layers) M3 and M13 and the fourth conductor layers (third wiring conductor layers) M4 and M14 are connected to each other by power supply vias 34a. (First wiring conductor layer) M2 and M12 and fourth conductor layers M4 and M14 are connected to each other by ground vias 34b.

  A surface wiring conductor layer M4 is formed on the third dielectric layer V3 on the first main surface side of the core material 2, and a plurality of solder lands 10a and 10b are provided thereon.

  On the other hand, a back surface wiring conductor layer M14 is formed on the third dielectric layer V13 on the second main surface side of the core material 2. The back surface wiring conductor layer M13 has a plurality of lands 20a and 20b for connecting the substrate 1 to a main substrate such as a motherboard in a known connection form such as a ball grid array (BGA) or a pin grid array (PGA). Is formed. Solder resist layers 8 and 18 (SR1, SR11) made of a photosensitive resin composition are formed on the front surface wiring conductor layer M3 and the back surface wiring conductor layer M13, respectively. In order to expose the solder lands 10a and 10b, the solder resist layer 8 on the surface side is formed with openings corresponding to the solder lands 10a and 10b in a one-to-one correspondence. Solder bumps 11a and 11b are arranged so as to be electrically connected to 10b.

  A chip capacitor (hereinafter also referred to as C / C) 200 is mounted on the first main surface of the electronic circuit board of FIG. The chip capacitor 200 is a decoupling capacitor and is provided between the power supply conduction path and the ground conduction path. Thereby, malfunction of the circuit element due to switching noise and crosstalk noise generated inside the electronic component (chip) 300 is suppressed. The chip capacitor 200 of the present embodiment is connected to a power supply conduction path formed immediately below the electronic component in a region not shown. A capacitor (not shown) is connected to the ground conduction path.

  Even in the region immediately below the capacitor 200, as in the region directly below the electronic component, depending on the power supply substrate elements such as the wiring 7a, the via 34a, the through hole 30a, the land 20a, the solder land 10a, and the solder bump 11a, A conduction path is formed. In the case of a capacitor connected to a ground conduction path, the conduction path is formed by a ground substrate element.

  These lands 20a, vias 34a, through-hole conductors 30a, solder lands 10a, and solder bumps 11a form a conduction path A for supplying a power supply voltage. The power supply voltage supply conduction path is a conduction path from the land 20a to the solder bump 11a, and is integrated by the wiring part 7a on the first main surface side of the core material 2 which is an intermediate part thereof. Yes. Further, the land 20b, the via 34b, the through-hole conductor 30b, the solder land 10b, and the solder bump 11b form a conduction path B for ground, and on the first main surface side of the core material 2 that is an intermediate portion thereof. The whole is integrated by the wiring part 7b.

  The vias 34a and 34b in FIG. 2 are formed as via arrays in each dielectric layer, but their individual shapes are provided so that the via hole is filled with a conductor and is electrically connected to the conductor on the bottom side. However, the vias applicable to the design by the CAD system of the present invention are not limited to this shape. The pads are formed on the solder-resist layers SR1 and SR2 as pad arrays, and the structure of each pad is a solder bump that is electrically connected to the lands 20a and 20b and the solder lands 10a and 10b. It is not limited to the structure consisting of 11a and 11b, and other pad structures can be applied to the design by the CAD system of the present invention.

  Hereinafter, the operation of the CAD system 100 will be described in detail. The drawing processing program 162a for starting the application program 162 of FIG. 2 can be executed, and the drawing screen 40 is displayed on the monitor 113 (FIG. 2) as shown in FIG. The application program 162 according to the present embodiment is constructed as draw graphic software as in the known CAD system, and is operated on the drawing screen 40 by operating the mouse 107 (hereinafter referred to as the element of the electronic circuit board 1). The drawing operation is advanced while individually inputting the graphic of FIG. In this embodiment, when the drawing screen 40 for a new drawing is launched, the drawing screen 40 corresponds to the main surface outline of the board to be designed / drawn based on the display data separately stored in the HDD 110 or the like. A quadrilateral reference region 51 and a graphic of a substrate element (in this embodiment, pads 53 and 55) that are normally formed on the substrate surface are displayed as default element graphics. In this case, a default element data storage unit that stores default element data in association with the product number is provided in the HDD 110, for example, and the product number is input by the keyboard 106 (or a soft button click on the screen by the mouse 107). If the default element data to be read is read out and displayed on the drawing screen, it is convenient because a figure such as the wiring portion 54 can be drawn and input immediately on a standardly formed board element.

  Here, the substrate to be designed is a package substrate or the like in which a plurality of wiring layers (conductor layers) are stacked via an insulating layer. Then, a plurality of drawing layers corresponding to the wiring layer to be formed are set on the drawing screen 40. Since these drawing layers (hereinafter also simply referred to as layers) overlap in FIG. 4, they cannot be visually determined. In addition, the figure written in each layer is overlaid on the drawing screen 40, but other figures can be displayed by displaying only the figure on a specific layer or changing the color, brightness, shading, fill pattern, etc. It is possible to make the display state different from the figure on the layer.

  FIG. 11 is a flowchart showing the flow of the drawing process by the drawing process program 162a. First, in S1, a layer to which an element is to be written is selected. This layer selection can be performed, for example, by clicking a soft button (not shown) for layer selection displayed on the screen with the mouse 107 (FIG. 2). The graphic elements that can be input are the above-described elements and via graphic elements for connecting elements between different layers. In S2 and S8, which one is selected is determined by command input. This command input can also be performed by a mouse click of a soft button (not shown) for selecting element input or via input.

  If element input is selected, the process proceeds from S2 to S3, and element drawing is performed. When drawing an element, a drawing tool is prepared for each type of element to be drawn, such as wiring drawing, pad, land, or surface conductor pattern drawing, as in known CAD system software. A drawing tool can also be selected by a mouse click of a drawing tool selection button (not shown) formed as a soft button on the screen. Then, when a desired drawing tool is selected, as shown in FIG. 4, a mouse click or drag (move the mouse while holding down the mouse button) while moving the pointer P indicating the drawing position by operating the mouse. Draw elements while combining operations. FIG. 4 shows a state where the figure of the wiring part connecting the pads 53 and 55 is drawn as an element.

  As shown in FIG. 6, every time one element is drawn, the element description data, which is graphic data, is associated with the element specifying data (for example, element code) and the layer specifying data (for example, layer number), It is stored in the drawing data memory 152g of FIG. For example, as shown in FIG. 5, the element description data defines the shape, size, and drawing position of the elements OB11, OB12, OB13, OB14, etc. on a coordinate plane set on the screen 40 (FIG. 4). Vector data, function data, or coordinates of specific reference points, and dimension defining data such as radius and length. For example, the element OB11 rotates in a predetermined direction (for example, clockwise) starting from the reference point A11 (x0, y0), and A11 (x1, y1), A11 (x2, y2), A11 (x3, y3) , A11 (x0, y0) are represented as a data set of coordinates of the end point position of each vector when the outline of the element is drawn by connecting the vectors in the order. The same applies to the element OB12. A circular element OB13 representing a pad, land, or the like is represented as a data set of its center coordinates C13 and radius r13. Further, for example, the element OB14 that is a figure of the wiring portion having a constant width W can be expressed as a data set of the coordinates of the start position B14 (X0, Y0) and the end position B14 (X1, Y1) and the line width W14. it can. In FIG. 5, the four elements OB11, OB12, OB13, and OB14 are all drawn on the same layer (M1).

  On the other hand, when the via input is selected in S8 of FIG. 11, the process proceeds to S9 and the via input process is performed. The via 34 connects the wirings of different wiring layers. In this embodiment, the graphic of the via 34 is input in units of via layers, and a via spanning a plurality of via layers is a plurality of vias. Are input in the form of stacked vias. Therefore, by designating a via layer to which a via is to be input, one unit via can be input. When three or more via layers are provided and a via that spans three or more via layers is input, an intermediate layer via is automatically generated by specifying a via start layer and a via end layer. It may be. As shown in FIG. 7, the data of the via graphic (which is also one of the board elements) includes via position data and layer specific information (via formation layer VLY ##) corresponding to the via layer. Are stored in the drawing data memory 152g in association with via specifying data (for example, via code).

  Returning to FIG. 11, when the element is drawn, the process proceeds to S4, and as shown in FIG. 9, the input element that partially overlaps (that is, is connected) with the input element OB12 in the same layer. It is determined whether or not OB11 exists. If it is No, it will progress to S5 further, and as shown in FIG. 10, it will be determined whether it is not connected to another element OB31 by the connection between different layers through via | veer VA11. If this is also No, the process proceeds to S6, where the element OB12 is set as a wiring net figure, for example, only the element specifying information is stored in the wiring net data registration memory 152i (FIG. 3) in the drawing data memory 152g. Number) and write it as new net data and register it.

  In S4 (see FIG. 8) or S5 (see FIG. 10) of FIG. 11, in both cases, the process proceeds to S7, in which the element is incorporated into the registered wiring net figure to which the element to be connected belongs, that is, a new process. The process of adding the element specifying data of the element drawn in (5) to the corresponding net data in the wiring net data registration memory 152i is performed (S4 → S7). In the case of connection by via, the via specifying data is also added to the net specifying information (S5 → S7). Thus, as shown in FIG. 3, in the wiring net data registration memory 152i, each net specifying information net1, net2,... And element specifying data OB11, OB12,. Net data in which the data VA11, VA12,... Are associated with each other is stored.

  On the other hand, as shown in FIG. 9, when elements overlapping between different layers occur, the element specifying data is not added to the overlapping net data. However, in S10 of FIG. 11, when a wiring net figure connected to each other by a newly input via graphic is generated, the process proceeds to S11, and the net data of those wiring net figures are merged. Is re-registered as net data of one wiring net figure. In this case, the net specific information may be left as one corresponding to one of the wiring net figures before integration, and the other may be deleted and treated as a missing number. You may make it provide net specific information.

  When the drawing operation is to be ended after repeating the drawing input of the elements and vias as described above, the process proceeds from S12 to S13, and the graphic data stored in the drawing data memory 152g, that is, the drawing data, A file name is given together with the net data in the wiring net data registration memory 152i, and it is written and saved in the drawing data file 163 of the HDD 110 (FIG. 2).

  The CAD data of each element (drawing target element) created as described above is converted into CAM data. The CAM data is a dimension of a manufacturing target element including an element or an additional element (for example, a solder bump formed on a solder land constituting the element) formed on the electronic circuit board 1 in a form associated with the element. , Shape and arrangement position, or jig for manufacturing a manufacturing target element (for example, a mask for exposing a via pattern, a wiring pattern, a gas vent hole pattern, or a solder paste coating mask used for forming a solder bump) ) Of graphic data for specifying the size, shape, and arrangement position of the part corresponding to the manufacturing object element.

  The present invention uses such a CAD system to draw a power supply or ground conduction path formed in a region immediately below an electronic component mounted on an electronic circuit board. In the following, a method for drawing and designing two types of conductive paths for power supply and ground formed in the region immediately below the electronic component 300 in the electronic circuit board 1 of FIG. 2 using the CAD system 100 will be described. Note that these power supply and ground conductor figures are different in display, for example, color scheme, line thickness, etc., so that they can be recognized on the screen as visually different figures during the drawing process. It is desirable to have it.

  First, the power supply and ground pad array portions formed on the first main surface of the electronic circuit board 1 are designed. These pad portions are connected to the terminals 301 of the electronic component 300 to be mounted on the electronic circuit board 1. Accordingly, in the design of the pad array unit, a predetermined pad conductor figure is drawn on the drawing layer so as to form an arrangement corresponding to the terminal arrangement of the electronic component 300. At this time, the CAD data of the drawn pad conductor figure is stored in the drawing data memory 152g, and the corresponding CAM data is stored in the CAM data memory 152m. In the present embodiment, the pad portions are the solder bumps 11a (for power supply) and 11b (for ground), and the solder lands 10a (for power supply) and 10b (for ground). Data is stored.

  Having determined the arrangement of the pad array portion, the arrangement of via arrays (via 34a (for power supply) and 34b (for ground)) formed in the third dielectric layer V3 immediately below the next is determined. These vias are formed so as to be electrically connected to the same type of pad portion. Therefore, a predetermined via figure is drawn on the via layer corresponding to the third dielectric layer V3 so that the vias 34a and 34b of the third dielectric layer V3 form an arrangement corresponding to the terminal arrangement of the pad portion. At this time, the CAD data of the via graphic is stored in the drawing data memory 152g, and the corresponding CAM data is stored in the CAM data memory 152m. In the case of the present embodiment, information related to the via figures 34a and 34b in the electronic circuit board of FIG. 2 is stored as CAD data and CAM data.

  FIGS. 12A and 12B represent typical examples of via graphic arrangements. In the via graphic shown in FIGS. 12A and 12B, the intersection of two different parallel line groups is set as a lattice point, and the via graphic is arranged on the lattice point. Specifically, the first parallel line group descending from the upper left to the lower right of the figure includes a first parallel line on which only a power supply via graphic (first type via graphic) is drawn, and a ground via graphic ( The second parallel lines on which only the second type via figure is drawn are alternately arranged, and has an intersection with the second parallel line group descending from the upper right to the lower left of the figure, and on the intersection A via figure is placed in Terminals of ordinary electronic components often have a grid-like arrangement rule as shown in FIGS. 12A and 12B, and therefore the via array is also as shown in FIGS. 12A and 12B. The dielectric layer is formed according to the arrangement rule. In the present embodiment, the terminals 301 of the electronic component 300 have a grid arrangement as shown in FIG. 12A, and therefore the via figure is drawn on the via layer in the arrangement shown in FIG. To do.

  When the arrangement of the vias on the outermost surface side of the electronic circuit board 1 (in this case, the vias 34 of the third dielectric layer V3) is determined, the through-hole conductor (through-hole conductor) formed in the core material 2 is next. ). The CAD system 100 stores a through-hole conductor graphic drawing processing program 162b as an application program 162 in the HDD 110. By executing this program, the through-hole conductor graphic is effectively arranged on the layer. be able to. Hereinafter, the through-hole conductor figure drawing program 162b will be described based on the flowchart shown in FIG. The board area to which this program is applied is the area where the core material 2 is formed immediately below the electronic component.

  First, in S100, it is determined whether or not a through-hole conductor figure has already been drawn on the through-hole conductor layer to be drawn. If the through-hole conductor has already been drawn, the process proceeds to S104 in order to continue drawing the through-hole conductor figure from the state where the drawing has been made. When drawing the first through-hole conductor figure on the through-hole conductor layer, the process proceeds to S101, and the process proceeds to the initial condition setting in S101.

  In S101, initial conditions are set. In this program, as an initial condition, a minimum value (hereinafter also referred to as a limit through-hole conductor interval) D is set for disposing different types of through holes adjacent to each other. When dissimilar through-hole conductors (power through-hole conductors and ground through-hole conductors) are placed adjacent to each other, electrical shorting and mechanical breakage of the board may occur between them. In order to prevent this, it is necessary to arrange these through-hole conductors at a predetermined interval. Since this interval is normally defined as a design rule for an electronic circuit board, the value may be input here. The input value is stored in the initial condition data memory 152a of the RAM 105.

  In step S102, a reference via is set. As shown in FIG. 14, the reference via graphic is one of the power supply via graphic (first type via graphic) 34a or the ground via graphic (second type via graphic) 34b drawn on the via layer. This is done by selecting one via shape. The CAD data of the selected reference via graphic is stored in the reference via data memory 152b of the RAM 105.

  Next, in S103, the limit through-hole conductor interval D set in S101 is read from the initial condition data memory, and as shown in FIG. 14, within the circular region having the radius D centered on the center position of the reference via graphic selected in S102. Is set on the via layer as a through-hole conductor prohibited region (through-hole conductor prohibited region). This through-hole conductor forbidden area is set to prohibit the through-hole from being drawn on the through-hole conductor layer that is directly below that area. This through-hole conductor prohibited area is stored in the prohibited area memory 152 c of the RAM 105.

  Next, in S104, as shown in FIG. 14, the through-hole conductor graphic 30 is generated in the region of the through-hole conductor layer immediately below the reference via graphic on the via layer. That is, the reference via graphic on the via layer is projected onto the through-hole conductor layer, and the through-hole conductor graphic is generated so that the center of the through-hole conductive graphic is positioned at the center of the projected reference via graphic. The generated through-hole conductor graphic is stored in the drawing data memory 152g of the RAM 105.

  Subsequently, in S105, as shown in FIG. 15, a type of via graphic different from the reference via graphic selected immediately before is selected as a new reference via graphic. At this time, if a via graphic of the same type as the via graphic selected immediately before is selected, a warning message or the like for warning that effect may be displayed on the screen to prompt the designer to change the selection. In this case, it is determined whether or not the type of the selected reference via graphic and the reference via graphic stored in the reference via data memory 152b are the same, and based on the result, a warning text is displayed and the selection via Make changes. At this time, the CAD data of the new reference via graphic whose selection is permitted is overwritten and stored in the reference via data memory 152b of the AM 105.

  In S106, all the through-hole conductor prohibited areas stored in the prohibited area memory 152c of the RAM 105 are read, and the newly selected reference via figure is in the through-hole conductor prohibited area (through-hole conductor prohibited area) on the via layer. It is determined whether or not there is. If it is determined that the reference via graphic selected in S105 is within the through-hole conductor prohibited area, the process returns to S105, the reference via graphic is selected again, and it is determined that it is outside the through-hole conductor prohibited area. In the case, proceed to S107.

  In S107, the limit through-hole conductor interval D is read from the initial condition data memory 152a, and as shown in FIG. 15, within the circular region with the radius D centered on the center position of the reference via figure newly selected in S105, A through-hole conductor prohibited area (through-hole conductor prohibited area) is additionally set on the via layer, and the process proceeds to S108. This newly added through-hole conductor prohibited area is stored in the prohibited area memory 152c so that the data of the through-hole conductor prohibited area already stored in the RAM 105 is not overwritten and stored. It is stored in the form added to the data up to.

  In S108, as shown in FIG. 15, a through-hole conductor figure of the same type as that of the reference via graphic is generated in the area of the through-hole conductor layer immediately below the reference via graphic newly set on the via layer. That is, the reference via graphic on the via layer is projected onto the through-hole conductor layer, and the through-hole conductor graphic is generated so that the center of the through-hole conductive graphic is positioned at the center of the projected reference via graphic. At this time, if the reference via figure is a via figure 34a for power supply, the through-hole conductor figure (first-type through-hole conductor figure) 30a for power supply is used. If the reference via figure is a via figure 34b for ground, the ground use figure is used. Through-hole conductor pattern (first-type through-hole conductor pattern) 30b is generated. The generated CAD data of the through-hole conductor figure is stored in the drawing data memory 152g of the RAM 105.

  In S109, in response to the completion of the drawing of the through-hole conductor figure in S108, it is selected whether or not to move to the drawing of the next through-hole conductor figure. If the drawing is moved to the next drawing, the process proceeds to S105 and does not move. If so, exit this program. As for the case of termination, although the CAD data of the drawn through-hole conductor figure is stored in the drawing data memory 152g of the RAM 105, it is not shown in the flowchart of FIG. In addition, the CAM data corresponding to the CAD data is saved in the CAM data file 164, and then the program is terminated.

  By repeating the drawing of the through-hole conductor figures 30a and 30b by the through-hole conductor figure drawing program 162b, the drawing of the through-hole figure is completed. The state in the upper diagram of FIG. 16 is a state in which S100 to S108 in the flowchart of FIG. 13 are processed in this order. Thereafter, the process returns to S105 in S109, and subsequently repeats S105 to S109, so that the reference via figure is sequentially selected on the via layer as shown in the center diagram of FIG. 16, and as a result, the lower diagram of FIG. As shown, a houndstooth-shaped through-hole conductor figure is drawn on the through-hole conductor layer. The hatched area shown in the middle diagram of FIG. 16 is a through-hole conductor prohibited area set in the process of drawing a through-hole conductor figure.

  Depending on the selection of the reference via graphic in S105, a through-hole conductor graphic having an arrangement different from that shown in FIG. 16 can be arranged as shown in the lower diagram of FIG. In the center diagram of FIG. 16, the reference via graphic selected at that time appears.

  It is also possible to draw a through-hole degree by a procedure different from the through-hole conductor figure drawing program 162b shown in FIG. FIG. 18 is a diagram showing a procedure for drawing a through-hole conductor figure by a procedure different from the above flowchart. In FIG. 18, the first selected reference via graphic 1 shown in the upper diagram and the next selected reference via graphic 2 (through-hole conductor prohibited region defined by the first reference via graphic 1 (FIG. A unit cell having a straight line connecting the outer via line) to the diagonal line is set as a diagonal line, and the unit rules are sequentially applied to the via graphic array as shown in the center of FIG. Then, through-hole conductor figures are sequentially generated in a region on the through-hole conductor layer immediately below the via figure formed at the end of the diagonal line of these unit lattices as shown in the lower figure of FIG. ing.

  After the through-hole conductor figure (through-hole conductor figure) is drawn by the above procedure, a conduction path for connecting the through-hole conductor and the via on the electronic component 300 side is drawn. At this time, the number of vias formed in the third dielectric layer and the through-hole conductor formed in the core material are different, and there are few through-hole conductors having a large diameter. Therefore, in the region between the core material 2 and the third dielectric layer V3, vias of the same type are merged (integrated) with the wiring so that the vias of the third dielectric layer and the through-hole conductors having a smaller number of vias are merged. And is designed to be connected. Hereinafter, a method for drawing a conduction path in the above region will be described.

  FIG. 19 is a flowchart showing the flow of the via integration processing program 162c for integrating the same type of vias in the region and connecting the vias with fewer vias than the vias. The board area to which this program is applied is an area directly below the electronic component and sandwiched between the electronic component and the core material.

  In S200, power supply via graphics (first-type via graphics) and ground via graphics (second-type via graphics) arranged in the third dielectric layer V3 as shown in FIG. Draw a wiring figure that integrates (via integrated wiring figure). In the case of the present embodiment, via figures drawn on the via layer as vias of the third dielectric layer V3 are arranged in a grid pattern as shown in FIG. More specifically, this via array is an array formed by arranging the same type of via figures in a straight line in the diagonal direction at equal intervals, and arranging the straight lines connecting the same type of vias by alternately changing the via type. is there. Therefore, in this program, linear wiring figures (via integrated wiring figures) La1 and Lb1 are formed along projected straight lines obtained by projecting straight lines connecting these types of vias onto the wiring layer (first wiring layer). Draw.

  Accordingly, in order to integrate the ground via 34b of the third dielectric layer V3 into the wiring layer (first wiring layer) corresponding to the second conductor layer M2, as shown in the upper diagram of FIG. A wiring graphic (second-type via integrated wiring graphic) Lb1 is drawn. Further, in order to integrate the ground via 34a of the third dielectric layer V3 into the wiring layer (first wiring layer) corresponding to the third conductor layer M3, the wiring as shown in the center diagram of FIG. A figure (first-type via integrated wiring figure) La1 is drawn. The CAD data of these wiring figures La1 and Lb1 is stored in the drawing data memory 152g of the RAM 105.

  Next, in S201, the core material 2 is arranged between the power through-hole figures (first-type through-hole conductor figures) arranged as shown in the lower diagram of FIG. The wiring figure (through-hole conductor integrated wiring figure) that integrates the seed through-hole conductor figures) is drawn. In the case of the present embodiment, the through-hole conductor figures drawn on the through-hole conductor layer as the through-hole conductors of the core material 2 are arranged in a grid pattern as shown in the lower diagram of FIG. In other words, this through-hole conductor figure is arranged in such a way that the same type of through-hole conductor figures are arranged in a straight line at equal intervals in the vertical direction of the figure, and the vertical lines connecting the same type of vias are alternated with different types of through-hole conductors. It is an array that is formed by arranging in place of. Therefore, in this program, a straight line connecting the same type of through-hole conductors is projected onto the wiring layer (second wiring layer), and linear wiring figures La2 and Lb2 are drawn along the projected straight line.

  Thereby, in order to integrate the ground through-hole conductor 30b of the core material 2 into the wiring layer (second wiring layer) corresponding to the first conductor layer M1, as shown in the lower diagram of FIG. A wiring pattern (second-type through-hole conductor integrated wiring pattern) Lb2 is drawn. Further, in order to integrate the through-hole conductor 30a for the power source of the core material 2 into the wiring layer (second wiring layer) corresponding to the first body layer M1, wiring as shown in the lower diagram of FIG. A figure (first-type through-hole conductor integrated wiring figure) La2 is drawn. The CAD data of these wiring figures La2 and Lb2 is stored in the drawing data memory 152g of the RAM 105.

  After performing the wiring drawing process as described above in S200 and S201, in S202, drawing is performed on the wiring layer (second wiring layer) corresponding to the first conductor layer M1 as shown in the upper diagram of FIG. Wiring figures La2, Lb2 drawn, wiring figure La1 drawn on the wiring layer (first wiring layer) corresponding to the second conductor layer M2, and wiring layer (first wiring layer) corresponding to the third conductor layer M3 When the wiring figure Lb1 drawn in FIG. 2 is projected on the same plane, the same kind of wiring figure, that is, the wiring figure La1 for power supply (first-type via integrated wiring figure) and La2 (first-type through-hole conductor integration) The intersections 33a and 33b of the wiring pattern Lb1 (second-type via integrated wiring pattern) and Lb2 (second-type through-hole conductor integrated wiring pattern) are calculated and the position coordinates are specified.

  In S203, the intersections 33a and 33b calculated in S202 are projected onto the via layer (intermediate layer) corresponding to the first dielectric layer V1, as shown in the center diagram of FIG. 21, and the projected point is used for integration. Via figures 34a and 34b are generated. Further, as shown in the lower diagram of FIG. 21, among the intersections calculated in S202, the intersection 33a of the power wiring wiring pattern is projected onto the via layer (intermediate layer) corresponding to the second dielectric layer V1. A power supply via figure 34a is generated around the projected point. Furthermore, since the ground via 34b of the third dielectric layer V3 is formed in the same manner in the second dielectric layer V2, the via pattern 34b for ground drawn on the via layer corresponding to the third conductor layer V3. Is projected onto the via layer corresponding to the second dielectric layer V2, and a similar via figure 34b is generated. At this time, the via figure based on the intersections 33a and 33b generated in the first dielectric layer V1 and the second dielectric layer V2 is a power supply via figure 34a according to the type of the two wiring figures forming the intersection. Whether it is a via graphic 34b for ground or not is determined. The CAD data of these via figures is stored in the drawing data memory 152g of the RAM 105. When the program is terminated, the CAD data stored in the drawing data memory is saved in the drawing data file 163 of the HDD 110, and the CAM data corresponding to the CAD data is saved in the CAM data file 164.

  In this embodiment, the ground wiring pattern is the wiring pattern Lb1 (wiring 7b in FIG. 2) as the second conductor layer M2, and the power wiring pattern La1 (wiring 7a in FIG. 2) is the third conductor layer M3. Is formed. In this case, equalization of the power supply and the ground is achieved by intentionally forming different types of wiring figures on different layers. In addition, the capacitance is increased so that a stable voltage can be supplied. The wiring figures Lb1 and La1 do not necessarily have to be formed in different layers, and may be formed in the same layer. In this case, it is necessary to arrange the wiring figures Lb1 and La1 so that they do not conduct, and a gap of a predetermined width defined in the design rule is provided between the two wiring figures, and the electrical short circuit and the mechanical board Care must be taken to prevent destruction.

  In addition, the power supply and ground conduction paths designed in this way are registered in the wiring net data registration memory 152i as two independent nets, and the board elements constituting each are stored as net data. To do.

  FIG. 22A is a diagram when the entire electronic circuit board 1 shown in FIG. 2 is viewed from the first main surface side. An electronic component 300 is disposed at the center of the electronic circuit board 1, and a capacitor 200 is disposed around the electronic component 300. FIG. 2B is a simplified view of the AA cross section of FIG. In the above embodiment, the region where the through-hole conductor is designed using the through-hole conductor graphic drawing program 162b is the region B in the figure. An area where vias and wiring are designed using the via integration processing program 162c is an area A in the figure. In the region immediately below the capacitor 200 in this figure, the through-hole conductor can be designed for the region E by the same program processing as that for the region B. Further, for the region D, vias and wirings can be designed by the same program processing as the region A.

Sectional drawing which shows an example of an electronic circuit board. The block diagram which shows the electrical constitution of the CAD system for electronic circuit boards of this invention. A map showing the contents of the wiring net data registration memory. Explanatory drawing of the operation process on the drawing screen in the CAD system for electronic circuit boards of this invention. Conceptual diagram of the element. The conceptual diagram of the CAD data of an element. The conceptual diagram of CAD data of a via figure. The 1st explanatory view of the overlapping connection state of an element. The 2nd explanatory view of the overlapping connection state of an element. Explanatory drawing of the via connection state of an element. The flowchart which shows the flow of a drawing process. Explanatory drawing which shows the arrangement | positioning state of a via figure. The flowchart which shows the flow of a through-hole conductor drawing process. Explanatory drawing which shows the drawing process of a through-hole conductor figure. The figure following FIG. The figure following FIG. FIG. 16 is an explanatory diagram illustrating a drawing process different from FIG. 16, following FIG. 15. Explanatory drawing of the drawing process of the through-hole conductor figure different from FIGS. The flowchart which shows the flow of a via integration process. Explanatory drawing explaining via integration. The figure following FIG. Schematic of the electronic circuit board shown in FIG.

Explanation of symbols

1 Electronic circuit board 2 Core material (core board)
30a, 30b Through-hole conductor (through-hole conductor), through-hole conductor pattern (through-hole conductor pattern)
34a, 34b Via, via graphic 101 CAD system for electronic circuit board 102 Input / output interface 103 CPU
105 RAM
106 Keyboard 107 Mouse (CAD data input means)
108 CD-ROM drive 110 Hard disk drive (storage means)
112 Computer body 120 CD-ROM
200 Capacitor 300 Electronic component (chip)

Claims (3)

On the first main surface on which the electronic component is mounted, a pad array for power supply and ground arranged corresponding to the arrangement of terminals of the electronic component,
Immediately below the pad array, a first type via array that conducts to one of the power supply and ground pad arrays and a second type via array that conducts to the other are arranged corresponding to the arrangement of the pad array. A core substrate on which a dielectric layer in which a via array is formed, a first type through-hole conductor conducting to the first type via array, and a second type through-hole conductor conducting to the second type via array; A CAD system for an electronic circuit board for designing an electronic circuit board having a kind of via array, the first kind of through-hole conductor, and a wiring layer connecting the second kind of via array and the second kind of through-hole conductor. ,
Via drawing means for drawing the first type via graphic and the second type via graphic forming the via array on a via layer;
Through-hole conductor drawing means for drawing the first-type through-hole conductor figure and the second-type through-hole conductor figure, which are fewer than the via figure, on the through-hole conductor layer;
A first type via integrated wiring figure that integrates a plurality of the first type via figures and a second type via integrated wiring figure that integrates the plurality of second type via figures are drawn on the first wiring layer, The first type through-hole conductor integrated wiring graphic that integrates the first type through-hole conductor graphic and the second type through-hole conductor integrated wiring graphic that integrates a plurality of the second type through-hole conductor graphic. Wiring drawing means for performing wiring drawing processing to be drawn on,
After the wiring drawing process, the via integrated wiring pattern and the through-hole are formed in an intermediate layer corresponding to a dielectric layer sandwiched between a wiring layer corresponding to the first wiring layer and a wiring layer corresponding to the second wiring layer. The hole conductor integrated wiring figure is projected, and by generating an integration via figure at the intersection of the projected same type of via integrated wiring figure and the through-hole conductor integrated wiring figure, the same kind of via figure and the A CAD system for an electronic circuit board, comprising: an integrated via generating means for connecting a through hole conductor figure.   A computer program that, when installed in a computer, causes the computer to function as each means constituting the CAD system for an electronic circuit board according to claim 1. In order to design a power supply or ground conductive path formed on an electronic circuit board to be obtained using the electronic circuit board CAD system according to claim 1, there is provided a board element constituting the conductive path. The via graphic, the through-hole conductor graphic, the wiring graphic, and the integration via graphic are displayed on the via layer, the through-hole conductor layer, the wiring layer, and the intermediate layer corresponding to the graphic as graphic data. An electronic circuit board design process that draws and modifies these figures as needed,
An electronic circuit board manufacturing process for manufacturing the board element of the electronic circuit board based on the graphic data of the electronic circuit board obtained by the board element design process;
The manufacturing method of the electronic circuit board characterized by including.

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