JPS6015947A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce coupling capacitance between a lower layer wiring and an upper layer wiring, which cross to each other, and to improve the performance of a LSI etc. processing analog signals by disposing a shielding film fixed at substrate potential between the wirings. CONSTITUTION:When forming a lower polycrystalline Si gate electrode in a laminated gate MOS transistor disposed in an integrated circuit, first wirings 3a-3c, etc. consisting of polycrystalline Si are formed simultaneously, and the surfaces of the first wirings 3a-3c, etc. are oxidized at the same time and second insulating films 4 are formed when the surface of the lower gate electrode is oxidized. When forming an upper polycrystalline Si gate electrode in the laminated gate MOS transistor, a conductor film 5 with first openings 6a-6c, etc. consisting of polycrystalline Si is shaped simultaneously, and the surface on the conductor film 5 is oxidized at the same time and a third insulating film 7 is formed when oxidizing the surface of a control gate electrode. When forming an electrode contact window in the transistor, etc., wiring contact windows 8a-8c, etc. are formed at the same time, and second wirings LA-LC in Al, etc. crossing with the first wirings 3a-3c are shaped simultaneously when forming the wirings in the integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a semiconductor device, and more particularly to a multilayer structure θ in a semiconductor device.

lbl between Takamichi Sakarai and Hiroteru When there are interconnections that intersect inside a semiconductor integrated circuit (LC), signals from one interconnect are transmitted to the other due to the coupling capacitance between the interconnects, causing noise (coupling).・Noise].In L3I that handles tenaro signals, this coupling noise is at least 1 to □ioo ioo to the signal level due to performance reasons.

(40 to 60 dB) or less.

However, recently, as LSIs have become larger, as shown in FIG. 1, the amplifier circuit A1. A large number of A, ,A, etc. are accumulated,
Internal wiring of the LSI as shown by a, b, c, etc.
As the number of locations where LIA, La, Lc, etc. intersect has increased, it has become difficult to suppress the coupling noise generated in these signal lines below the above tolerance (40 to 60 (dB)). It is coming.

In conventional multi-layer wiring layout, this is
This is because B, LC, etc. intersect with only the insulating film being used as a valve.

That is, in the conventional multilayer structure SSa, as shown in FIG. This causes a coupling appearance, and also causes an anti-coupling (decoupling) capacitance, ' dl + Cd2, between the valley wiring LIA, Ls and the substrate G through the first insulating film, for example, Ln. Due to the voltage change (dvn), the ratio of voltage reduction ((1v)) exerted on LA, that is, the cup link noise, becomes the 11th factor of the following equation.

dvAC (dvB Cd, -1cc And in normal LSI, the port width is 2 to 3 [μm]
For example, if the wiring length of LA is about 5 [chest], the area of the flat capacitor formed between wiring JA and LIB is about 100% of the total area of the person who wrote it. 8 degrees, but the thickness of the first insulating film and the second insulating film are approximately equal, and the thickness of the insulating film corresponding to Cd is the same as that of the first insulating film.
Since the A color line film 10 and the second 5 color line film S& are approximately twice the J♀ thickness of the insulating film (first insulating film) for EC, from the relationship with the above curve ratio, the flat plate Condition 1
Coupling capacitance U between wiring LA and LIH due to capacitor
C is approximately 1000 times the coupling capacitance of the wiring LA.

Traditional multilayer section like this? 111a for fMJa construction
Since the value of Cc per crossing point of 1 is already close to the allowable value, large 1. In SI, naturally, the coupling noise generated in the valley signal line becomes a large value exceeding the i/f valley value.

IcI OBJECT OF THE INVENTION In order to eliminate the above-mentioned problems, the present invention provides a multilayer wiring structure capable of reducing the coupling capacitance between opposite wirings. To improve LSI (7) performance.

ldl The structure of the invention, that is, the present invention provides a first wiring disposed on a semiconductor substrate via a first insulating film, and the first wiring. 5, a conductor film disposed on top of the conductor film via a second insulating film and to which a fixed potential is applied; and a second wiring that intersects the wiring of ff.
The present invention relates to a semiconductor device characterized in that the first wiring and the conductive film are made of a polycrystalline silicon film, and the second wiring is made of a pincushion.

Fe) Examples of the Invention The structure of the present invention and its formation method will be explained below with reference to the drawings.

Figure 3 is a schematic top view of the structure of the first man on the tree (i+, cross-sectional view of A-A grand celebration (ol, cross-sectional view of B-B arrow e)
FIG. 4 is a schematic diagram of the wiring connection portion and its vicinity in the embodiment.

The semiconductor device of the present invention, for example, as shown in FIG. 3, has a first barrier made of a field oxide film or the like formed on a silicon substrate 1 on which an integrated circuit (not shown) is formed.
On the i2, a polycrystalline silicon film (PA) of 2I41 with a high frost rate of about 3000 to 5o00cA) was extruded in one direction from these collector circuits. The first wiring 3a + 3b + 36 is connected to the first wiring 3a, 3b, 3c with a thickness of 2000 (A) made of silicon dioxide (Sr (J,)).
A second insulating film 4 having a thickness of approximately 3,000 to 5,000 (A) and having a high tolerance of approximately 3,000 to 5,000 (A) is formed on the surface on which the FB), and the first
A conductive film (shield film) 5 is provided which contacts the silicon substrate through a contact window (not shown) formed in the insulating film 2, and the first wirings 3a, 3b are connected to the conductive film 5. , 3c (area to which other wiring is to be connected) are exposed through the first openings 6a, 6b, 6c.
are provided on the surface of the conductor film 5 (the openings 6a, 6b
, 81 with a thickness of about 2000 (A) including the side surface of 6c
A third insulating film 7 made of a 0.02 film is formed, and a first arrangement g exposed in the first opening 5 a r 6 b + 6 C is formed.
The second absolute # on 3 a, 3 b, 3 c! @
4, a second opening (wiring contact window) 8a, 81) that exposes the entrance surface of the wiring (CP face).

8C are formed on the 6'rW body film 5 which covers the third insulating film 7, and the first openings 6a, 61. +, 6
c and second openings (wiring contact windows) 8a, 8b,
1st wiring 3a, 3b, 3c made by one person via 8c
For example, the wires ()8 to 81f, which are respectively jν and intersect with the first wiring along the surface periphery, are made of gold f′-↓ film such as aluminum (xl). Second wiring Lh
, Ln.

Lc is arranged.

That is, the semiconductor device d of the present invention has, for example, 7 as shown in 11 above.
61 polycrystalline silicon @()' First configuration consisting of A, l 3a, 31), 3C? j = that is, the lower layer wiring, and a further direct example is gold nine; the second wiring L A I which is 7λ from the opposite side
Between L n +Lc, etc., that is, the upper layer wiring, there is a 21-2 N! which is made of 8102 film on the ] part and the upper part. A multi-node 1 wiring on which a conductor film (shield film) 5 made of a second polycrystalline silicon film (Pn) is disposed via a third edge film 4 or a third insulating film 7, respectively, is connected to a 41-shield. It is characterized by the fact that

FIG. 4 shows an example of the state of the center of gravity contact part and its vicinity in the multilayer wiring structure according to Book 7. In the figure, 1 is the silicon substrate, and 2 is the first Kb edge. film,
3a and 3b are the first (1) 1JeJi (lower layer wiring), 4 is the second insulating film, 5 is the four-layer turtle film (shield film), 6b is the first opening, and 7 is the third insulating film. , 8b is the second opening (wiring contact window), and Ln is opening the second wiring (upper layer wiring).

To form the structure of the above embodiment, conventional stacked polycrystalline silicon gate formation techniques can be applied. In other words, the lower polycrystalline silicon gate electrode (a floating
When forming these integrated circuits, first wirings 3a, 3b, 3c, etc. made of polycrystalline silicon, which are drawn out from these integrated circuits to a wiring area usually provided at the periphery of the chip, are formed at the same time, and the surface of the lower gate electrode is At the same time as the oxidation, the surfaces of the first wirings 3a, 3b, 30, etc. are oxidized to form a second insulating film 4, and the upper polycrystalline silicon gate electrode (control gate) of the stacked gate MUSI-transistor is formed. At the same time, a first opening 5 made of polycrystalline silicon is formed.
A conductor film (shield film) 5 having a, 6b, 6c, etc. is formed, and the surface of the control gate electrode is oxidized.At the same time, the surface of the conductor film (shield film) 5 is oxidized to form a third insulator. After forming the film 7, and then forming the electrode contact window of the transistor etc., a contact 3C is formed at the same time.
Second wiring lines such as At that intersect with LA, LB, Lc
All you have to do is form. Therefore, forming the multilayer wiring structure of the present invention does not complicate the LSI manufacturing process. In addition to the upper HL b sU 2 film, the third insulating film 7 may be made of phosphosilicate glass (P8G)ljJ, which is disposed as an insulating film in M(JS) transistors, etc.; The platform is used to simultaneously apply the first layer to the PSG insulating film when forming electrode contact windows in M(JS) transistors, etc.
It is necessary to form a wiring contact window that exposes the wiring connection part of the wiring 3a + 3h I3C.

In the above embodiment, a polycrystalline silicon film was used for the first wiring (lower layer wiring) and the 4-layer film (shield film), and a metal film was used for the second wiring (upper layer wiring). A metal film may be used for the lower layer wiring and the shield film (and a polycrystalline silicon film may be used for the upper layer wiring. Also, metals other than upper B6HT (gold) may be used as the material for the lower layer wiring, shield gland, and lower layer wiring. ,
molybdenum.

Tungsten etc.], or a high melting point gold maple silicide such as molybdenum silicide, tungsten silicide:V, etc. may be used.

(fl As explained in detail about the invention, a shield film fixed to the substrate potential is described between the lower layer wiring and the upper layer wiring which intersect with each other. Since the electric field formed is cut off by the shield film, the coupling capacitance t(CC) between the lower layer wiring and the upper layer wiring at the difference portion is
becomes almost zero, and the cup link noise generated by each of the intersecting distributions B+ at the intersection becomes extremely small.

Therefore, the present invention particularly focuses on a human wave LSI that handles analog signals.
It is extremely effective for the market because of its performance.

[Brief explanation of the drawing]

Fig. 1 shows the place where the present invention can be applied; Fig. 2 is a horizontal schematic diagram of humanoid bS1; Fig. 2 is a tuyere for explaining cup link noise; and Fig. 3 is an embodiment of the structure of the present invention. Top schematic diagram (I,
A-A arrow sectional view HU+, B-B arrow view 1
FIG. 4 is a schematic view of the wiring section and its vicinity in an example of cough flow. In the figure, 1 is a silicon substrate, 2 is a first insulating film (field oxide film), and 3a , 3b, 3c are the first wiring (lower layer wiring), 4 is the second loquat film (sho. film), 5 is the 4-electrode film (shield arc), 6 a r 6
b +6C is the first hole, 7 is the third, 1× # membrane (Si
n, leg, 3 a r 8 b + 8C is the second opening (self-contact connection, LA, LIB, LC are the second wiring (upper layer wiring) opposite to the first wiring, P person is the first PB indicates the second polycrystalline silicon gland. Fig. 1 Fig. 2 Fig. 3 Fig. 4

Claims (1)

[Claims] fil A first wiring disposed on a semiconductor substrate with a first insulating film interposed therebetween, and a first wiring disposed above the first wiring via a second insulating film and fixed. It has eight turtle membranes to which a potential is applied, and a second wiring that is connected to the top of the non-electrical film with a third insulating film intersecting the first wiring. A semiconductor device characterized by: (2) The scope of the claim characterized in that the wiring and the electrocardioelectric body membrane of the upper 6C 1 are made of a multilayer one-piece silicon film doped with impurities, and the second self-wire of the upper 8C is made of gold cormorant film. 15
The semiconductor device according to item 1.