JPS63255941A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the stray capacitance of a crossing part of wiring in a multilayer interconnection structure having a flattened interlayer insulating film, by forming a recessed part in the base substrate of a lower wiring of the crossing part. CONSTITUTION:An interlayer insulating film 3 between a lower wiring layer 1 being a first layer wiring and an upper wiring layer 2 being a second layer wiring is flattened. At a crossing part of the first layer wiring and the second layer wiring, a recessed part 5 is formed in a semi-insulating semiconductor substrate 4 being a base substrate of the first layer wiring. The thickness of the interlayer insulating film on the lower layer wiring 1 is h2, and the upper surface of the lower wiring layer 1 becomes lower by the depth h3 of the recessed part 5. On the other hand, as the surface of the interlayer insulating film is flat, the thickness h4 of the interlayer insulating film at the crossing part becomes h2+h3. Therefor, the thickness is increased by h3, as compared with the usual structure, and the stray capacitance is decreased by that amount. Accordingly, a large stray capacitance does not generate at the crossing part of wirings.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a multilayer wiring structure.

[Conventional technology]

When forming wiring in a semiconductor integrated circuit, it is preferable that the level difference in the base of the wiring layer be small in order to prevent breakage at the level difference, etching residue, etc. For this reason, conventionally, especially in the case of multilayer wiring, steps on the surface of the lower layer wiring become an obstacle to the formation of the upper layer wiring, so in order to reduce this, bias sputtering, etchback, etc. In some cases, the surface of the insulating film was flattened.

[Problem that the invention seeks to solve]

However, in that case, as shown in FIG. 2, the thickness h2 of the interlayer insulating film 3 on the lower wiring layer 1 is smaller than the thickness hl in the area without the lower wiring layer 1, and the thickness is flat for simplicity. Assuming that the process is completely completed, the thickness of the lower wiring layer 1 will increase. h2=h, -h.

It becomes.

On the other hand, in order to increase the speed of integrated circuits, it is necessary to reduce wiring capacitance, and in the case of the structure shown in Figure 2, h
I want to make 2 as large as possible. However, in general, hl cannot be made very large due to film stress, dust generation, through-hole depth, etc., and ho cannot be made very small due to wiring resistance, etc. Therefore, the size of h2 is also limited, and there is a problem that a relatively large stray capacitance occurs at the wiring intersection.

[Means for solving problems]

The semiconductor integrated circuit of the present invention has a multilayer wiring structure in which a lower wiring layer and an upper wiring layer are provided with a glabella insulating film interposed therebetween, in which the interlayer insulating film is smaller than the level difference in the base layer. The surface is flattened, and a recess is provided in the base of the lower wiring layer at the intersection of the upper wiring layer and the lower wiring layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a perspective view of a semiconductor chip showing the main parts of a first embodiment of the present invention.

The interlayer insulating film 3 between the lower wiring layer 1, which is the first layer wiring, and the upper wiring layer 2, which is the second layer wiring above it, is flat. The surface is flat regardless of the layer wiring thickness (ho, etc.).

Also, 1st. In the part where the second layer wiring intersects, the first
A recess 5 is formed in a semi-insulating semiconductor substrate 4 that is a base for layer wiring. The thickness of the interlayer insulating film on the lower wiring layer 1 is h2, but at the intersection, the upper surface of the lower wiring layer 1 is also lowered by the depth h3 of the recess 5, while the surface of the insulating film between the eyebrows is flat. Therefore, the thickness h4 of the interlayer insulating film in this portion is h2+h3, which is increased by h3 compared to the conventional structure, and the stray capacitance is reduced accordingly.

Note that the formation of the recessed portion 5 can generally be used in combination with the step of carving alignment marks and the like on the semi-insulating semiconductor substrate 4, so there is no increase in the number of steps. Further, it is preferable that the width of the recess is larger than the width of the upper wiring layer.

FIG. 3 is a sectional view of a semiconductor chip showing the main parts of a second embodiment of the present invention. The lower wiring layer 1 is insulated 115!6
is formed on top of. The underlying recess 5 is formed by etching the insulating film 6 to provide an opening, thereby reducing its thickness h5.
is formed at a depth of

This embodiment has the advantage that no processing is required for the semi-insulating semiconductor substrate 4.

In the above embodiments, a semi-insulating substrate was used as a representative, but any substrate may be used as long as it serves as a substrate for the wiring layer.

〔Effect of the invention〕

As explained above, the present invention can reduce stray capacitance at the intersection by forming a recess in the base of the lower layer wiring at the interconnect intersection in a multilayer wiring structure without a flattened interlayer insulating film. This has the effect of increasing the speed of semiconductor integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a perspective view of a semiconductor chip showing the main parts of a first embodiment of the present invention, FIG. 2 is a perspective view of a semiconductor chip showing main parts of a conventional example, and FIG. 3 is a perspective view of a semiconductor chip showing main parts of a conventional example. 1 is a cross-sectional view of a semiconductor chip showing main parts of an embodiment. DESCRIPTION OF SYMBOLS 1... Lower wiring layer, 2... Upper wiring layer, 3... Interlayer insulating film, 4... Semi-insulating semiconductor substrate, 5... Concave portion, 6... Insulating film. Agent Patent Attorney Susumu Uchihara j-no1. \ゝ-1〆Z two-lipped ordinal flexion

Claims (1)

[Claims] In a semiconductor integrated circuit having a multilayer wiring structure in which a lower wiring layer and an upper wiring layer are provided with an interlayer insulating film interposed therebetween, the surface of the interlayer insulating film is planarized compared to the level difference in the underlying layer. and a recessed portion is provided in the base of the lower wiring layer at the intersection of the upper wiring layer and the lower wiring layer.