JPH09283630A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacitance between a clock trunk and a lower layer wiring below the clock trunk, by increasing the width of a portion crossing the clock trunk to be greater than an ordinary wiring width and increasing the thickness of an interlayer insulating film at the crossing portion. SOLUTION: In the case where a core has a diameter of 4mm, about 500 wirings cross below a clock trunk 14. In this case, if the width of the clock trunk 14 is set to 20μm and the width of a lower layer wiring 12 remains to be the ordinary wiring width of 0.8μm, the capacitance between the wirings is 3.0pF and the capacitance between the wiring and a board 10 is 1.02pF, thus making 4.02pF in total. However, if the width of the portion crossing the clock trunk is increased to 1.2μm, which is greater than the ordinary wiring width, the capacitance between the wirings is 2.5pF and the capacitance between the wiring and the board 10 is 0.85pF, thus making 3.35pF in total. Thus, the capacitance may be reduced by approximately 80%. By this reduction in capacitance, reduction in delay time in driving the clock trunk may be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a clock trunk suitable for use in a semiconductor device in which a wide clock trunk driven by a clock driver or the like is arranged on a lower layer wiring. Reduce capacity,
The present invention relates to a semiconductor device capable of reducing a clock delay time.

[0002]

2. Description of the Related Art In a semiconductor device such as a large scale integrated circuit (LSI), it is necessary to supply a clock to each place in a semiconductor chip, and a dedicated clock trunk is used. Since this clock trunk drives about 100 to 1000 flip-flops, skew or the like due to RC delay becomes a problem. Therefore, in order to reduce the resistance value, a wide wiring wider than the normal wiring width is formed.

[0003]

However, in the case of a wide wiring, although the resistance value is lowered, the wiring capacitance is increased on the contrary, and the clock delay time cannot be reduced.

As shown in FIG. 1, in general, the clock trunk 14 uses the uppermost metal layer having few wiring faults. This is an effective method because the capacity with the substrate 10 may be the smallest, but the lower layer wiring (metal) 1
The capacity of 2 does not change regardless of which layer is used. As described above, the clock trunk uses the wide metal in order to reduce the RC delay and the clock skew, so that the capacitance with the lower layer wiring 12 cannot be ignored.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to reduce the wiring capacitance between the clock trunk and the wiring in the lower layer thereof to reduce the clock delay time.

[0006]

According to the present invention, in a semiconductor device in which a wide clock trunk driven by a clock driver or the like is arranged on a lower layer wiring, the wiring of the lower layer of the clock trunk intersects with the clock trunk. The problem is solved by making the width of the portion wider than the normal wiring width and increasing the thickness of the interlayer insulating film at the intersection.

Generally, the capacitance between the upper layer metal and the lower layer metal is determined by the thickness of the interlayer insulating film between the two, rather than the area where they face each other. The thicker the interlayer insulating film, the smaller the capacitance can be made. There is a correlation between the thickness of the interlayer insulating film 16 and the width of the lower layer wiring 12, and as shown in FIG.
Is thicker in the right half, which is wider than in the left half, which is a normal wiring width. Therefore, by utilizing this property, the wiring capacity at the intersection can be reduced by widening the lower wiring only at the intersection of the wirings below the clock trunk.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

In this embodiment, as shown in FIG. 3, in a semiconductor device similar to the conventional one, the width of the portion of the wiring 12 in the lower layer of the clock trunk 14 that intersects with the clock trunk 14 is wider than the normal wiring width. However, the thickness of the interlayer insulating film at the intersection is increased.

[0010]

EXAMPLES Examples of the present invention applied to a two-layer wiring process will be described below. When the core has a diameter of 4 mm, about 500 wires cross under the clock trunk. In this case, the width of the clock trunk is 20
Assuming μm, the width of the lower layer wiring is the normal wiring width 0.8 μm
In the conventional example which remains the same, the capacitance between the wirings is 3.0 pF,
The capacitance with the substrate is 1.02 pF, for a total of 4.02 pF
However, according to the present invention, in the embodiment in which the width of the portion intersecting with the clock trunk is 1.2 μm, which is wider than the normal wiring width, the capacitance between wirings is 2.5 pF and the capacitance with the substrate is 0. .85 pF, a total of 3.35 pF,
It was confirmed that the capacity could be reduced by about 80%.

Due to this capacity reduction, the delay time for driving the clock trunk is 588 ps in the above-described embodiment, whereas it was 665 ps in the above-mentioned conventional example, and a delay reduction of about 88% can be realized.

In the above description, the present invention has been described by taking the case where the clock trunk is formed on the upper layer side of the two-layer wiring process as an example, but the present invention is not limited to this and three layers are applied. It is obvious that the present invention can be similarly applied to the case where the clock trunk is formed on the upper layer side other than the lowermost layer in the above wiring process.

[0013]

As described above, according to the present invention,
By increasing the thickness of the interlayer insulating film at the intersection of the clock trunk and the lower layer wiring, the wiring capacitance can be reduced and the clock delay time can be reduced.

[Brief description of drawings]

FIG. 1 is a plan view showing a main part of a conventional semiconductor chip in which a wide clock trunk is formed on a lower wiring of a normal wiring width.

FIG. 2 is a sectional view of a main part of a semiconductor chip for explaining the principle of the present invention.

FIG. 3 is a plan view of a main part of a semiconductor chip showing an embodiment of the present invention.

[Explanation of symbols]

 10 ... Substrate 12 ... Lower layer wiring 14 ... Clock trunk 16 ... Interlayer insulating film

Claims (1)

[Claims] 1. In a semiconductor device in which a wide-width clock trunk driven by a clock driver or the like is arranged on a lower layer wiring, the width of a portion of the lower layer wiring of the clock trunk intersecting the clock trunk is set to a normal wiring. A semiconductor device characterized in that it is wider than the width and the thickness of the interlayer insulating film at the intersection is increased.