JPH04364042A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To prevent wiring which has the multilayer structure of an aluminum layer and a tungsten silicide layer from short-circuiting caused by a lateral hillock for the metal wiring of a semiconductor integrated circuit device. CONSTITUTION:A lateral hillock is particularly generated in wide-width wiring. Dummy wiring 8 is provided between the wide wiring 7 and other wiring 6 adjacent to the wiring 7, the lateral hillock 5 is brought into contact with the dummy wiring 8 and short-circuit of the wiring 6 and 7 is prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, and more particularly to metal wiring structures.

0002

2. Description of the Related Art As semiconductor integrated circuit devices become more highly integrated and multi-functional, they are becoming increasingly finer. In particular, since metal wiring connecting each transistor on a semiconductor substrate occupies about half of the area within a semiconductor integrated circuit device, the wiring width and wiring spacing are becoming smaller, and the wiring is becoming more multi-layered.

Conventionally, metal wiring has used a metal layer mainly composed of aluminum, but recently copper has been added to aluminum to prevent migration such as electromigration and stress migration associated with miniaturization. Wiring having a laminated structure in which a silicide layer such as tungsten silicide is layered on an aluminum layer is used.

0004

[Problems to be Solved by the Invention] FIG. 2(a) is a plan view of a conventional wiring with miniaturization and anti-migration measures, and FIG. 2(b) is a cross-sectional view taken along the line A-A' in FIG. 2(a). be. As shown in FIGS. 2(a) and 2(b), a thick insulating film 2 is formed on a semiconductor substrate 1, and a laminated wiring structure consisting of a metal layer 3 mainly composed of aluminum and a tungsten silicide layer 4 is formed on top of the thick insulating film 2. has been done.

[0005] The above-mentioned layered structure wiring has a minimum wiring width of 1.5 μm.
Although it is possible to achieve a microfabrication of about 300 m, and has a structure that is highly resistant to migration, hillocks from the aluminum layer 3 in the lateral direction (so-called lateral There is a problem in that hillocks 5 occur and short circuits occur between wiring lines.

[0006] This phenomenon occurs because the aluminum layer 3 is normally suppressed by the tungsten silicide layer 4, so the hillocks 5 cannot grow upward but grow laterally, especially when the metal layer has a large area. It is more likely to occur in wires with minimum width, and less likely to occur in wiring with the minimum width. In other words, this does not occur when the minimum width wirings 6 are adjacent to each other with a minimum spacing as shown in FIG. Lateral hillock 5 may occur and there is a risk of short circuit.

An object of the present invention is to provide a semiconductor integrated circuit device that solves the above problems.

[0008]

[Means for Solving the Problems] In order to achieve the above object, a semiconductor integrated circuit device according to the present invention includes a metal layer mainly composed of aluminum and a silicide layer of a high melting point metal formed on a semiconductor substrate. When a wide first wiring is adjacent to a second wiring with a minimum spacing in the wiring having a laminated structure, there is a floating wiring with a minimum spacing between the first wiring and the second wiring. A dummy wiring for the state is provided.

[0009] Furthermore, the wide first wiring has a width of 3 μm.
The minimum interval is 1.5 μm or less.

0010

[Operation] In the semiconductor integrated circuit device of the present invention, when a relatively wide first wiring is adjacent to another second wiring with a minimum interval, there is a gap between the first wiring and the second wiring. , dummy wiring in a floating state is provided with a minimum interval, and the first
By bringing the lateral hillock generated from the wiring into contact with the dummy wiring, short-circuiting between the first wiring and the second wiring via the lateral hillock is prevented.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1(a) is a plan view showing an embodiment of the present invention, and FIG. 1(b) is a sectional view taken along the line AA' in FIG. 1(a).

In FIGS. 1A and 1B, a thick insulating film 2 is formed on a semiconductor substrate 1, and an aluminum layer 3 containing 1% silicon having a thickness of about 1.0 μm is formed on the insulating film 2 by, for example, sputtering. Then, a tungsten silicide layer 4 with a thickness of about 0.1 μm is formed, and a desired metal wiring is formed by well-known photolithography technology and anisotropic reactive ion etching.

The present invention is characterized in that dummy wiring 8 is provided in the metal wiring pattern. In other words, when a relatively wide wiring 7 that is likely to cause lateral hillocks 5 and another wiring 6 are adjacent to each other, the dummy wiring 8 can be provided between the wide wiring 7 and the other wiring 6. , short circuits between wirings due to lateral hillocks 5 are prevented. The wide wiring 7 in the present invention has a width of 3 μm or more, and a minimum interval of 1.5 μm or less.

[0015]

[Effects of the Invention] As explained above, the present invention solves the problem of short-circuiting of wires due to lateral hillocks by providing dummy wires along relatively wide wires where lateral hillocks are likely to occur. It is possible to provide a metal wiring having a laminated structure of an aluminum layer and a tungsten silicide layer with anti-migration measures suitable for miniaturization.

[Brief explanation of drawings]

FIG. 1(a) is a plan view showing one embodiment of the present invention;
b) is a sectional view taken along line AA' in FIG. 1(a).

2(a) is a plan view showing a conventional example, and FIG. 2(b) is a sectional view taken along the line AA' in FIG. 2(a).

[Explanation of symbols]

1 Semiconductor substrate 2 Insulating film 3 Aluminum layer 4 Tungsten silicide layer 5 Lateral hillock 6 Minimum width wiring 7 Wide wiring 8 Dummy wiring

Claims (2)

[Claims] 1. A wiring having a laminated structure of a metal layer mainly composed of aluminum and a silicide layer of a high melting point metal formed on a semiconductor substrate, wherein a wide first wiring is connected to a second wiring at a minimum interval. 1. A semiconductor integrated circuit device, characterized in that a dummy wiring in a floating state is provided with a minimum interval between the first wiring and the second wiring when the first wiring is adjacent to the second wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein the wide first wiring has a width of 3 μm or more and a minimum interval of 1.5 μm or less.