JP2762844B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring.

[0002]

2. Description of the Related Art A case of a four-layer aluminum wiring will be described as an example of a conventional semiconductor device having a multilayer wiring with reference to the drawings.

FIGS. 4A and 4B are a plan view and a cross-sectional view taken along line BB 'for explaining an example of a conventional semiconductor device.

[0004] As shown in FIGS.
The first-layer signal lines 103 on the Y grids 3 and 8 of the wirings formed by the wirings are the second-layer signal lines 104 on the X grids 2 and 4, respectively.
And the first through hole 105. X lattice 7
The upper second layer signal line 104 and the third layer signal line 1 on the Y lattice 7
07 is connected through a second through hole 108 to the Y grid 9
The upper third layer signal line 107 and the fourth layer signal line 1 on the X grid 5
10 is connected through a third through hole 109. X
The fourth layer signal lines 110 on the lattices 6 and 9 are passing signal lines.

Here, the four-layer aluminum wiring is formed on an interlayer insulating film 112 on a P-type silicon substrate 111, and interlayer insulating films 113, 114, 115 are provided between signal lines 103, 107, 110 of each layer. Are formed. The interlayer insulating film 113 is formed of a silicon oxide film formed by a plasma CVD method and a coated glass (spin-on glass) film using a silicon oxide film and a coated glass (spin-on glass) film in order to improve the step coverage of the upper signal line and prevent disconnection. Is flattened smoothly.

[0006]

In this conventional multi-layer wiring, the interlayer insulating film 113 is insufficiently flattened, so that a region where lower-layer wirings are dense, for example, as shown in FIG. , Y lattices 7 to 9 have an interlayer insulating film 1
13 is flattened, but the interlayer insulating film 113 is not sufficiently flattened in a region where the lower layer wiring is sparse, for example, a region from Y lattices 1 to 5 shown in FIG. There is a problem that the step coverage of the signal line 110 is deteriorated.

Further, as shown in FIG. 4 (b), when processing the fourth layer signal line 110, the first layer signal line 103 and the third layer signal line 107 on the Y lattice 3 overlap. And a portion where there is no signal line below the Y gratings 5 and 6, there is a step of 1.5 to 2.0 μm. Therefore, the focus is not focused at the time of alignment and exposure, and the photoresist film cannot be patterned. was there. Even if the photoresist film can be patterned, since the photoresist film in the portion of the Y lattice 3 is thinner than usual, the photoresist film disappears during dry etching and the fourth layer signal line 110 is also etched. There was a problem that it was broken.

As a means for solving this problem, there is a method of arranging dummy wirings in all areas where there is no wiring. However, in this method, the wiring capacitance, that is, the capacitance between adjacent wirings in the same layer and the wiring between lower wirings are used. In addition, there is a problem that the capacitance between the upper wirings increases and the circuit operation is slowed down.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device having a multilayer wiring in which wirings are arranged on a wiring grid set on a semiconductor substrate, at least one wiring layer other than the uppermost wiring layer of the multilayer wiring may be formed on an even grid or an odd grid. It has dummy wirings arranged and provided.

[0010]

Next, the present invention will be described with reference to the drawings.

FIGS. 1 and 2A and 2B are a plan view and a sectional view taken along the line AA 'shown in accordance with a design procedure for explaining a first embodiment of the present invention.

First, as shown in FIG. 1, before automatic wiring, a first-layer dummy wiring 101 is arranged on an even-numbered Y lattice, and a third-layer dummy wiring 102 is arranged on an odd-numbered lattice. .

Next, as shown in FIGS. 2 (a) and 2 (b),
The signal lines required to form the integrated circuit are wired. That is, the first layer signal lines 103 and 106 of the Y lattices 3 and 8 and the second layer signal lines 104 of the X lattices 2 and 4 are
05, the third layer signal lines 10 of the Y lattice 7
7 and the second layer signal line 104 of the X lattice 7 are connected by a second through hole 108, and the third layer signal line 107 of the Y lattice 9 and the fourth layer signal line 110 of the X lattice 5 are connected to the third through hole 10.
9 is connected. The fourth layer signal line 110 of the X grating 9 is a signal line passing in this plane.

In the Y grid 8, the first layer dummy wiring 101 is arranged before the automatic wiring. However, the first wiring is used as the first layer signal line 106 by the automatic wiring. As a result, one part becomes the first layer signal line 106 and the other part becomes the first layer dummy wiring 101 as it is. Similarly, a part of the third layer dummy wirings 102 of the Y lattices 7 and 9 is also used as the third layer signal line 107, and the other part is used as the dummy wiring 102.

Further, interlayer insulating films 113, 1 between the respective wiring layers are provided.
Reference numerals 14 and 115 are flattened by a silicon oxide film and a coated glass (spin-on glass) film formed by a plasma CVD method.
The first layer dummy wiring 101 is provided on both sides of the first wiring layer 03, the interlayer insulating film 113 on the first wiring layer is completely flattened, and the first layer dummy wiring 10
The first and first layer signal lines 106 are arranged at every other pitch, and although not completely flattened, become the interlayer insulating film 113 which is fairly well flattened.
Since the second and third layer signal lines 107 are arranged in the concave portions of the interlayer insulating film 114, the steps are reduced, and the interlayer insulating film 115 is almost completely flattened.

FIGS. 3A and 3B are plan views showing a design procedure for explaining a second embodiment of the present invention.

First, as shown in FIG. 3A, before the automatic wiring, the third layer dummy wiring 102
The second layer dummy wiring 301 is arranged in an odd lattice of the X lattice.

Next, as shown in FIG. 3B, signal lines are arranged in the same design procedure as in the first embodiment. In addition,
The connection state of the wiring is the same as that of the first embodiment, and a description thereof will be omitted.

Also in this embodiment, dummy wirings are arranged in the second and third wiring layers, so that the flatness of the interlayer insulating film can be greatly improved. In this embodiment, the first wiring layer has no dummy wiring. However, when the first wiring layer is applied in a transistor cell, the first wiring layer is often used for wiring in the transistor cell and is dense. Even if not used, the interlayer insulating film is flat, and the flattening is further improved.

[0020]

As described above, according to the present invention, the flatness of the interlayer insulating film is improved by forming the dummy wiring on the even grid or the odd grid, and the disconnection of the wiring due to the step of the upper wiring layer is performed. Has the effect of preventing

For example, in the four-layer wiring structure, the step between the high and low portions of the interlayer insulating film under the fourth aluminum wiring is 1.5 to 3.0 μm in the prior art, but is 0.5 μm or less. And the step coverage of the fourth layer wiring is almost 1
00%. In addition, since this step is reduced, the thickness of the photoresist film in the through-hole forming process and wiring forming process is almost uniform within the chip, eliminating the problem that the focus is partially out of focus during exposure, enabling fine patterning. And the number of wiring layers can be increased, that is, the conventional four-layer wiring can be replaced with six to eight-layer wiring.

The wiring capacity increases with the adjacent wiring due to the addition of the dummy wiring. However, when the dummy wiring is in all the lattices, the wiring capacity increases by about 20% compared to the case of the present invention. The increase in wiring capacitance is reduced to 5% or less.

Further, by changing the grid for arranging the dummy wiring between the upper layer wiring and the lower layer wiring, the unevenness of the interlayer insulating film can be reduced, and the flatness can be further improved.

As described above, according to the present invention, it is possible to further improve the miniaturization and multi-layering of the multilayer wiring by flattening the interlayer insulating film, and to suppress the increase in the wiring capacitance low, thereby achieving high integration and high performance of the semiconductor device. Can be achieved.

[Brief description of the drawings]

FIG. 1 is a plan view showing a design procedure for explaining a first embodiment of the present invention.

FIGS. 2A and 2B are a plan view and a sectional view taken along the line AA 'shown in accordance with a design procedure for explaining the first embodiment of the present invention. FIGS.

FIG. 3 is a plan view showing a design procedure for explaining a second embodiment of the present invention.

FIG. 4 is a plan view and a cross-sectional view taken along the line BB 'for explaining an example of a conventional semiconductor device.

[Explanation of symbols]

 101 first layer dummy wiring 102 third layer dummy wiring 103 first layer signal line 104 second layer signal line 105 first through hole 106 first layer signal line 107 third layer signal line 108 second through hole 109 third through Hole 110 fourth-layer signal line 111 p-type silicon substrate 112, 113, 114, 115 interlayer insulating film 301 second-layer dummy wiring

Claims (4)

(57) [Claims] In a semiconductor device having a multilayer wiring in which wirings are arranged on a wiring grid set on a semiconductor substrate, at least one wiring layer other than the uppermost wiring layer of the multilayer wiring has an even number of wiring layers. Alternatively, there is provided a semiconductor device having dummy wirings arranged on odd-numbered lattices. 2. A dummy wiring provided on an even grid of one wiring layer of a plurality of wiring layers, and a dummy wiring provided on an odd grid of another wiring layer different from the wiring layer. 2. The semiconductor device according to claim 1, comprising: 3. The wiring provided on the even-numbered wiring layer and the wiring provided on the odd-numbered wiring layer are arranged orthogonal to each other, and at least one of the even-numbered wiring layers and the odd-numbered wiring layer are provided. 2. The semiconductor device according to claim 1, further comprising a dummy wiring provided in at least one wiring layer of the first wiring layer. 4. The wiring provided in the even-numbered wiring layer and the wiring provided in the odd-numbered wiring layer are arranged orthogonal to each other, and the wiring of the even-numbered wiring layer and the odd-numbered wiring layer 2. The semiconductor device according to claim 1, further comprising a dummy wiring disposed only in one of the wiring layers.